mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-22 08:53:18 +07:00
[media] r820t: add IMR calibrate code
This code seems to calibrate I/Q phase and gain during the device initialization. This is done only once, and it doesn't seem to be needed to happen after resuming. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> Tested-by: Antti Palosaari <crope@iki.fi>
This commit is contained in:
Mauro Carvalho Chehab
parent
d75d538899
commit
25cf4d462a
@ -47,6 +47,8 @@
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*/
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#define REG_SHADOW_START 5
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#define NUM_REGS 27
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#define NUM_IMR 5
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#define IMR_TRIAL 9
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#define VER_NUM 49
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@ -66,6 +68,12 @@ enum xtal_cap_value {
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XTAL_HIGH_CAP_0P
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};
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struct r820t_sect_type {
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u8 phase_y;
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u8 gain_x;
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u16 value;
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};
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struct r820t_priv {
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struct list_head hybrid_tuner_instance_list;
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const struct r820t_config *cfg;
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@ -80,6 +88,8 @@ struct r820t_priv {
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u8 fil_cal_code;
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bool imr_done;
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struct r820t_sect_type imr_data[NUM_IMR];
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/* Store current mode */
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u32 delsys;
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enum v4l2_tuner_type type;
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@ -459,7 +469,7 @@ static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
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{
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const struct r820t_freq_range *range;
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int i, rc;
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u8 val;
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u8 val, reg08, reg09;
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/* Get the proper frequency range */
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freq = freq / 1000000;
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@ -507,17 +517,18 @@ static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
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if (rc < 0)
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return rc;
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/*
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* FIXME: the original driver has a logic there with preserves
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* gain/phase from registers 8 and 9 reading the data from the
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* registers before writing, if "IMF done". That code was sort of
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* commented there, as the flag is always false.
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*/
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rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
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if (priv->imr_done) {
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reg08 = priv->imr_data[range->imr_mem].gain_x;
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reg09 = priv->imr_data[range->imr_mem].phase_y;
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} else {
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reg08 = 0;
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reg09 = 0;
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}
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rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f);
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if (rc < 0)
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return rc;
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rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
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rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f);
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return rc;
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}
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@ -1383,6 +1394,667 @@ static int r820t_xtal_check(struct r820t_priv *priv)
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return r820t_xtal_capacitor[i][1];
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}
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static int r820t_imr_prepare(struct r820t_priv *priv)
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{
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int rc;
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/* Initialize the shadow registers */
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memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
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/* lna off (air-in off) */
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rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20);
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if (rc < 0)
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return rc;
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/* mixer gain mode = manual */
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rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
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if (rc < 0)
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return rc;
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/* filter corner = lowest */
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rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f);
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if (rc < 0)
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return rc;
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/* filter bw=+2cap, hp=5M */
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rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f);
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if (rc < 0)
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return rc;
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/* adc=on, vga code mode, gain = 26.5dB */
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rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
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if (rc < 0)
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return rc;
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/* ring clk = on */
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rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08);
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if (rc < 0)
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return rc;
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/* ring power = on */
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rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10);
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if (rc < 0)
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return rc;
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/* from ring = ring pll in */
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rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02);
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if (rc < 0)
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return rc;
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/* sw_pdect = det3 */
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rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80);
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if (rc < 0)
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return rc;
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/* Set filt_3dB */
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rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20);
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return rc;
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}
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static int r820t_multi_read(struct r820t_priv *priv)
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{
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int rc, i;
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u8 data[2], min = 0, max = 255, sum = 0;
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usleep_range(5000, 6000);
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for (i = 0; i < 6; i++) {
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rc = r820t_read(priv, 0x00, data, sizeof(data));
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if (rc < 0)
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return rc;
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sum += data[1];
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if (data[1] < min)
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min = data[1];
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if (data[1] > max)
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max = data[1];
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}
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rc = sum - max - min;
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return rc;
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}
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static int r820t_imr_cross(struct r820t_priv *priv,
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struct r820t_sect_type iq_point[3],
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u8 *x_direct)
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{
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struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */
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struct r820t_sect_type tmp;
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int i, rc;
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u8 reg08, reg09;
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reg08 = r820t_read_cache_reg(priv, 8) & 0xc0;
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reg09 = r820t_read_cache_reg(priv, 9) & 0xc0;
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tmp.gain_x = 0;
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tmp.phase_y = 0;
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tmp.value = 255;
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for (i = 0; i < 5; i++) {
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switch (i) {
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case 0:
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cross[i].gain_x = reg08;
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cross[i].phase_y = reg09;
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break;
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case 1:
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cross[i].gain_x = reg08; /* 0 */
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cross[i].phase_y = reg09 + 1; /* Q-1 */
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break;
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case 2:
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cross[i].gain_x = reg08; /* 0 */
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cross[i].phase_y = (reg09 | 0x20) + 1; /* I-1 */
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break;
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case 3:
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cross[i].gain_x = reg08 + 1; /* Q-1 */
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cross[i].phase_y = reg09;
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break;
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default:
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cross[i].gain_x = (reg08 | 0x20) + 1; /* I-1 */
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cross[i].phase_y = reg09;
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}
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rc = r820t_write_reg(priv, 0x08, cross[i].gain_x);
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if (rc < 0)
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return rc;
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rc = r820t_write_reg(priv, 0x09, cross[i].phase_y);
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if (rc < 0)
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return rc;
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rc = r820t_multi_read(priv);
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if (rc < 0)
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return rc;
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cross[i].value = rc;
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if (cross[i].value < tmp.value)
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memcpy(&tmp, &cross[i], sizeof(tmp));
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}
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if ((tmp.phase_y & 0x1f) == 1) { /* y-direction */
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*x_direct = 0;
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iq_point[0] = cross[0];
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iq_point[1] = cross[1];
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iq_point[2] = cross[2];
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} else { /* (0,0) or x-direction */
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*x_direct = 1;
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iq_point[0] = cross[0];
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iq_point[1] = cross[3];
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iq_point[2] = cross[4];
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}
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return 0;
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}
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static void r820t_compre_cor(struct r820t_sect_type iq[3])
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{
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int i;
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for (i = 3; i > 0; i--) {
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if (iq[0].value > iq[i - 1].value)
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swap(iq[0], iq[i - 1]);
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}
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}
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static int r820t_compre_step(struct r820t_priv *priv,
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struct r820t_sect_type iq[3], u8 reg)
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{
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int rc;
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struct r820t_sect_type tmp;
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/*
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* Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare
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* with min value:
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* new < min => update to min and continue
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* new > min => Exit
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*/
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/* min value already saved in iq[0] */
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tmp.phase_y = iq[0].phase_y;
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tmp.gain_x = iq[0].gain_x;
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while (((tmp.gain_x & 0x1f) < IMR_TRIAL) &&
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((tmp.phase_y & 0x1f) < IMR_TRIAL)) {
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if (reg == 0x08)
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tmp.gain_x++;
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else
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tmp.phase_y++;
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rc = r820t_write_reg(priv, 0x08, tmp.gain_x);
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if (rc < 0)
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return rc;
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rc = r820t_write_reg(priv, 0x09, tmp.phase_y);
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if (rc < 0)
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return rc;
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rc = r820t_multi_read(priv);
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if (rc < 0)
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return rc;
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tmp.value = rc;
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if (tmp.value <= iq[0].value) {
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iq[0].gain_x = tmp.gain_x;
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iq[0].phase_y = tmp.phase_y;
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iq[0].value = tmp.value;
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} else {
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return 0;
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}
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}
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return 0;
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}
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static int r820t_iq_tree(struct r820t_priv *priv,
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struct r820t_sect_type iq[3],
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u8 fix_val, u8 var_val, u8 fix_reg)
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{
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int rc, i;
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u8 tmp, var_reg;
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/*
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* record IMC results by input gain/phase location then adjust
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* gain or phase positive 1 step and negtive 1 step,
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* both record results
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*/
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if (fix_reg == 0x08)
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var_reg = 0x09;
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else
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var_reg = 0x08;
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for (i = 0; i < 3; i++) {
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rc = r820t_write_reg(priv, fix_reg, fix_val);
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if (rc < 0)
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return rc;
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rc = r820t_write_reg(priv, var_reg, var_val);
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if (rc < 0)
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return rc;
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rc = r820t_multi_read(priv);
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if (rc < 0)
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return rc;
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iq[i].value = rc;
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if (fix_reg == 0x08) {
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iq[i].gain_x = fix_val;
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iq[i].phase_y = var_val;
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} else {
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iq[i].phase_y = fix_val;
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iq[i].gain_x = var_val;
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}
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if (i == 0) { /* try right-side point */
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var_val++;
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} else if (i == 1) { /* try left-side point */
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/* if absolute location is 1, change I/Q direction */
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if ((var_val & 0x1f) < 0x02) {
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tmp = 2 - (var_val & 0x1f);
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/* b[5]:I/Q selection. 0:Q-path, 1:I-path */
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if (var_val & 0x20) {
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var_val &= 0xc0;
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var_val |= tmp;
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} else {
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var_val |= 0x20 | tmp;
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}
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} else {
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var_val -= 2;
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}
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}
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}
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return 0;
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}
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static int r820t_section(struct r820t_priv *priv,
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struct r820t_sect_type *iq_point)
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{
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int rc;
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struct r820t_sect_type compare_iq[3], compare_bet[3];
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/* Try X-1 column and save min result to compare_bet[0] */
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if (!(iq_point->gain_x & 0x1f))
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compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1; /* Q-path, Gain=1 */
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else
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compare_iq[0].gain_x = iq_point->gain_x - 1; /* left point */
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compare_iq[0].phase_y = iq_point->phase_y;
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/* y-direction */
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rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
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compare_iq[0].phase_y, 0x08);
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if (rc < 0)
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return rc;
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r820t_compre_cor(compare_iq);
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compare_bet[0] = compare_iq[0];
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/* Try X column and save min result to compare_bet[1] */
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compare_iq[0].gain_x = iq_point->gain_x;
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compare_iq[0].phase_y = iq_point->phase_y;
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rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
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compare_iq[0].phase_y, 0x08);
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if (rc < 0)
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return rc;
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r820t_compre_cor(compare_iq);
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compare_bet[1] = compare_iq[0];
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/* Try X+1 column and save min result to compare_bet[2] */
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if ((iq_point->gain_x & 0x1f) == 0x00)
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compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1; /* I-path, Gain=1 */
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else
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compare_iq[0].gain_x = iq_point->gain_x + 1;
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compare_iq[0].phase_y = iq_point->phase_y;
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rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
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compare_iq[0].phase_y, 0x08);
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if (rc < 0)
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return rc;
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r820t_compre_cor(compare_iq);
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compare_bet[2] = compare_iq[0];
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r820t_compre_cor(compare_bet);
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*iq_point = compare_bet[0];
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return 0;
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}
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static int r820t_vga_adjust(struct r820t_priv *priv)
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{
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int rc;
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u8 vga_count;
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/* increase vga power to let image significant */
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for (vga_count = 12; vga_count < 16; vga_count++) {
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rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f);
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if (rc < 0)
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return rc;
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usleep_range(10000, 11000);
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rc = r820t_multi_read(priv);
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if (rc < 0)
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return rc;
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if (rc > 40 * 4)
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break;
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}
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return 0;
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}
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static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
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{
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struct r820t_sect_type compare_iq[3];
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int rc;
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u8 x_direction = 0; /* 1:x, 0:y */
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u8 dir_reg, other_reg;
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r820t_vga_adjust(priv);
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rc = r820t_imr_cross(priv, compare_iq, &x_direction);
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if (rc < 0)
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return rc;
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if (x_direction == 1) {
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dir_reg = 0x08;
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other_reg = 0x09;
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} else {
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dir_reg = 0x09;
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other_reg = 0x08;
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}
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/* compare and find min of 3 points. determine i/q direction */
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r820t_compre_cor(compare_iq);
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/* increase step to find min value of this direction */
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rc = r820t_compre_step(priv, compare_iq, dir_reg);
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if (rc < 0)
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return rc;
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/* the other direction */
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rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
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compare_iq[0].phase_y, dir_reg);
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if (rc < 0)
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return rc;
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/* compare and find min of 3 points. determine i/q direction */
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r820t_compre_cor(compare_iq);
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/* increase step to find min value on this direction */
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rc = r820t_compre_step(priv, compare_iq, other_reg);
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if (rc < 0)
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return rc;
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/* check 3 points again */
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rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
|
||||
compare_iq[0].phase_y, other_reg);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
r820t_compre_cor(compare_iq);
|
||||
|
||||
/* section-9 check */
|
||||
rc = r820t_section(priv, compare_iq);
|
||||
|
||||
*iq_pont = compare_iq[0];
|
||||
|
||||
/* reset gain/phase control setting */
|
||||
rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
|
||||
{
|
||||
int rc;
|
||||
|
||||
r820t_vga_adjust(priv);
|
||||
|
||||
/*
|
||||
* search surrounding points from previous point
|
||||
* try (x-1), (x), (x+1) columns, and find min IMR result point
|
||||
*/
|
||||
rc = r820t_section(priv, iq_pont);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag)
|
||||
{
|
||||
struct r820t_sect_type imr_point;
|
||||
int rc;
|
||||
u32 ring_vco, ring_freq, ring_ref;
|
||||
u8 n_ring, n;
|
||||
int reg18, reg19, reg1f;
|
||||
|
||||
if (priv->cfg->xtal > 24000000)
|
||||
ring_ref = priv->cfg->xtal / 2;
|
||||
else
|
||||
ring_ref = priv->cfg->xtal;
|
||||
|
||||
for (n = 0; n < 16; n++) {
|
||||
if ((16 + n) * 8 * ring_ref >= 3100000) {
|
||||
n_ring = n;
|
||||
break;
|
||||
}
|
||||
|
||||
/* n_ring not found */
|
||||
if (n == 15)
|
||||
n_ring = n;
|
||||
}
|
||||
|
||||
reg18 = r820t_read_cache_reg(priv, 0x18);
|
||||
reg19 = r820t_read_cache_reg(priv, 0x19);
|
||||
reg1f = r820t_read_cache_reg(priv, 0x1f);
|
||||
|
||||
reg18 &= 0xf0; /* set ring[3:0] */
|
||||
reg18 |= n_ring;
|
||||
|
||||
ring_vco = (16 + n_ring) * 8 * ring_ref;
|
||||
|
||||
reg18 &= 0xdf; /* clear ring_se23 */
|
||||
reg19 &= 0xfc; /* clear ring_seldiv */
|
||||
reg1f &= 0xfc; /* clear ring_att */
|
||||
|
||||
switch (imr_mem) {
|
||||
case 0:
|
||||
ring_freq = ring_vco / 48;
|
||||
reg18 |= 0x20; /* ring_se23 = 1 */
|
||||
reg19 |= 0x03; /* ring_seldiv = 3 */
|
||||
reg1f |= 0x02; /* ring_att 10 */
|
||||
break;
|
||||
case 1:
|
||||
ring_freq = ring_vco / 16;
|
||||
reg18 |= 0x00; /* ring_se23 = 0 */
|
||||
reg19 |= 0x02; /* ring_seldiv = 2 */
|
||||
reg1f |= 0x00; /* pw_ring 00 */
|
||||
break;
|
||||
case 2:
|
||||
ring_freq = ring_vco / 8;
|
||||
reg18 |= 0x00; /* ring_se23 = 0 */
|
||||
reg19 |= 0x01; /* ring_seldiv = 1 */
|
||||
reg1f |= 0x03; /* pw_ring 11 */
|
||||
break;
|
||||
case 3:
|
||||
ring_freq = ring_vco / 6;
|
||||
reg18 |= 0x20; /* ring_se23 = 1 */
|
||||
reg19 |= 0x00; /* ring_seldiv = 0 */
|
||||
reg1f |= 0x03; /* pw_ring 11 */
|
||||
break;
|
||||
case 4:
|
||||
ring_freq = ring_vco / 4;
|
||||
reg18 |= 0x00; /* ring_se23 = 0 */
|
||||
reg19 |= 0x00; /* ring_seldiv = 0 */
|
||||
reg1f |= 0x01; /* pw_ring 01 */
|
||||
break;
|
||||
default:
|
||||
ring_freq = ring_vco / 4;
|
||||
reg18 |= 0x00; /* ring_se23 = 0 */
|
||||
reg19 |= 0x00; /* ring_seldiv = 0 */
|
||||
reg1f |= 0x01; /* pw_ring 01 */
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
/* write pw_ring, n_ring, ringdiv2 registers */
|
||||
|
||||
/* n_ring, ring_se23 */
|
||||
rc = r820t_write_reg(priv, 0x18, reg18);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
/* ring_sediv */
|
||||
rc = r820t_write_reg(priv, 0x19, reg19);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
/* pw_ring */
|
||||
rc = r820t_write_reg(priv, 0x1f, reg1f);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
/* mux input freq ~ rf_in freq */
|
||||
rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV,
|
||||
(ring_freq - 5300) * 1000);
|
||||
if (!priv->has_lock)
|
||||
rc = -EINVAL;
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
if (im_flag) {
|
||||
rc = r820t_iq(priv, &imr_point);
|
||||
} else {
|
||||
imr_point.gain_x = priv->imr_data[3].gain_x;
|
||||
imr_point.phase_y = priv->imr_data[3].phase_y;
|
||||
imr_point.value = priv->imr_data[3].value;
|
||||
|
||||
rc = r820t_f_imr(priv, &imr_point);
|
||||
}
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
/* save IMR value */
|
||||
switch (imr_mem) {
|
||||
case 0:
|
||||
priv->imr_data[0].gain_x = imr_point.gain_x;
|
||||
priv->imr_data[0].phase_y = imr_point.phase_y;
|
||||
priv->imr_data[0].value = imr_point.value;
|
||||
break;
|
||||
case 1:
|
||||
priv->imr_data[1].gain_x = imr_point.gain_x;
|
||||
priv->imr_data[1].phase_y = imr_point.phase_y;
|
||||
priv->imr_data[1].value = imr_point.value;
|
||||
break;
|
||||
case 2:
|
||||
priv->imr_data[2].gain_x = imr_point.gain_x;
|
||||
priv->imr_data[2].phase_y = imr_point.phase_y;
|
||||
priv->imr_data[2].value = imr_point.value;
|
||||
break;
|
||||
case 3:
|
||||
priv->imr_data[3].gain_x = imr_point.gain_x;
|
||||
priv->imr_data[3].phase_y = imr_point.phase_y;
|
||||
priv->imr_data[3].value = imr_point.value;
|
||||
break;
|
||||
case 4:
|
||||
priv->imr_data[4].gain_x = imr_point.gain_x;
|
||||
priv->imr_data[4].phase_y = imr_point.phase_y;
|
||||
priv->imr_data[4].value = imr_point.value;
|
||||
break;
|
||||
default:
|
||||
priv->imr_data[4].gain_x = imr_point.gain_x;
|
||||
priv->imr_data[4].phase_y = imr_point.phase_y;
|
||||
priv->imr_data[4].value = imr_point.value;
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int r820t_imr_callibrate(struct r820t_priv *priv)
|
||||
{
|
||||
int rc, i;
|
||||
int xtal_cap = 0;
|
||||
|
||||
if (priv->imr_done)
|
||||
return 0;
|
||||
|
||||
/* Initialize registers */
|
||||
rc = r820t_write(priv, 0x05,
|
||||
r820t_init_array, sizeof(r820t_init_array));
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
/* Detect Xtal capacitance */
|
||||
if ((priv->cfg->rafael_chip == CHIP_R820T) ||
|
||||
(priv->cfg->rafael_chip == CHIP_R828S) ||
|
||||
(priv->cfg->rafael_chip == CHIP_R820C)) {
|
||||
priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
|
||||
} else {
|
||||
for (i = 0; i < 3; i++) {
|
||||
rc = r820t_xtal_check(priv);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
if (!i || rc > xtal_cap)
|
||||
xtal_cap = rc;
|
||||
}
|
||||
priv->xtal_cap_sel = xtal_cap;
|
||||
}
|
||||
|
||||
/* Initialize registers */
|
||||
rc = r820t_write(priv, 0x05,
|
||||
r820t_init_array, sizeof(r820t_init_array));
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
rc = r820t_imr_prepare(priv);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
rc = r820t_imr(priv, 3, true);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
rc = r820t_imr(priv, 1, false);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
rc = r820t_imr(priv, 0, false);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
rc = r820t_imr(priv, 2, false);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
rc = r820t_imr(priv, 4, false);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
priv->imr_done = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* r820t frontend operations and tuner attach code
|
||||
*
|
||||
@ -1392,8 +2064,7 @@ static int r820t_xtal_check(struct r820t_priv *priv)
|
||||
static int r820t_init(struct dvb_frontend *fe)
|
||||
{
|
||||
struct r820t_priv *priv = fe->tuner_priv;
|
||||
int rc, i;
|
||||
int xtal_cap = 0;
|
||||
int rc;
|
||||
|
||||
tuner_dbg("%s:\n", __func__);
|
||||
|
||||
@ -1401,20 +2072,9 @@ static int r820t_init(struct dvb_frontend *fe)
|
||||
if (fe->ops.i2c_gate_ctrl)
|
||||
fe->ops.i2c_gate_ctrl(fe, 1);
|
||||
|
||||
if ((priv->cfg->rafael_chip == CHIP_R820T) ||
|
||||
(priv->cfg->rafael_chip == CHIP_R828S) ||
|
||||
(priv->cfg->rafael_chip == CHIP_R820C)) {
|
||||
priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
|
||||
} else {
|
||||
for (i = 0; i < 3; i++) {
|
||||
rc = r820t_xtal_check(priv);
|
||||
if (rc < 0)
|
||||
goto err;
|
||||
if (!i || rc > xtal_cap)
|
||||
xtal_cap = rc;
|
||||
}
|
||||
priv->xtal_cap_sel = xtal_cap;
|
||||
}
|
||||
rc = r820t_imr_callibrate(priv);
|
||||
if (rc < 0)
|
||||
goto err;
|
||||
|
||||
/* Initialize registers */
|
||||
rc = r820t_write(priv, 0x05,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user