AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2025-01-24 15:29:28 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

Merge branch 'devel' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel-stable

Browse Source
This commit is contained in:
Russell King 2010-12-22 22:46:24 +00:00
commit 25cf0398bd
683 changed files with 10444 additions and 6830 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

83
Documentation/ABI/testing/sysfs-bus-rbd Normal file
View File

@ -0,0 +1,83 @@
What: /sys/bus/rbd/
Date: November 2010
Contact: Yehuda Sadeh <yehuda@hq.newdream.net>,
Sage Weil <sage@newdream.net>
Description:
Being used for adding and removing rbd block devices.
Usage: <mon ip addr> <options> <pool name> <rbd image name> [snap name]
$ echo "192.168.0.1 name=admin rbd foo" > /sys/bus/rbd/add
The snapshot name can be "-" or omitted to map the image read/write. A <dev-id>
will be assigned for any registered block device. If snapshot is used, it will
be mapped read-only.
Removal of a device:
$ echo <dev-id> > /sys/bus/rbd/remove
Entries under /sys/bus/rbd/devices/<dev-id>/
--------------------------------------------
client_id
The ceph unique client id that was assigned for this specific session.
major
The block device major number.
name
The name of the rbd image.
pool
The pool where this rbd image resides. The pool-name pair is unique
per rados system.
size
The size (in bytes) of the mapped block device.
refresh
Writing to this file will reread the image header data and set
all relevant datastructures accordingly.
current_snap
The current snapshot for which the device is mapped.
create_snap
Create a snapshot:
$ echo <snap-name> > /sys/bus/rbd/devices/<dev-id>/snap_create
rollback_snap
Rolls back data to the specified snapshot. This goes over the entire
list of rados blocks and sends a rollback command to each.
$ echo <snap-name> > /sys/bus/rbd/devices/<dev-id>/snap_rollback
snap_*
A directory per each snapshot
Entries under /sys/bus/rbd/devices/<dev-id>/snap_<snap-name>
-------------------------------------------------------------
id
The rados internal snapshot id assigned for this snapshot
size
The size of the image when this snapshot was taken.

16
Documentation/ABI/testing/sysfs-platform-asus-laptop
View File

@ -47,6 +47,20 @@ Date: January 2007
KernelVersion: 2.6.20
Contact: "Corentin Chary" <corentincj@iksaif.net>
Description:
Control the bluetooth device. 1 means on, 0 means off.
Control the wlan device. 1 means on, 0 means off.
This may control the led, the device or both.
Users: Lapsus
What: /sys/devices/platform/asus_laptop/wimax
Date: October 2010
KernelVersion: 2.6.37
Contact: "Corentin Chary" <corentincj@iksaif.net>
Description:
Control the wimax device. 1 means on, 0 means off.
What: /sys/devices/platform/asus_laptop/wwan
Date: October 2010
KernelVersion: 2.6.37
Contact: "Corentin Chary" <corentincj@iksaif.net>
Description:
Control the wwan (3G) device. 1 means on, 0 means off.

10
Documentation/ABI/testing/sysfs-platform-eeepc-wmi Normal file
View File

@ -0,0 +1,10 @@
What: /sys/devices/platform/eeepc-wmi/cpufv
Date: Oct 2010
KernelVersion: 2.6.37
Contact: "Corentin Chary" <corentincj@iksaif.net>
Description:
Change CPU clock configuration (write-only).
There are three available clock configuration:
* 0 -> Super Performance Mode
* 1 -> High Performance Mode
* 2 -> Power Saving Mode

129
Documentation/driver-model/interface.txt
View File

@ -1,129 +0,0 @@
Device Interfaces
Introduction
~~~~~~~~~~~~
Device interfaces are the logical interfaces of device classes that correlate
directly to userspace interfaces, like device nodes.
Each device class may have multiple interfaces through which you can
access the same device. An input device may support the mouse interface,
the 'evdev' interface, and the touchscreen interface. A SCSI disk would
support the disk interface, the SCSI generic interface, and possibly a raw
device interface.
Device interfaces are registered with the class they belong to. As devices
are added to the class, they are added to each interface registered with
the class. The interface is responsible for determining whether the device
supports the interface or not.
Programming Interface
~~~~~~~~~~~~~~~~~~~~~
struct device_interface {
char * name;
rwlock_t lock;
u32 devnum;
struct device_class * devclass;
struct list_head node;
struct driver_dir_entry dir;
int (*add_device)(struct device *);
int (*add_device)(struct intf_data *);
};
int interface_register(struct device_interface *);
void interface_unregister(struct device_interface *);
An interface must specify the device class it belongs to. It is added
to that class's list of interfaces on registration.
Interfaces can be added to a device class at any time. Whenever it is
added, each device in the class is passed to the interface's
add_device callback. When an interface is removed, each device is
removed from the interface.
Devices
~~~~~~~
Once a device is added to a device class, it is added to each
interface that is registered with the device class. The class
is expected to place a class-specific data structure in
struct device::class_data. The interface can use that (along with
other fields of struct device) to determine whether or not the driver
and/or device support that particular interface.
Data
~~~~
struct intf_data {
struct list_head node;
struct device_interface * intf;
struct device * dev;
u32 intf_num;
};
int interface_add_data(struct interface_data *);
The interface is responsible for allocating and initializing a struct
intf_data and calling interface_add_data() to add it to the device's list
of interfaces it belongs to. This list will be iterated over when the device
is removed from the class (instead of all possible interfaces for a class).
This structure should probably be embedded in whatever per-device data
structure the interface is allocating anyway.
Devices are enumerated within the interface. This happens in interface_add_data()
and the enumerated value is stored in the struct intf_data for that device.
sysfs
~~~~~
Each interface is given a directory in the directory of the device
class it belongs to:
Interfaces get a directory in the class's directory as well:
class/
`-- input
|-- devices
|-- drivers
|-- mouse
`-- evdev
When a device is added to the interface, a symlink is created that points
to the device's directory in the physical hierarchy:
class/
`-- input
|-- devices
| `-- 1 -> ../../../root/pci0/00:1f.0/usb_bus/00:1f.2-1:0/
|-- drivers
| `-- usb:usb_mouse -> ../../../bus/drivers/usb_mouse/
|-- mouse
| `-- 1 -> ../../../root/pci0/00:1f.0/usb_bus/00:1f.2-1:0/
`-- evdev
`-- 1 -> ../../../root/pci0/00:1f.0/usb_bus/00:1f.2-1:0/
Future Plans
~~~~~~~~~~~~
A device interface is correlated directly with a userspace interface
for a device, specifically a device node. For instance, a SCSI disk
exposes at least two interfaces to userspace: the standard SCSI disk
interface and the SCSI generic interface. It might also export a raw
device interface.
Many interfaces have a major number associated with them and each
device gets a minor number. Or, multiple interfaces might share one
major number, and each will receive a range of minor numbers (like in
the case of input devices).
These major and minor numbers could be stored in the interface
structure. Major and minor allocations could happen when the interface
is registered with the class, or via a helper function.

7
Documentation/filesystems/Locking
View File

@ -173,12 +173,13 @@ prototypes:
sector_t (*bmap)(struct address_space *, sector_t);
int (*invalidatepage) (struct page *, unsigned long);
int (*releasepage) (struct page *, int);
void (*freepage)(struct page *);
int (*direct_IO)(int, struct kiocb *, const struct iovec *iov,
loff_t offset, unsigned long nr_segs);
int (*launder_page) (struct page *);
locking rules:
All except set_page_dirty may block
All except set_page_dirty and freepage may block
BKL PageLocked(page) i_mutex
writepage: no yes, unlocks (see below)
@ -193,6 +194,7 @@ perform_write: no n/a yes
bmap: no
invalidatepage: no yes
releasepage: no yes
freepage: no yes
direct_IO: no
launder_page: no yes
@ -288,6 +290,9 @@ buffers from the page in preparation for freeing it. It returns zero to
indicate that the buffers are (or may be) freeable. If ->releasepage is zero,
the kernel assumes that the fs has no private interest in the buffers.
->freepage() is called when the kernel is done dropping the page
from the page cache.
->launder_page() may be called prior to releasing a page if
it is still found to be dirty. It returns zero if the page was successfully
cleaned, or an error value if not. Note that in order to prevent the page

16
Documentation/filesystems/vfs.txt
View File

@ -534,6 +534,7 @@ struct address_space_operations {
sector_t (*bmap)(struct address_space *, sector_t);
int (*invalidatepage) (struct page *, unsigned long);
int (*releasepage) (struct page *, int);
void (*freepage)(struct page *);
ssize_t (*direct_IO)(int, struct kiocb *, const struct iovec *iov,
loff_t offset, unsigned long nr_segs);
struct page* (*get_xip_page)(struct address_space *, sector_t,
@ -660,11 +661,10 @@ struct address_space_operations {
releasepage: releasepage is called on PagePrivate pages to indicate
that the page should be freed if possible. ->releasepage
should remove any private data from the page and clear the
PagePrivate flag. It may also remove the page from the
address_space. If this fails for some reason, it may indicate
failure with a 0 return value.
This is used in two distinct though related cases. The first
is when the VM finds a clean page with no active users and
PagePrivate flag. If releasepage() fails for some reason, it must
indicate failure with a 0 return value.
releasepage() is used in two distinct though related cases. The
first is when the VM finds a clean page with no active users and
wants to make it a free page. If ->releasepage succeeds, the
page will be removed from the address_space and become free.
@ -679,6 +679,12 @@ struct address_space_operations {
need to ensure this. Possibly it can clear the PageUptodate
bit if it cannot free private data yet.
freepage: freepage is called once the page is no longer visible in
the page cache in order to allow the cleanup of any private
data. Since it may be called by the memory reclaimer, it
should not assume that the original address_space mapping still
exists, and it should not block.
direct_IO: called by the generic read/write routines to perform
direct_IO - that is IO requests which bypass the page cache
and transfer data directly between the storage and the

23
MAINTAINERS
View File

@ -559,14 +559,14 @@ W: http://maxim.org.za/at91_26.html
S: Maintained
ARM/BCMRING ARM ARCHITECTURE
M: Leo Chen <leochen@broadcom.com>
M: Jiandong Zheng <jdzheng@broadcom.com>
M: Scott Branden <sbranden@broadcom.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-bcmring
ARM/BCMRING MTD NAND DRIVER
M: Leo Chen <leochen@broadcom.com>
M: Jiandong Zheng <jdzheng@broadcom.com>
M: Scott Branden <sbranden@broadcom.com>
L: linux-mtd@lists.infradead.org
S: Maintained
@ -815,7 +815,7 @@ F: drivers/mmc/host/msm_sdcc.c
F: drivers/mmc/host/msm_sdcc.h
F: drivers/serial/msm_serial.h
F: drivers/serial/msm_serial.c
T: git git://codeaurora.org/quic/kernel/dwalker/linux-msm.git
T: git git://codeaurora.org/quic/kernel/davidb/linux-msm.git
S: Maintained
ARM/TOSA MACHINE SUPPORT
@ -2060,7 +2060,7 @@ F: Documentation/blockdev/drbd/
DRIVER CORE, KOBJECTS, DEBUGFS AND SYSFS
M: Greg Kroah-Hartman <gregkh@suse.de>
T: quilt kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core-2.6.git
S: Supported
F: Documentation/kobject.txt
F: drivers/base/
@ -2080,7 +2080,7 @@ F: include/drm/
INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets)
M: Chris Wilson <chris@chris-wilson.co.uk>
L: intel-gfx@lists.freedesktop.org
L: intel-gfx@lists.freedesktop.org (subscribers-only)
L: dri-devel@lists.freedesktop.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel.git
S: Supported
@ -4064,9 +4064,8 @@ F: drivers/scsi/NCR_D700.*
NETEFFECT IWARP RNIC DRIVER (IW_NES)
M: Faisal Latif <faisal.latif@intel.com>
M: Chien Tung <chien.tin.tung@intel.com>
L: linux-rdma@vger.kernel.org
W: http://www.neteffect.com
W: http://www.intel.com/Products/Server/Adapters/Server-Cluster/Server-Cluster-overview.htm
S: Supported
F: drivers/infiniband/hw/nes/
@ -5933,7 +5932,6 @@ F: include/linux/tty.h
TULIP NETWORK DRIVERS
M: Grant Grundler <grundler@parisc-linux.org>
M: Kyle McMartin <kyle@mcmartin.ca>
L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/tulip/
@ -6585,6 +6583,15 @@ F: include/linux/mfd/wm8400*
F: include/sound/wm????.h
F: sound/soc/codecs/wm*
WORKQUEUE
M: Tejun Heo <tj@kernel.org>
L: linux-kernel@vger.kernel.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq.git
S: Maintained
F: include/linux/workqueue.h
F: kernel/workqueue.c
F: Documentation/workqueue.txt
X.25 NETWORK LAYER
M: Andrew Hendry <andrew.hendry@gmail.com>
L: linux-x25@vger.kernel.org

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 37
EXTRAVERSION = -rc4
EXTRAVERSION = -rc6
NAME = Flesh-Eating Bats with Fangs
# *DOCUMENTATION*

10
arch/arm/Kconfig
View File

@ -9,7 +9,7 @@ config ARM
select GENERIC_ATOMIC64 if (!CPU_32v6K || !AEABI)
select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
select HAVE_ARCH_KGDB
select HAVE_KPROBES if (!XIP_KERNEL)
select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
select HAVE_KRETPROBES if (HAVE_KPROBES)
select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
@ -1000,8 +1000,8 @@ source arch/arm/mm/Kconfig
config IWMMXT
bool "Enable iWMMXt support"
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
default y if PXA27x || PXA3xx || ARCH_MMP
depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
help
Enable support for iWMMXt context switching at run time if
running on a CPU that supports it.
@ -1314,7 +1314,7 @@ config HZ
config THUMB2_KERNEL
bool "Compile the kernel in Thumb-2 mode"
depends on CPU_V7 && EXPERIMENTAL
depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
select AEABI
select ARM_ASM_UNIFIED
help
@ -1762,7 +1762,7 @@ comment "At least one emulation must be selected"
config FPE_NWFPE
bool "NWFPE math emulation"
depends on !AEABI || OABI_COMPAT
depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
---help---
Say Y to include the NWFPE floating point emulator in the kernel.
This is necessary to run most binaries. Linux does not currently

5
arch/arm/boot/Makefile
View File

@ -70,12 +70,7 @@ else
$(obj)/uImage: LOADADDR=$(ZRELADDR)
endif
ifeq ($(CONFIG_THUMB2_KERNEL),y)
# Set bit 0 to 1 so that "mov pc, rx" switches to Thumb-2 mode
$(obj)/uImage: STARTADDR=$(shell echo $(LOADADDR) | sed -e "s/.$$/1/")
else
$(obj)/uImage: STARTADDR=$(LOADADDR)
endif
$(obj)/uImage: $(obj)/zImage FORCE
$(call if_changed,uimage)

2
arch/arm/boot/bootp/init.S
View File

@ -73,6 +73,8 @@ move: ldmia r4!, {r7 - r10} @ move 32-bytes at a time
.size _start, . - _start
.align
.type data,#object
data: .word initrd_start @ source initrd address
.word initrd_phys @ destination initrd address

13
arch/arm/boot/compressed/head.S
View File

@ -125,9 +125,13 @@ wait: mrc p14, 0, pc, c0, c1, 0
* sort out different calling conventions
*/
.align
.arm @ Always enter in ARM state
start:
.type start,#function
.rept 8
THUMB( adr r12, BSYM(1f) )
THUMB( bx r12 )
THUMB( .rept 6 )
ARM( .rept 8 )
mov r0, r0
.endr
@ -135,6 +139,7 @@ start:
.word 0x016f2818 @ Magic numbers to help the loader
.word start @ absolute load/run zImage address
.word _edata @ zImage end address
THUMB( .thumb )
1: mov r7, r1 @ save architecture ID
mov r8, r2 @ save atags pointer
@ -174,7 +179,8 @@ not_angel:
ldr sp, [r0, #28]
#ifdef CONFIG_AUTO_ZRELADDR
@ determine final kernel image address
and r4, pc, #0xf8000000
mov r4, pc
and r4, r4, #0xf8000000
add r4, r4, #TEXT_OFFSET
#else
ldr r4, =zreladdr
@ -445,7 +451,8 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size
*/
mov r1, #0x1e
orr r1, r1, #3 << 10
mov r2, pc, lsr #20
mov r2, pc
mov r2, r2, lsr #20
orr r1, r1, r2, lsl #20
add r0, r3, r2, lsl #2
str r1, [r0], #4

40
arch/arm/common/gic.c
View File

@ -146,9 +146,15 @@ static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
unsigned int shift = (irq % 4) * 8;
unsigned int cpu = cpumask_first(mask_val);
u32 val;
struct irq_desc *desc;
spin_lock(&irq_controller_lock);
irq_desc[irq].node = cpu;
desc = irq_to_desc(irq);
if (desc == NULL) {
spin_unlock(&irq_controller_lock);
return -EINVAL;
}
desc->node = cpu;
val = readl(reg) & ~(0xff << shift);
val |= 1 << (cpu + shift);
writel(val, reg);
@ -210,7 +216,7 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
unsigned int irq_start)
{
unsigned int max_irq, i;
unsigned int gic_irqs, irq_limit, i;
u32 cpumask = 1 << smp_processor_id();
if (gic_nr >= MAX_GIC_NR)
@ -226,47 +232,49 @@ void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
/*
* Find out how many interrupts are supported.
*/
max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
max_irq = (max_irq + 1) * 32;
/*
* The GIC only supports up to 1020 interrupt sources.
* Limit this to either the architected maximum, or the
* platform maximum.
*/
if (max_irq > max(1020, NR_IRQS))
max_irq = max(1020, NR_IRQS);
gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;
gic_irqs = (gic_irqs + 1) * 32;
if (gic_irqs > 1020)
gic_irqs = 1020;
/*
* Set all global interrupts to be level triggered, active low.
*/
for (i = 32; i < max_irq; i += 16)
for (i = 32; i < gic_irqs; i += 16)
writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
/*
* Set all global interrupts to this CPU only.
*/
for (i = 32; i < max_irq; i += 4)
for (i = 32; i < gic_irqs; i += 4)
writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
/*
* Set priority on all global interrupts.
*/
for (i = 32; i < max_irq; i += 4)
for (i = 32; i < gic_irqs; i += 4)
writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
/*
* Disable all interrupts. Leave the PPI and SGIs alone
* as these enables are banked registers.
*/
for (i = 32; i < max_irq; i += 32)
for (i = 32; i < gic_irqs; i += 32)
writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
/*
* Limit number of interrupts registered to the platform maximum
*/
irq_limit = gic_data[gic_nr].irq_offset + gic_irqs;
if (WARN_ON(irq_limit > NR_IRQS))
irq_limit = NR_IRQS;
/*
* Setup the Linux IRQ subsystem.
*/
for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
for (i = irq_start; i < irq_limit; i++) {
set_irq_chip(i, &gic_chip);
set_irq_chip_data(i, &gic_data[gic_nr]);
set_irq_handler(i, handle_level_irq);

341
arch/arm/configs/at91rm9200_defconfig Normal file
View File

@ -0,0 +1,341 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_MACH_ONEARM=y
CONFIG_ARCH_AT91RM9200DK=y
CONFIG_MACH_AT91RM9200EK=y
CONFIG_MACH_CSB337=y
CONFIG_MACH_CSB637=y
CONFIG_MACH_CARMEVA=y
CONFIG_MACH_ATEB9200=y
CONFIG_MACH_KB9200=y
CONFIG_MACH_PICOTUX2XX=y
CONFIG_MACH_KAFA=y
CONFIG_MACH_ECBAT91=y
CONFIG_MACH_YL9200=y
CONFIG_MACH_CPUAT91=y
CONFIG_MACH_ECO920=y
CONFIG_MTD_AT91_DATAFLASH_CARD=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
CONFIG_AT91_TIMER_HZ=100
# CONFIG_ARM_THUMB is not set
CONFIG_PCCARD=y
CONFIG_AT91_CF=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_LEDS=y
CONFIG_LEDS_CPU=y
CONFIG_ZBOOT_ROM_TEXT=0x10000000
CONFIG_ZBOOT_ROM_BSS=0x20040000
CONFIG_KEXEC=y
CONFIG_FPE_NWFPE=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE=m
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
CONFIG_INET_XFRM_MODE_TRANSPORT=m
CONFIG_INET_XFRM_MODE_TUNNEL=m
CONFIG_INET_XFRM_MODE_BEET=m
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_MIP6=m
CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
CONFIG_IPV6_TUNNEL=m
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_BT=m
CONFIG_BT_L2CAP=m
CONFIG_BT_SCO=m
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_AFS_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PLATRAM=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_GLUEBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_ATMEL_TCLIB=y
CONFIG_EEPROM_LEGACY=m
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_BLK_DEV_SR=m
CONFIG_BLK_DEV_SR_VENDOR=y
CONFIG_CHR_DEV_SG=m
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_TUN=m
CONFIG_PHYLIB=y
CONFIG_DAVICOM_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_EPSON2888=y
CONFIG_PPP=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_BSDCOMP=y
CONFIG_PPP_MPPE=m
CONFIG_PPPOE=m
CONFIG_SLIP=m
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_SMART=y
CONFIG_SLIP_MODE_SLIP6=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_LEGACY_PTY_COUNT=32
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_ATMEL=y
CONFIG_SPI_BITBANG=y
CONFIG_GPIO_SYSFS=y
CONFIG_HWMON=m
CONFIG_SENSORS_ADM1021=m
CONFIG_SENSORS_ADM1025=m
CONFIG_SENSORS_ADM1026=m
CONFIG_SENSORS_ADM1029=m
CONFIG_SENSORS_ADM1031=m
CONFIG_SENSORS_ADM9240=m
CONFIG_SENSORS_DS1621=m
CONFIG_SENSORS_GL518SM=m
CONFIG_SENSORS_GL520SM=m
CONFIG_SENSORS_IT87=m
CONFIG_SENSORS_LM63=m
CONFIG_SENSORS_LM73=m
CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM77=m
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
CONFIG_SENSORS_LM83=m
CONFIG_SENSORS_LM85=m
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_LM92=m
CONFIG_SENSORS_MAX1619=m
CONFIG_SENSORS_PCF8591=m
CONFIG_SENSORS_SMSC47B397=m
CONFIG_SENSORS_W83781D=m
CONFIG_SENSORS_W83791D=m
CONFIG_SENSORS_W83792D=m
CONFIG_SENSORS_W83793=m
CONFIG_SENSORS_W83L785TS=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_AT91RM9200_WATCHDOG=y
CONFIG_FB=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
CONFIG_FB_S1D13XXX=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_DISPLAY_SUPPORT=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FONTS=y
CONFIG_FONT_MINI_4x6=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_STORAGE=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_KEYSPAN=y
CONFIG_USB_SERIAL_KEYSPAN_MPR=y
CONFIG_USB_SERIAL_KEYSPAN_USA28=y
CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
CONFIG_USB_SERIAL_KEYSPAN_USA19=y
CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
CONFIG_USB_SERIAL_MCT_U232=y
CONFIG_USB_SERIAL_PL2303=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETH=m
CONFIG_USB_MASS_STORAGE=m
CONFIG_MMC=y
CONFIG_MMC_AT91=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_REISERFS_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_NTFS_FS=m
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RUBIN=y
CONFIG_CRAMFS=y
CONFIG_MINIX_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=y
CONFIG_SMB_FS=m
CONFIG_CIFS=m
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAC_PARTITION=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_FTRACE is not set
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_SHA1=y

72
arch/arm/configs/at91rm9200dk_defconfig
View File

@ -1,72 +0,0 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91RM9200DK=y
CONFIG_MACH_ECO920=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
# CONFIG_ARM_THUMB is not set
CONFIG_PCCARD=y
CONFIG_AT91_CF=y
CONFIG_LEDS=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw"
CONFIG_FPE_NWFPE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_AT91RM9200_WATCHDOG=y
# CONFIG_VGA_CONSOLE is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_MMC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_EXT2_FS=y
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y

73
arch/arm/configs/at91rm9200ek_defconfig
View File

@ -1,73 +0,0 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_MACH_AT91RM9200EK=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
# CONFIG_ARM_THUMB is not set
CONFIG_LEDS=y
CONFIG_LEDS_CPU=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw"
CONFIG_FPE_NWFPE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IPV6 is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_AT91RM9200_WATCHDOG=y
CONFIG_FB=y
CONFIG_FB_S1D13XXX=y
# CONFIG_VGA_CONSOLE is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_MMC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_EXT2_FS=y
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y

131
arch/arm/configs/ateb9200_defconfig
View File

@ -1,131 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_PROFILING=y
CONFIG_OPROFILE=m
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_AT91=y
CONFIG_MACH_ATEB9200=y
CONFIG_PCCARD=m
CONFIG_AT91_CF=m
CONFIG_PREEMPT=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_FPE_NWFPE=y
CONFIG_PM=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IPV6 is not set
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK_RO=y
CONFIG_BLK_DEV_LOOP=m
CONFIG_BLK_DEV_NBD=m
CONFIG_SCSI=m
CONFIG_BLK_DEV_SD=m
CONFIG_BLK_DEV_SR=m
CONFIG_BLK_DEV_SR_VENDOR=y
CONFIG_CHR_DEV_SG=m
CONFIG_SCSI_MULTI_LUN=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=m
CONFIG_TUN=m
CONFIG_PHYLIB=y
CONFIG_DAVICOM_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
CONFIG_USB_USBNET=y
CONFIG_USB_NET_GL620A=y
CONFIG_USB_NET_PLUSB=y
CONFIG_USB_NET_RNDIS_HOST=y
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_EPSON2888=y
CONFIG_PPP=m
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPPOE=m
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_I2C=m
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_GPIO=m
# CONFIG_VGA_CONSOLE is not set
CONFIG_SOUND=y
CONFIG_USB_HID=m
CONFIG_HID_PID=y
CONFIG_USB_HIDDEV=y
CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_STORAGE=m
CONFIG_USB_STORAGE_DATAFAB=m
CONFIG_USB_STORAGE_FREECOM=m
CONFIG_USB_STORAGE_USBAT=m
CONFIG_USB_STORAGE_SDDR09=m
CONFIG_USB_STORAGE_SDDR55=m
CONFIG_USB_STORAGE_JUMPSHOT=m
CONFIG_USB_SERIAL=m
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_PL2303=m
CONFIG_USB_GADGET=m
CONFIG_USB_ETH=m
CONFIG_USB_GADGETFS=m
CONFIG_USB_FILE_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_MMC=m
CONFIG_MMC_DEBUG=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_EXT2_FS=m
CONFIG_EXT3_FS=m
CONFIG_REISERFS_FS=m
CONFIG_INOTIFY=y
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_NTFS_FS=m
CONFIG_NTFS_RW=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_NFSD=m
CONFIG_NFSD_V4=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAC_PARTITION=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_UNIXWARE_DISKLABEL=y
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_UTF8=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_ARC4=m
CONFIG_CRC16=m
CONFIG_LIBCRC32C=m

47
arch/arm/configs/carmeva_defconfig
View File

@ -1,47 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
# CONFIG_HOTPLUG is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_ARCH_AT91=y
CONFIG_MACH_CARMEVA=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_FPE_NWFPE=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
# CONFIG_IPV6 is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_BLK_DEV_RAM=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_SERIO=m
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_MMC=m
CONFIG_MMC_DEBUG=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
# CONFIG_DNOTIFY is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_NFSD=y

112
arch/arm/configs/cpuat91_defconfig
View File

@ -1,112 +0,0 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_MACH_CPUAT91=y
CONFIG_AT91_TIMER_HZ=100
# CONFIG_ARM_THUMB is not set
CONFIG_PREEMPT=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PLATRAM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=y
CONFIG_BLK_DEV_RAM=y
# CONFIG_MISC_DEVICES is not set
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_PHYLIB=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_PPP=y
CONFIG_PPP_ASYNC=y
CONFIG_PPP_DEFLATE=y
CONFIG_PPP_BSDCOMP=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_LEGACY_PTY_COUNT=32
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_AT91RM9200_WATCHDOG=y
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_ETH=m
CONFIG_MMC=y
CONFIG_MMC_AT91=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_PCF8563=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_INOTIFY=y
CONFIG_AUTOFS4_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_CRAMFS=y
CONFIG_MINIX_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set

104
arch/arm/configs/csb337_defconfig
View File

@ -1,104 +0,0 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_AT91=y
CONFIG_MACH_CSB337=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
# CONFIG_ARM_THUMB is not set
CONFIG_PCCARD=y
CONFIG_AT91_CF=y
CONFIG_LEDS=y
CONFIG_LEDS_CPU=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw"
CONFIG_FPE_NWFPE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_ATMEL_SSC=y
CONFIG_SCSI=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_AT91RM9200_WATCHDOG=y
# CONFIG_VGA_CONSOLE is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_KEYSPAN=y
CONFIG_USB_SERIAL_KEYSPAN_MPR=y
CONFIG_USB_SERIAL_KEYSPAN_USA28=y
CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
CONFIG_USB_SERIAL_KEYSPAN_USA19=y
CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
CONFIG_USB_SERIAL_MCT_U232=y
CONFIG_USB_GADGET=y
CONFIG_MMC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc1"
# CONFIG_RTC_INTF_SYSFS is not set
CONFIG_RTC_DRV_DS1307=y
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_EXT2_FS=y
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y

98
arch/arm/configs/csb637_defconfig
View File

@ -1,98 +0,0 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_AT91=y
CONFIG_MACH_CSB637=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
# CONFIG_ARM_THUMB is not set
CONFIG_PCCARD=y
CONFIG_AT91_CF=y
CONFIG_LEDS=y
CONFIG_LEDS_CPU=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=32M console=ttyS0,38400 initrd=0x20410000,3145728 root=/dev/ram0 rw"
CONFIG_FPE_NWFPE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_SCSI=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_AT91RM9200_WATCHDOG=y
# CONFIG_VGA_CONSOLE is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_SERIAL=y
CONFIG_USB_SERIAL_CONSOLE=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_FTDI_SIO=y
CONFIG_USB_SERIAL_KEYSPAN=y
CONFIG_USB_SERIAL_KEYSPAN_MPR=y
CONFIG_USB_SERIAL_KEYSPAN_USA28=y
CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
CONFIG_USB_SERIAL_KEYSPAN_USA19=y
CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
CONFIG_USB_SERIAL_MCT_U232=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_EXT2_FS=y
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y

99
arch/arm/configs/ecbat91_defconfig
View File

@ -1,99 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_MACH_ECBAT91=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
CONFIG_PCCARD=y
CONFIG_AT91_CF=y
CONFIG_PREEMPT=y
CONFIG_LEDS=y
CONFIG_LEDS_CPU=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="rootfstype=reiserfs root=/dev/mmcblk0p1 console=ttyS0,115200n8 rootdelay=1"
CONFIG_FPE_NWFPE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IPV6 is not set
CONFIG_CFG80211=y
CONFIG_MAC80211=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_AFS_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_DATAFLASH=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_PPP=y
CONFIG_PPP_MULTILINK=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
# CONFIG_VGA_CONSOLE is not set
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_PRINTER=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_MMC=y
CONFIG_MMC_DEBUG=y
CONFIG_MMC_AT91=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_REISERFS_FS=y
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_DEBUG_USER=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_SHA1=y

61
arch/arm/configs/kafa_defconfig
View File

@ -1,61 +0,0 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_MACH_KAFA=y
# CONFIG_ARM_THUMB is not set
CONFIG_PREEMPT=y
CONFIG_LEDS=y
CONFIG_LEDS_CPU=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20800000,10M root=/dev/ram0 rw"
CONFIG_FPE_NWFPE=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK_RO=y
CONFIG_NETDEVICES=y
CONFIG_PHYLIB=y
CONFIG_DAVICOM_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_LEGACY_PTY_COUNT=32
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_AT91RM9200_WATCHDOG=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_RTC_CLASS=y
# CONFIG_RTC_HCTOSYS is not set
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=m
CONFIG_NFS_V3=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_DES=y

127
arch/arm/configs/kb9202_defconfig
View File

@ -1,127 +0,0 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_AUDIT=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_EXTRA_PASS=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_ARCH_AT91=y
CONFIG_MACH_KB9200=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x10000000
CONFIG_ZBOOT_ROM_BSS=0x20040000
CONFIG_CMDLINE="noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M"
CONFIG_KEXEC=y
CONFIG_FPE_NWFPE=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_MTD=y
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_GLUEBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_ATMEL_TCLIB=y
CONFIG_ATMEL_SSC=y
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_SCSI_MULTI_LUN=y
CONFIG_SCSI_CONSTANTS=y
CONFIG_SCSI_LOGGING=y
CONFIG_SCSI_SPI_ATTRS=m
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_AT91RM9200_WATCHDOG=y
CONFIG_FB=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
# CONFIG_LCD_CLASS_DEVICE is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FONTS=y
CONFIG_FONT_MINI_4x6=y
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_LIBUSUAL=y
CONFIG_MMC=y
CONFIG_MMC_AT91=m
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
CONFIG_JFFS2_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_UTF8=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set

80
arch/arm/configs/onearm_defconfig
View File

@ -1,80 +0,0 @@
CONFIG_EXPERIMENTAL=y
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
CONFIG_EMBEDDED=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_MACH_ONEARM=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
# CONFIG_ARM_THUMB is not set
CONFIG_PCCARD=y
CONFIG_AT91_CF=y
CONFIG_LEDS=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp mem=64M"
CONFIG_FPE_NWFPE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IPV6=y
# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
# CONFIG_INET6_XFRM_MODE_BEET is not set
# CONFIG_IPV6_SIT is not set
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_NBD=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_AT91RM9200_WATCHDOG=y
# CONFIG_USB_HID is not set
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_MMC=y
CONFIG_EXT2_FS=y
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_CRAMFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_ROOT_NFS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y

242
arch/arm/configs/picotux200_defconfig
View File

@ -1,242 +0,0 @@
CONFIG_EXPERIMENTAL=y
CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=m
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_EMBEDDED=y
# CONFIG_KALLSYMS is not set
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_MACH_PICOTUX2XX=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
CONFIG_AEABI=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_KEXEC=y
CONFIG_FPE_NWFPE=y
CONFIG_BINFMT_MISC=m
CONFIG_NET=y
CONFIG_PACKET=m
CONFIG_UNIX=y
CONFIG_XFRM_USER=m
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE=m
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
CONFIG_INET_XFRM_MODE_TRANSPORT=m
CONFIG_INET_XFRM_MODE_TUNNEL=m
CONFIG_INET_XFRM_MODE_BEET=m
CONFIG_INET_DIAG=m
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_MIP6=m
CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
CONFIG_IPV6_TUNNEL=m
CONFIG_BRIDGE=m
CONFIG_VLAN_8021Q=m
CONFIG_BT=m
CONFIG_BT_L2CAP=m
CONFIG_BT_SCO=m
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=m
CONFIG_FW_LOADER=m
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_LOOP=m
CONFIG_EEPROM_LEGACY=m
CONFIG_SCSI=m
CONFIG_BLK_DEV_SD=m
CONFIG_BLK_DEV_SR=m
CONFIG_BLK_DEV_SR_VENDOR=y
CONFIG_CHR_DEV_SG=m
CONFIG_NETDEVICES=y
CONFIG_TUN=m
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
CONFIG_USB_CATC=m
CONFIG_USB_KAWETH=m
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_USBNET=m
CONFIG_USB_NET_DM9601=m
CONFIG_USB_NET_GL620A=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
CONFIG_USB_NET_RNDIS_HOST=m
CONFIG_USB_ALI_M5632=y
CONFIG_USB_AN2720=y
CONFIG_USB_EPSON2888=y
CONFIG_USB_KC2190=y
CONFIG_PPP=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_MPPE=m
CONFIG_PPPOE=m
CONFIG_SLIP=m
CONFIG_SLIP_COMPRESSED=y
CONFIG_SLIP_SMART=y
CONFIG_SLIP_MODE_SLIP6=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_I2C=m
CONFIG_I2C_CHARDEV=m
CONFIG_I2C_GPIO=m
CONFIG_HWMON=m
CONFIG_SENSORS_ADM1021=m
CONFIG_SENSORS_ADM1025=m
CONFIG_SENSORS_ADM1026=m
CONFIG_SENSORS_ADM1029=m
CONFIG_SENSORS_ADM1031=m
CONFIG_SENSORS_ADM9240=m
CONFIG_SENSORS_DS1621=m
CONFIG_SENSORS_GL518SM=m
CONFIG_SENSORS_GL520SM=m
CONFIG_SENSORS_IT87=m
CONFIG_SENSORS_LM63=m
CONFIG_SENSORS_LM75=m
CONFIG_SENSORS_LM77=m
CONFIG_SENSORS_LM78=m
CONFIG_SENSORS_LM80=m
CONFIG_SENSORS_LM83=m
CONFIG_SENSORS_LM85=m
CONFIG_SENSORS_LM87=m
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_LM92=m
CONFIG_SENSORS_MAX1619=m
CONFIG_SENSORS_PCF8591=m
CONFIG_SENSORS_SMSC47B397=m
CONFIG_SENSORS_W83781D=m
CONFIG_SENSORS_W83791D=m
CONFIG_SENSORS_W83792D=m
CONFIG_SENSORS_W83793=m
CONFIG_SENSORS_W83L785TS=m
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_AT91RM9200_WATCHDOG=m
CONFIG_HID=m
CONFIG_USB=m
CONFIG_USB_DEVICEFS=y
CONFIG_USB_OHCI_HCD=m
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_STORAGE=m
CONFIG_USB_SERIAL=m
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_PL2303=m
CONFIG_MMC=m
CONFIG_MMC_AT91=m
CONFIG_RTC_CLASS=m
CONFIG_RTC_DRV_AT91RM9200=m
CONFIG_EXT2_FS=m
CONFIG_EXT3_FS=m
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_INOTIFY=y
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_UDF_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_NTFS_FS=m
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_NFS_FS=m
CONFIG_SMB_FS=m
CONFIG_CIFS=m
CONFIG_PARTITION_ADVANCED=y
CONFIG_AMIGA_PARTITION=y
CONFIG_NLS_DEFAULT="utf-8"
CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=m
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_LL=y
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_TEST=m
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XCBC=m
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_SHA256=m
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_LIBCRC32C=m

137
arch/arm/configs/yl9200_defconfig
View File

@ -1,137 +0,0 @@
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91RM9200DK=y
CONFIG_MACH_YL9200=y
# CONFIG_ARM_THUMB is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw"
CONFIG_FPE_NWFPE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_MTD=y
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PLATRAM=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=3
CONFIG_BLK_DEV_RAM_SIZE=8192
# CONFIG_MISC_DEVICES is not set
CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_NETDEVICES=y
CONFIG_PHYLIB=y
CONFIG_DAVICOM_PHY=y
CONFIG_NET_ETHERNET=y
CONFIG_ARM_AT91_ETHER=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
CONFIG_KEYBOARD_GPIO=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_SPI=y
CONFIG_SPI_DEBUG=y
CONFIG_SPI_ATMEL=y
CONFIG_FB=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_DISPLAY_SUPPORT=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_VGA16 is not set
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_USB_DEVICEFS=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_MON=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_M66592=y
CONFIG_USB_FILE_STORAGE=m
CONFIG_MMC=y
CONFIG_MMC_DEBUG=y
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_MMC_AT91=m
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT3_FS=y
CONFIG_REISERFS_FS=y
CONFIG_INOTIFY=y
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=1
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_RUBIN=y
CONFIG_CRAMFS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_MAC_PARTITION=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_SLUB_DEBUG_ON=y
CONFIG_DEBUG_KOBJECT=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_LIST=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_DEBUG_LL=y

1
arch/arm/kernel/Makefile
View File

@ -51,6 +51,7 @@ AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o
obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o
obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o
obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o
obj-$(CONFIG_IWMMXT) += iwmmxt.o
obj-$(CONFIG_CPU_HAS_PMU) += pmu.o
obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o

2
arch/arm/kernel/entry-armv.S
View File

@ -915,7 +915,7 @@ __kuser_cmpxchg: @ 0xffff0fc0
* A special ghost syscall is used for that (see traps.c).
*/
stmfd sp!, {r7, lr}
ldr r7, =1f @ it's 20 bits
ldr r7, 1f @ it's 20 bits
swi __ARM_NR_cmpxchg
ldmfd sp!, {r7, pc}
1: .word __ARM_NR_cmpxchg

7
arch/arm/kernel/head.S
View File

@ -85,9 +85,11 @@ ENTRY(stext)
mrc p15, 0, r9, c0, c0 @ get processor id
bl __lookup_processor_type @ r5=procinfo r9=cpuid
movs r10, r5 @ invalid processor (r5=0)?
THUMB( it eq ) @ force fixup-able long branch encoding
beq __error_p @ yes, error 'p'
bl __lookup_machine_type @ r5=machinfo
movs r8, r5 @ invalid machine (r5=0)?
THUMB( it eq ) @ force fixup-able long branch encoding
beq __error_a @ yes, error 'a'
bl __vet_atags
#ifdef CONFIG_SMP_ON_UP
@ -262,6 +264,7 @@ __create_page_tables:
mov pc, lr
ENDPROC(__create_page_tables)
.ltorg
.align
__enable_mmu_loc:
.long .
.long __enable_mmu
@ -282,6 +285,7 @@ ENTRY(secondary_startup)
bl __lookup_processor_type
movs r10, r5 @ invalid processor?
moveq r0, #'p' @ yes, error 'p'
THUMB( it eq ) @ force fixup-able long branch encoding
beq __error_p
/*
@ -308,6 +312,8 @@ ENTRY(__secondary_switched)
b secondary_start_kernel
ENDPROC(__secondary_switched)
.align
.type __secondary_data, %object
__secondary_data:
.long .
@ -413,6 +419,7 @@ __fixup_smp_on_up:
mov pc, lr
ENDPROC(__fixup_smp)
.align
1: .word .
.word __smpalt_begin
.word __smpalt_end

55
arch/arm/kernel/iwmmxt.S
View File

@ -19,6 +19,14 @@
#include <asm/thread_info.h>
#include <asm/asm-offsets.h>
#if defined(CONFIG_CPU_PJ4)
#define PJ4(code...) code
#define XSC(code...)
#else
#define PJ4(code...)
#define XSC(code...) code
#endif
#define MMX_WR0 (0x00)
#define MMX_WR1 (0x08)
#define MMX_WR2 (0x10)
@ -58,11 +66,17 @@
ENTRY(iwmmxt_task_enable)
mrc p15, 0, r2, c15, c1, 0
tst r2, #0x3 @ CP0 and CP1 accessible?
XSC(mrc p15, 0, r2, c15, c1, 0)
PJ4(mrc p15, 0, r2, c1, c0, 2)
@ CP0 and CP1 accessible?
XSC(tst r2, #0x3)
PJ4(tst r2, #0xf)
movne pc, lr @ if so no business here
orr r2, r2, #0x3 @ enable access to CP0 and CP1
mcr p15, 0, r2, c15, c1, 0
@ enable access to CP0 and CP1
XSC(orr r2, r2, #0x3)
XSC(mcr p15, 0, r2, c15, c1, 0)
PJ4(orr r2, r2, #0xf)
PJ4(mcr p15, 0, r2, c1, c0, 2)
ldr r3, =concan_owner
add r0, r10, #TI_IWMMXT_STATE @ get task Concan save area
@ -179,17 +193,26 @@ ENTRY(iwmmxt_task_disable)
teqne r1, r2 @ or specified one?
bne 1f @ no: quit
mrc p15, 0, r4, c15, c1, 0
orr r4, r4, #0x3 @ enable access to CP0 and CP1
mcr p15, 0, r4, c15, c1, 0
@ enable access to CP0 and CP1
XSC(mrc p15, 0, r4, c15, c1, 0)
XSC(orr r4, r4, #0xf)
XSC(mcr p15, 0, r4, c15, c1, 0)
PJ4(mrc p15, 0, r4, c1, c0, 2)
PJ4(orr r4, r4, #0x3)
PJ4(mcr p15, 0, r4, c1, c0, 2)
mov r0, #0 @ nothing to load
str r0, [r3] @ no more current owner
mrc p15, 0, r2, c2, c0, 0
mov r2, r2 @ cpwait
bl concan_save
bic r4, r4, #0x3 @ disable access to CP0 and CP1
mcr p15, 0, r4, c15, c1, 0
@ disable access to CP0 and CP1
XSC(bic r4, r4, #0x3)
XSC(mcr p15, 0, r4, c15, c1, 0)
PJ4(bic r4, r4, #0xf)
PJ4(mcr p15, 0, r4, c1, c0, 2)
mrc p15, 0, r2, c2, c0, 0
mov r2, r2 @ cpwait
@ -277,8 +300,11 @@ ENTRY(iwmmxt_task_restore)
*/
ENTRY(iwmmxt_task_switch)
mrc p15, 0, r1, c15, c1, 0
tst r1, #0x3 @ CP0 and CP1 accessible?
XSC(mrc p15, 0, r1, c15, c1, 0)
PJ4(mrc p15, 0, r1, c1, c0, 2)
@ CP0 and CP1 accessible?
XSC(tst r1, #0x3)
PJ4(tst r1, #0xf)
bne 1f @ yes: block them for next task
ldr r2, =concan_owner
@ -287,8 +313,11 @@ ENTRY(iwmmxt_task_switch)
teq r2, r3 @ next task owns it?
movne pc, lr @ no: leave Concan disabled
1: eor r1, r1, #3 @ flip Concan access
mcr p15, 0, r1, c15, c1, 0
1: @ flip Conan access
XSC(eor r1, r1, #0x3)
XSC(mcr p15, 0, r1, c15, c1, 0)
PJ4(eor r1, r1, #0xf)
PJ4(mcr p15, 0, r1, c1, c0, 2)
mrc p15, 0, r1, c2, c0, 0
sub pc, lr, r1, lsr #32 @ cpwait and return

94
arch/arm/kernel/pj4-cp0.c Normal file
View File

@ -0,0 +1,94 @@
/*
* linux/arch/arm/kernel/pj4-cp0.c
*
* PJ4 iWMMXt coprocessor context switching and handling
*
* Copyright (c) 2010 Marvell International Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/thread_notify.h>
static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
{
struct thread_info *thread = t;
switch (cmd) {
case THREAD_NOTIFY_FLUSH:
/*
* flush_thread() zeroes thread->fpstate, so no need
* to do anything here.
*
* FALLTHROUGH: Ensure we don't try to overwrite our newly
* initialised state information on the first fault.
*/
case THREAD_NOTIFY_EXIT:
iwmmxt_task_release(thread);
break;
case THREAD_NOTIFY_SWITCH:
iwmmxt_task_switch(thread);
break;
}
return NOTIFY_DONE;
}
static struct notifier_block iwmmxt_notifier_block = {
.notifier_call = iwmmxt_do,
};
static u32 __init pj4_cp_access_read(void)
{
u32 value;
__asm__ __volatile__ (
"mrc p15, 0, %0, c1, c0, 2\n\t"
: "=r" (value));
return value;
}
static void __init pj4_cp_access_write(u32 value)
{
u32 temp;
__asm__ __volatile__ (
"mcr p15, 0, %1, c1, c0, 2\n\t"
"mrc p15, 0, %0, c1, c0, 2\n\t"
"mov %0, %0\n\t"
"sub pc, pc, #4\n\t"
: "=r" (temp) : "r" (value));
}
/*
* Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
* switch code handle iWMMXt context switching.
*/
static int __init pj4_cp0_init(void)
{
u32 cp_access;
cp_access = pj4_cp_access_read() & ~0xf;
pj4_cp_access_write(cp_access);
printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n");
elf_hwcap |= HWCAP_IWMMXT;
thread_register_notifier(&iwmmxt_notifier_block);
return 0;
}
late_initcall(pj4_cp0_init);

2
arch/arm/kernel/relocate_kernel.S
View File

@ -59,6 +59,8 @@ relocate_new_kernel:
ldr r2,kexec_boot_atags
mov pc,lr
.align
.globl kexec_start_address
kexec_start_address:
.long 0x0

4
arch/arm/mach-at91/Makefile
View File

@ -24,8 +24,8 @@ obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
# AT91RM9200 board-specific support
obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o
obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o
obj-$(CONFIG_ARCH_AT91RM9200DK) += board-rm9200dk.o
obj-$(CONFIG_MACH_AT91RM9200EK) += board-rm9200ek.o
obj-$(CONFIG_MACH_CSB337) += board-csb337.o
obj-$(CONFIG_MACH_CSB637) += board-csb637.o
obj-$(CONFIG_MACH_CARMEVA) += board-carmeva.o

45
arch/arm/mach-at91/at91rm9200_devices.c
View File

@ -1106,51 +1106,6 @@ static inline void configure_usart3_pins(unsigned pins)
static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
struct platform_device *atmel_default_console_device; /* the serial console device */
void __init __deprecated at91_init_serial(struct at91_uart_config *config)
{
int i;
/* Fill in list of supported UARTs */
for (i = 0; i < config->nr_tty; i++) {
switch (config->tty_map[i]) {
case 0:
configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
at91_uarts[i] = &at91rm9200_uart0_device;
at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart");
break;
case 1:
configure_usart1_pins(ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DSR | ATMEL_UART_DTR | ATMEL_UART_DCD | ATMEL_UART_RI);
at91_uarts[i] = &at91rm9200_uart1_device;
at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart");
break;
case 2:
configure_usart2_pins(0);
at91_uarts[i] = &at91rm9200_uart2_device;
at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart");
break;
case 3:
configure_usart3_pins(0);
at91_uarts[i] = &at91rm9200_uart3_device;
at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart");
break;
case 4:
configure_dbgu_pins();
at91_uarts[i] = &at91rm9200_dbgu_device;
at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart");
break;
default:
continue;
}
at91_uarts[i]->id = i; /* update ID number to mapped ID */
}
/* Set serial console device */
if (config->console_tty < ATMEL_MAX_UART)
atmel_default_console_device = at91_uarts[config->console_tty];
if (!atmel_default_console_device)
printk(KERN_INFO "AT91: No default serial console defined.\n");
}
void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
{
struct platform_device *pdev;

26
arch/arm/mach-at91/board-1arm.c
View File

@ -39,24 +39,24 @@
#include "generic.h"
/*
* Serial port configuration.
* 0 .. 3 = USART0 .. USART3
* 4 = DBGU
*/
static struct at91_uart_config __initdata onearm_uart_config = {
.console_tty = 0, /* ttyS0 */
.nr_tty = 3,
.tty_map = { 4, 0, 1, -1, -1 }, /* ttyS0, ..., ttyS4 */
};
static void __init onearm_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91rm9200_initialize(18432000, AT91RM9200_PQFP);
/* Setup the serial ports and console */
at91_init_serial(&onearm_uart_config);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
/* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
| ATMEL_UART_RI);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init onearm_init_irq(void)

21
arch/arm/mach-at91/board-kafa.c
View File

@ -39,17 +39,6 @@
#include "generic.h"
/*
* Serial port configuration.
* 0 .. 3 = USART0 .. USART3
* 4 = DBGU
*/
static struct at91_uart_config __initdata kafa_uart_config = {
.console_tty = 0, /* ttyS0 */
.nr_tty = 2,
.tty_map = { 4, 0, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
};
static void __init kafa_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
@ -58,8 +47,14 @@ static void __init kafa_map_io(void)
/* Set up the LEDs */
at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4);
/* Setup the serial ports and console */
at91_init_serial(&kafa_uart_config);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init kafa_init_irq(void)

53
arch/arm/mach-at91/board-picotux200.c
View File

@ -43,24 +43,21 @@
#include "generic.h"
/*
* Serial port configuration.
* 0 .. 3 = USART0 .. USART3
* 4 = DBGU
*/
static struct at91_uart_config __initdata picotux200_uart_config = {
.console_tty = 0, /* ttyS0 */
.nr_tty = 2,
.tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
};
static void __init picotux200_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91rm9200_initialize(18432000, AT91RM9200_BGA);
/* Setup the serial ports and console */
at91_init_serial(&picotux200_uart_config);
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
| ATMEL_UART_RI);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init picotux200_init_irq(void)
@ -77,11 +74,6 @@ static struct at91_usbh_data __initdata picotux200_usbh_data = {
.ports = 1,
};
// static struct at91_udc_data __initdata picotux200_udc_data = {
// .vbus_pin = AT91_PIN_PD4,
// .pullup_pin = AT91_PIN_PD5,
// };
static struct at91_mmc_data __initdata picotux200_mmc_data = {
.det_pin = AT91_PIN_PB27,
.slot_b = 0,
@ -89,21 +81,6 @@ static struct at91_mmc_data __initdata picotux200_mmc_data = {
.wp_pin = AT91_PIN_PA17,
};
// static struct spi_board_info picotux200_spi_devices[] = {
// { /* DataFlash chip */
// .modalias = "mtd_dataflash",
// .chip_select = 0,
// .max_speed_hz = 15 * 1000 * 1000,
// },
// #ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
// { /* DataFlash card */
// .modalias = "mtd_dataflash",
// .chip_select = 3,
// .max_speed_hz = 15 * 1000 * 1000,
// },
// #endif
// };
#define PICOTUX200_FLASH_BASE AT91_CHIPSELECT_0
#define PICOTUX200_FLASH_SIZE SZ_4M
@ -135,21 +112,11 @@ static void __init picotux200_board_init(void)
at91_add_device_eth(&picotux200_eth_data);
/* USB Host */
at91_add_device_usbh(&picotux200_usbh_data);
/* USB Device */
// at91_add_device_udc(&picotux200_udc_data);
// at91_set_multi_drive(picotux200_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */
/* I2C */
at91_add_device_i2c(NULL, 0);
/* SPI */
// at91_add_device_spi(picotux200_spi_devices, ARRAY_SIZE(picotux200_spi_devices));
#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
/* DataFlash card */
at91_set_gpio_output(AT91_PIN_PB22, 0);
#else
/* MMC */
at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
at91_add_device_mmc(0, &picotux200_mmc_data);
#endif
/* NOR Flash */
platform_device_register(&picotux200_flash);
}

4
arch/arm/mach-at91/board-dk.c → arch/arm/mach-at91/board-rm9200dk.c
View File

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-at91/board-dk.c
* linux/arch/arm/mach-at91/board-rm9200dk.c
*
* Copyright (C) 2005 SAN People
*
@ -91,10 +91,12 @@ static struct at91_cf_data __initdata dk_cf_data = {
// .vcc_pin = ... always powered
};
#ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
static struct at91_mmc_data __initdata dk_mmc_data = {
.slot_b = 0,
.wire4 = 1,
};
#endif
static struct spi_board_info dk_spi_devices[] = {
{ /* DataFlash chip */

4
arch/arm/mach-at91/board-ek.c → arch/arm/mach-at91/board-rm9200ek.c
View File

@ -1,5 +1,5 @@
/*
* linux/arch/arm/mach-at91/board-ek.c
* linux/arch/arm/mach-at91/board-rm9200ek.c
*
* Copyright (C) 2005 SAN People
*
@ -84,12 +84,14 @@ static struct at91_udc_data __initdata ek_udc_data = {
.pullup_pin = AT91_PIN_PD5,
};
#ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
static struct at91_mmc_data __initdata ek_mmc_data = {
.det_pin = AT91_PIN_PB27,
.slot_b = 0,
.wire4 = 1,
.wp_pin = AT91_PIN_PA17,
};
#endif
static struct spi_board_info ek_spi_devices[] = {
{ /* DataFlash chip */

2
arch/arm/mach-at91/board-yl-9200.c
View File

@ -387,7 +387,7 @@ static struct spi_board_info yl9200_spi_devices[] = {
* EPSON S1D13806 FB (discontinued chip)
* EPSON S1D13506 FB
*/
#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
#include <video/s1d13xxxfb.h>

6
arch/arm/mach-at91/include/mach/board.h
View File

@ -137,13 +137,7 @@ extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_de
extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
extern void __init at91_set_serial_console(unsigned portnr);
struct at91_uart_config {
unsigned short console_tty; /* tty number of serial console */
unsigned short nr_tty; /* number of serial tty's */
short tty_map[]; /* map UART to tty number */
};
extern struct platform_device *atmel_default_console_device;
extern void __init __deprecated at91_init_serial(struct at91_uart_config *config);
struct atmel_uart_data {
short use_dma_tx; /* use transmit DMA? */

2
arch/arm/mach-cns3xxx/pcie.c
View File

@ -369,7 +369,7 @@ static int __init cns3xxx_pcie_init(void)
{
int i;
hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS,
hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
"imprecise external abort");
for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {

22
arch/arm/mach-mmp/Kconfig
View File

@ -37,25 +37,38 @@ config MACH_TTC_DKB
Say 'Y' here if you want to support the Marvell PXA910-based
TTC_DKB Development Board.
config MACH_BROWNSTONE
bool "Marvell's Brownstone Development Platform"
depends on !CPU_MOHAWK
select CPU_MMP2
help
Say 'Y' here if you want to support the Marvell MMP2-based
Brown Development Platform.
MMP2-based board can't be co-existed with PXA168-based &
PXA910-based development board. Since MMP2 is compatible to
ARMv7 architecture.
config MACH_FLINT
bool "Marvell's Flint Development Platform"
depends on !CPU_MOHAWK
select CPU_MMP2
help
Say 'Y' here if you want to support the Marvell MMP2-based
Flint Development Platform.
MMP2-based board can't be co-existed with PXA168-based &
PXA910-based development board. Since MMP2 is compatible to
ARMv6 architecture.
ARMv7 architecture.
config MACH_MARVELL_JASPER
bool "Marvell's Jasper Development Platform"
depends on !CPU_MOHAWK
select CPU_MMP2
help
Say 'Y' here if you want to support the Marvell MMP2-base
Jasper Development Platform.
MMP2-based board can't be co-existed with PXA168-based &
PXA910-based development board. Since MMP2 is compatible to
ARMv6 architecture.
ARMv7 architecture.
config MACH_TETON_BGA
bool "Marvell's PXA168 Teton BGA Development Board"
@ -80,8 +93,7 @@ config CPU_PXA910
config CPU_MMP2
bool
select CPU_V6
select CPU_32v6K
select CPU_PJ4
help
Select code specific to MMP2. MMP2 is ARMv6 compatible.
Select code specific to MMP2. MMP2 is ARMv7 compatible.
endif

1
arch/arm/mach-mmp/Makefile
View File

@ -15,6 +15,7 @@ obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o
obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o
obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o
obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o
obj-$(CONFIG_MACH_FLINT) += flint.o
obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o

204
arch/arm/mach-mmp/brownstone.c Normal file
View File

@ -0,0 +1,204 @@
/*
* linux/arch/arm/mach-mmp/brownstone.c
*
* Support for the Marvell Brownstone Development Platform.
*
* Copyright (C) 2009-2010 Marvell International Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/max8649.h>
#include <linux/regulator/fixed.h>
#include <linux/mfd/max8925.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/addr-map.h>
#include <mach/mfp-mmp2.h>
#include <mach/mmp2.h>
#include <mach/irqs.h>
#include "common.h"
#define BROWNSTONE_NR_IRQS (IRQ_BOARD_START + 40)
#define GPIO_5V_ENABLE (89)
static unsigned long brownstone_pin_config[] __initdata = {
/* UART1 */
GPIO29_UART1_RXD,
GPIO30_UART1_TXD,
/* UART3 */
GPIO51_UART3_RXD,
GPIO52_UART3_TXD,
/* DFI */
GPIO168_DFI_D0,
GPIO167_DFI_D1,
GPIO166_DFI_D2,
GPIO165_DFI_D3,
GPIO107_DFI_D4,
GPIO106_DFI_D5,
GPIO105_DFI_D6,
GPIO104_DFI_D7,
GPIO111_DFI_D8,
GPIO164_DFI_D9,
GPIO163_DFI_D10,
GPIO162_DFI_D11,
GPIO161_DFI_D12,
GPIO110_DFI_D13,
GPIO109_DFI_D14,
GPIO108_DFI_D15,
GPIO143_ND_nCS0,
GPIO144_ND_nCS1,
GPIO147_ND_nWE,
GPIO148_ND_nRE,
GPIO150_ND_ALE,
GPIO149_ND_CLE,
GPIO112_ND_RDY0,
GPIO160_ND_RDY1,
/* PMIC */
PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
/* MMC0 */
GPIO131_MMC1_DAT3 | MFP_PULL_HIGH,
GPIO132_MMC1_DAT2 | MFP_PULL_HIGH,
GPIO133_MMC1_DAT1 | MFP_PULL_HIGH,
GPIO134_MMC1_DAT0 | MFP_PULL_HIGH,
GPIO136_MMC1_CMD | MFP_PULL_HIGH,
GPIO139_MMC1_CLK,
GPIO140_MMC1_CD | MFP_PULL_LOW,
GPIO141_MMC1_WP | MFP_PULL_LOW,
/* MMC1 */
GPIO37_MMC2_DAT3 | MFP_PULL_HIGH,
GPIO38_MMC2_DAT2 | MFP_PULL_HIGH,
GPIO39_MMC2_DAT1 | MFP_PULL_HIGH,
GPIO40_MMC2_DAT0 | MFP_PULL_HIGH,
GPIO41_MMC2_CMD | MFP_PULL_HIGH,
GPIO42_MMC2_CLK,
/* MMC2 */
GPIO165_MMC3_DAT7 | MFP_PULL_HIGH,
GPIO162_MMC3_DAT6 | MFP_PULL_HIGH,
GPIO166_MMC3_DAT5 | MFP_PULL_HIGH,
GPIO163_MMC3_DAT4 | MFP_PULL_HIGH,
GPIO167_MMC3_DAT3 | MFP_PULL_HIGH,
GPIO164_MMC3_DAT2 | MFP_PULL_HIGH,
GPIO168_MMC3_DAT1 | MFP_PULL_HIGH,
GPIO111_MMC3_DAT0 | MFP_PULL_HIGH,
GPIO112_MMC3_CMD | MFP_PULL_HIGH,
GPIO151_MMC3_CLK,
/* 5V regulator */
GPIO89_GPIO,
};
static struct regulator_consumer_supply max8649_supply[] = {
REGULATOR_SUPPLY("vcc_core", NULL),
};
static struct regulator_init_data max8649_init_data = {
.constraints = {
.name = "vcc_core range",
.min_uV = 1150000,
.max_uV = 1280000,
.always_on = 1,
.boot_on = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = 1,
.consumer_supplies = &max8649_supply[0],
};
static struct max8649_platform_data brownstone_max8649_info = {
.mode = 2, /* VID1 = 1, VID0 = 0 */
.extclk = 0,
.ramp_timing = MAX8649_RAMP_32MV,
.regulator = &max8649_init_data,
};
static struct regulator_consumer_supply brownstone_v_5vp_supplies[] = {
REGULATOR_SUPPLY("v_5vp", NULL),
};
static struct regulator_init_data brownstone_v_5vp_data = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(brownstone_v_5vp_supplies),
.consumer_supplies = brownstone_v_5vp_supplies,
};
static struct fixed_voltage_config brownstone_v_5vp = {
.supply_name = "v_5vp",
.microvolts = 5000000,
.gpio = GPIO_5V_ENABLE,
.enable_high = 1,
.enabled_at_boot = 1,
.init_data = &brownstone_v_5vp_data,
};
static struct platform_device brownstone_v_5vp_device = {
.name = "reg-fixed-voltage",
.id = 1,
.dev = {
.platform_data = &brownstone_v_5vp,
},
};
static struct max8925_platform_data brownstone_max8925_info = {
.irq_base = IRQ_BOARD_START,
};
static struct i2c_board_info brownstone_twsi1_info[] = {
[0] = {
.type = "max8649",
.addr = 0x60,
.platform_data = &brownstone_max8649_info,
},
[1] = {
.type = "max8925",
.addr = 0x3c,
.irq = IRQ_MMP2_PMIC,
.platform_data = &brownstone_max8925_info,
},
};
static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
.max_speed = 25000000,
};
static void __init brownstone_init(void)
{
mfp_config(ARRAY_AND_SIZE(brownstone_pin_config));
/* on-chip devices */
mmp2_add_uart(1);
mmp2_add_uart(3);
mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
/* enable 5v regulator */
platform_device_register(&brownstone_v_5vp_device);
}
MACHINE_START(BROWNSTONE, "Brownstone Development Platform")
/* Maintainer: Haojian Zhuang <haojian.zhuang@marvell.com> */
.map_io = mmp_map_io,
.nr_irqs = BROWNSTONE_NR_IRQS,
.init_irq = mmp2_init_irq,
.timer = &mmp2_timer,
.init_machine = brownstone_init,
MACHINE_END

2
arch/arm/mach-mmp/flint.c
View File

@ -47,7 +47,7 @@ static unsigned long flint_pin_config[] __initdata = {
GPIO113_SMC_RDY,
/*Ethernet*/
GPIO155_GPIO155,
GPIO155_GPIO,
/* DFI */
GPIO168_DFI_D0,

338
arch/arm/mach-mmp/include/mach/mfp-mmp2.h
View File

@ -9,175 +9,175 @@
#define MFP_DRIVE_FAST (0x8 << 13)
/* GPIO */
#define GPIO0_GPIO0 MFP_CFG(GPIO0, AF0)
#define GPIO1_GPIO1 MFP_CFG(GPIO1, AF0)
#define GPIO2_GPIO2 MFP_CFG(GPIO2, AF0)
#define GPIO3_GPIO3 MFP_CFG(GPIO3, AF0)
#define GPIO4_GPIO4 MFP_CFG(GPIO4, AF0)
#define GPIO5_GPIO5 MFP_CFG(GPIO5, AF0)
#define GPIO6_GPIO6 MFP_CFG(GPIO6, AF0)
#define GPIO7_GPIO7 MFP_CFG(GPIO7, AF0)
#define GPIO8_GPIO8 MFP_CFG(GPIO8, AF0)
#define GPIO9_GPIO9 MFP_CFG(GPIO9, AF0)
#define GPIO10_GPIO10 MFP_CFG(GPIO10, AF0)
#define GPIO11_GPIO11 MFP_CFG(GPIO11, AF0)
#define GPIO12_GPIO12 MFP_CFG(GPIO12, AF0)
#define GPIO13_GPIO13 MFP_CFG(GPIO13, AF0)
#define GPIO14_GPIO14 MFP_CFG(GPIO14, AF0)
#define GPIO15_GPIO15 MFP_CFG(GPIO15, AF0)
#define GPIO16_GPIO16 MFP_CFG(GPIO16, AF0)
#define GPIO17_GPIO17 MFP_CFG(GPIO17, AF0)
#define GPIO18_GPIO18 MFP_CFG(GPIO18, AF0)
#define GPIO19_GPIO19 MFP_CFG(GPIO19, AF0)
#define GPIO20_GPIO20 MFP_CFG(GPIO20, AF0)
#define GPIO21_GPIO21 MFP_CFG(GPIO21, AF0)
#define GPIO22_GPIO22 MFP_CFG(GPIO22, AF0)
#define GPIO23_GPIO23 MFP_CFG(GPIO23, AF0)
#define GPIO24_GPIO24 MFP_CFG(GPIO24, AF0)
#define GPIO25_GPIO25 MFP_CFG(GPIO25, AF0)
#define GPIO26_GPIO26 MFP_CFG(GPIO26, AF0)
#define GPIO27_GPIO27 MFP_CFG(GPIO27, AF0)
#define GPIO28_GPIO28 MFP_CFG(GPIO28, AF0)
#define GPIO29_GPIO29 MFP_CFG(GPIO29, AF0)
#define GPIO30_GPIO30 MFP_CFG(GPIO30, AF0)
#define GPIO31_GPIO31 MFP_CFG(GPIO31, AF0)
#define GPIO32_GPIO32 MFP_CFG(GPIO32, AF0)
#define GPIO33_GPIO33 MFP_CFG(GPIO33, AF0)
#define GPIO34_GPIO34 MFP_CFG(GPIO34, AF0)
#define GPIO35_GPIO35 MFP_CFG(GPIO35, AF0)
#define GPIO36_GPIO36 MFP_CFG(GPIO36, AF0)
#define GPIO37_GPIO37 MFP_CFG(GPIO37, AF0)
#define GPIO38_GPIO38 MFP_CFG(GPIO38, AF0)
#define GPIO39_GPIO39 MFP_CFG(GPIO39, AF0)
#define GPIO40_GPIO40 MFP_CFG(GPIO40, AF0)
#define GPIO41_GPIO41 MFP_CFG(GPIO41, AF0)
#define GPIO42_GPIO42 MFP_CFG(GPIO42, AF0)
#define GPIO43_GPIO43 MFP_CFG(GPIO43, AF0)
#define GPIO44_GPIO44 MFP_CFG(GPIO44, AF0)
#define GPIO45_GPIO45 MFP_CFG(GPIO45, AF0)
#define GPIO46_GPIO46 MFP_CFG(GPIO46, AF0)
#define GPIO47_GPIO47 MFP_CFG(GPIO47, AF0)
#define GPIO48_GPIO48 MFP_CFG(GPIO48, AF0)
#define GPIO49_GPIO49 MFP_CFG(GPIO49, AF0)
#define GPIO50_GPIO50 MFP_CFG(GPIO50, AF0)
#define GPIO51_GPIO51 MFP_CFG(GPIO51, AF0)
#define GPIO52_GPIO52 MFP_CFG(GPIO52, AF0)
#define GPIO53_GPIO53 MFP_CFG(GPIO53, AF0)
#define GPIO54_GPIO54 MFP_CFG(GPIO54, AF0)
#define GPIO55_GPIO55 MFP_CFG(GPIO55, AF0)
#define GPIO56_GPIO56 MFP_CFG(GPIO56, AF0)
#define GPIO57_GPIO57 MFP_CFG(GPIO57, AF0)
#define GPIO58_GPIO58 MFP_CFG(GPIO58, AF0)
#define GPIO59_GPIO59 MFP_CFG(GPIO59, AF0)
#define GPIO60_GPIO60 MFP_CFG(GPIO60, AF0)
#define GPIO61_GPIO61 MFP_CFG(GPIO61, AF0)
#define GPIO62_GPIO62 MFP_CFG(GPIO62, AF0)
#define GPIO63_GPIO63 MFP_CFG(GPIO63, AF0)
#define GPIO64_GPIO64 MFP_CFG(GPIO64, AF0)
#define GPIO65_GPIO65 MFP_CFG(GPIO65, AF0)
#define GPIO66_GPIO66 MFP_CFG(GPIO66, AF0)
#define GPIO67_GPIO67 MFP_CFG(GPIO67, AF0)
#define GPIO68_GPIO68 MFP_CFG(GPIO68, AF0)
#define GPIO69_GPIO69 MFP_CFG(GPIO69, AF0)
#define GPIO70_GPIO70 MFP_CFG(GPIO70, AF0)
#define GPIO71_GPIO71 MFP_CFG(GPIO71, AF0)
#define GPIO72_GPIO72 MFP_CFG(GPIO72, AF0)
#define GPIO73_GPIO73 MFP_CFG(GPIO73, AF0)
#define GPIO74_GPIO74 MFP_CFG(GPIO74, AF0)
#define GPIO75_GPIO75 MFP_CFG(GPIO75, AF0)
#define GPIO76_GPIO76 MFP_CFG(GPIO76, AF0)
#define GPIO77_GPIO77 MFP_CFG(GPIO77, AF0)
#define GPIO78_GPIO78 MFP_CFG(GPIO78, AF0)
#define GPIO79_GPIO79 MFP_CFG(GPIO79, AF0)
#define GPIO80_GPIO80 MFP_CFG(GPIO80, AF0)
#define GPIO81_GPIO81 MFP_CFG(GPIO81, AF0)
#define GPIO82_GPIO82 MFP_CFG(GPIO82, AF0)
#define GPIO83_GPIO83 MFP_CFG(GPIO83, AF0)
#define GPIO84_GPIO84 MFP_CFG(GPIO84, AF0)
#define GPIO85_GPIO85 MFP_CFG(GPIO85, AF0)
#define GPIO86_GPIO86 MFP_CFG(GPIO86, AF0)
#define GPIO87_GPIO87 MFP_CFG(GPIO87, AF0)
#define GPIO88_GPIO88 MFP_CFG(GPIO88, AF0)
#define GPIO89_GPIO89 MFP_CFG(GPIO89, AF0)
#define GPIO90_GPIO90 MFP_CFG(GPIO90, AF0)
#define GPIO91_GPIO91 MFP_CFG(GPIO91, AF0)
#define GPIO92_GPIO92 MFP_CFG(GPIO92, AF0)
#define GPIO93_GPIO93 MFP_CFG(GPIO93, AF0)
#define GPIO94_GPIO94 MFP_CFG(GPIO94, AF0)
#define GPIO95_GPIO95 MFP_CFG(GPIO95, AF0)
#define GPIO96_GPIO96 MFP_CFG(GPIO96, AF0)
#define GPIO97_GPIO97 MFP_CFG(GPIO97, AF0)
#define GPIO98_GPIO98 MFP_CFG(GPIO98, AF0)
#define GPIO99_GPIO99 MFP_CFG(GPIO99, AF0)
#define GPIO100_GPIO100 MFP_CFG(GPIO100, AF0)
#define GPIO101_GPIO101 MFP_CFG(GPIO101, AF0)
#define GPIO102_GPIO102 MFP_CFG(GPIO102, AF1)
#define GPIO103_GPIO103 MFP_CFG(GPIO103, AF1)
#define GPIO104_GPIO104 MFP_CFG(GPIO104, AF1)
#define GPIO105_GPIO105 MFP_CFG(GPIO105, AF1)
#define GPIO106_GPIO106 MFP_CFG(GPIO106, AF1)
#define GPIO107_GPIO107 MFP_CFG(GPIO107, AF1)
#define GPIO108_GPIO108 MFP_CFG(GPIO108, AF1)
#define GPIO109_GPIO109 MFP_CFG(GPIO109, AF1)
#define GPIO110_GPIO110 MFP_CFG(GPIO110, AF1)
#define GPIO111_GPIO111 MFP_CFG(GPIO111, AF1)
#define GPIO112_GPIO112 MFP_CFG(GPIO112, AF1)
#define GPIO113_GPIO113 MFP_CFG(GPIO113, AF1)
#define GPIO114_GPIO114 MFP_CFG(GPIO114, AF0)
#define GPIO115_GPIO115 MFP_CFG(GPIO115, AF0)
#define GPIO116_GPIO116 MFP_CFG(GPIO116, AF0)
#define GPIO117_GPIO117 MFP_CFG(GPIO117, AF0)
#define GPIO118_GPIO118 MFP_CFG(GPIO118, AF0)
#define GPIO119_GPIO119 MFP_CFG(GPIO119, AF0)
#define GPIO120_GPIO120 MFP_CFG(GPIO120, AF0)
#define GPIO121_GPIO121 MFP_CFG(GPIO121, AF0)
#define GPIO122_GPIO122 MFP_CFG(GPIO122, AF0)
#define GPIO123_GPIO123 MFP_CFG(GPIO123, AF0)
#define GPIO124_GPIO124 MFP_CFG(GPIO124, AF0)
#define GPIO125_GPIO125 MFP_CFG(GPIO125, AF0)
#define GPIO126_GPIO126 MFP_CFG(GPIO126, AF0)
#define GPIO127_GPIO127 MFP_CFG(GPIO127, AF0)
#define GPIO128_GPIO128 MFP_CFG(GPIO128, AF0)
#define GPIO129_GPIO129 MFP_CFG(GPIO129, AF0)
#define GPIO130_GPIO130 MFP_CFG(GPIO130, AF0)
#define GPIO131_GPIO131 MFP_CFG(GPIO131, AF0)
#define GPIO132_GPIO132 MFP_CFG(GPIO132, AF0)
#define GPIO133_GPIO133 MFP_CFG(GPIO133, AF0)
#define GPIO134_GPIO134 MFP_CFG(GPIO134, AF0)
#define GPIO135_GPIO135 MFP_CFG(GPIO135, AF0)
#define GPIO136_GPIO136 MFP_CFG(GPIO136, AF0)
#define GPIO137_GPIO137 MFP_CFG(GPIO137, AF0)
#define GPIO138_GPIO138 MFP_CFG(GPIO138, AF0)
#define GPIO139_GPIO139 MFP_CFG(GPIO139, AF0)
#define GPIO140_GPIO140 MFP_CFG(GPIO140, AF0)
#define GPIO141_GPIO141 MFP_CFG(GPIO141, AF0)
#define GPIO142_GPIO142 MFP_CFG(GPIO142, AF1)
#define GPIO143_GPIO143 MFP_CFG(GPIO143, AF1)
#define GPIO144_GPIO144 MFP_CFG(GPIO144, AF1)
#define GPIO145_GPIO145 MFP_CFG(GPIO145, AF1)
#define GPIO146_GPIO146 MFP_CFG(GPIO146, AF1)
#define GPIO147_GPIO147 MFP_CFG(GPIO147, AF1)
#define GPIO148_GPIO148 MFP_CFG(GPIO148, AF1)
#define GPIO149_GPIO149 MFP_CFG(GPIO149, AF1)
#define GPIO150_GPIO150 MFP_CFG(GPIO150, AF1)
#define GPIO151_GPIO151 MFP_CFG(GPIO151, AF1)
#define GPIO152_GPIO152 MFP_CFG(GPIO152, AF1)
#define GPIO153_GPIO153 MFP_CFG(GPIO153, AF1)
#define GPIO154_GPIO154 MFP_CFG(GPIO154, AF1)
#define GPIO155_GPIO155 MFP_CFG(GPIO155, AF1)
#define GPIO156_GPIO156 MFP_CFG(GPIO156, AF1)
#define GPIO157_GPIO157 MFP_CFG(GPIO157, AF1)
#define GPIO158_GPIO158 MFP_CFG(GPIO158, AF1)
#define GPIO159_GPIO159 MFP_CFG(GPIO159, AF1)
#define GPIO160_GPIO160 MFP_CFG(GPIO160, AF1)
#define GPIO161_GPIO161 MFP_CFG(GPIO161, AF1)
#define GPIO162_GPIO162 MFP_CFG(GPIO162, AF1)
#define GPIO163_GPIO163 MFP_CFG(GPIO163, AF1)
#define GPIO164_GPIO164 MFP_CFG(GPIO164, AF1)
#define GPIO165_GPIO165 MFP_CFG(GPIO165, AF1)
#define GPIO166_GPIO166 MFP_CFG(GPIO166, AF1)
#define GPIO167_GPIO167 MFP_CFG(GPIO167, AF1)
#define GPIO168_GPIO168 MFP_CFG(GPIO168, AF1)
#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
#define GPIO46_GPIO MFP_CFG(GPIO46, AF0)
#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
#define GPIO102_GPIO MFP_CFG(GPIO102, AF1)
#define GPIO103_GPIO MFP_CFG(GPIO103, AF1)
#define GPIO104_GPIO MFP_CFG(GPIO104, AF1)
#define GPIO105_GPIO MFP_CFG(GPIO105, AF1)
#define GPIO106_GPIO MFP_CFG(GPIO106, AF1)
#define GPIO107_GPIO MFP_CFG(GPIO107, AF1)
#define GPIO108_GPIO MFP_CFG(GPIO108, AF1)
#define GPIO109_GPIO MFP_CFG(GPIO109, AF1)
#define GPIO110_GPIO MFP_CFG(GPIO110, AF1)
#define GPIO111_GPIO MFP_CFG(GPIO111, AF1)
#define GPIO112_GPIO MFP_CFG(GPIO112, AF1)
#define GPIO113_GPIO MFP_CFG(GPIO113, AF1)
#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
#define GPIO128_GPIO MFP_CFG(GPIO128, AF0)
#define GPIO129_GPIO MFP_CFG(GPIO129, AF0)
#define GPIO130_GPIO MFP_CFG(GPIO130, AF0)
#define GPIO131_GPIO MFP_CFG(GPIO131, AF0)
#define GPIO132_GPIO MFP_CFG(GPIO132, AF0)
#define GPIO133_GPIO MFP_CFG(GPIO133, AF0)
#define GPIO134_GPIO MFP_CFG(GPIO134, AF0)
#define GPIO135_GPIO MFP_CFG(GPIO135, AF0)
#define GPIO136_GPIO MFP_CFG(GPIO136, AF0)
#define GPIO137_GPIO MFP_CFG(GPIO137, AF0)
#define GPIO138_GPIO MFP_CFG(GPIO138, AF0)
#define GPIO139_GPIO MFP_CFG(GPIO139, AF0)
#define GPIO140_GPIO MFP_CFG(GPIO140, AF0)
#define GPIO141_GPIO MFP_CFG(GPIO141, AF0)
#define GPIO142_GPIO MFP_CFG(GPIO142, AF1)
#define GPIO143_GPIO MFP_CFG(GPIO143, AF1)
#define GPIO144_GPIO MFP_CFG(GPIO144, AF1)
#define GPIO145_GPIO MFP_CFG(GPIO145, AF1)
#define GPIO146_GPIO MFP_CFG(GPIO146, AF1)
#define GPIO147_GPIO MFP_CFG(GPIO147, AF1)
#define GPIO148_GPIO MFP_CFG(GPIO148, AF1)
#define GPIO149_GPIO MFP_CFG(GPIO149, AF1)
#define GPIO150_GPIO MFP_CFG(GPIO150, AF1)
#define GPIO151_GPIO MFP_CFG(GPIO151, AF1)
#define GPIO152_GPIO MFP_CFG(GPIO152, AF1)
#define GPIO153_GPIO MFP_CFG(GPIO153, AF1)
#define GPIO154_GPIO MFP_CFG(GPIO154, AF1)
#define GPIO155_GPIO MFP_CFG(GPIO155, AF1)
#define GPIO156_GPIO MFP_CFG(GPIO156, AF1)
#define GPIO157_GPIO MFP_CFG(GPIO157, AF1)
#define GPIO158_GPIO MFP_CFG(GPIO158, AF1)
#define GPIO159_GPIO MFP_CFG(GPIO159, AF1)
#define GPIO160_GPIO MFP_CFG(GPIO160, AF1)
#define GPIO161_GPIO MFP_CFG(GPIO161, AF1)
#define GPIO162_GPIO MFP_CFG(GPIO162, AF1)
#define GPIO163_GPIO MFP_CFG(GPIO163, AF1)
#define GPIO164_GPIO MFP_CFG(GPIO164, AF1)
#define GPIO165_GPIO MFP_CFG(GPIO165, AF1)
#define GPIO166_GPIO MFP_CFG(GPIO166, AF1)
#define GPIO167_GPIO MFP_CFG(GPIO167, AF1)
#define GPIO168_GPIO MFP_CFG(GPIO168, AF1)
/* DFI */
#define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0)

22
arch/arm/mach-mmp/include/mach/mmp2.h
View File

@ -1,6 +1,8 @@
#ifndef __ASM_MACH_MMP2_H
#define __ASM_MACH_MMP2_H
#include <plat/sdhci.h>
struct sys_timer;
extern struct sys_timer mmp2_timer;
@ -22,6 +24,10 @@ extern struct pxa_device_desc mmp2_device_twsi3;
extern struct pxa_device_desc mmp2_device_twsi4;
extern struct pxa_device_desc mmp2_device_twsi5;
extern struct pxa_device_desc mmp2_device_twsi6;
extern struct pxa_device_desc mmp2_device_sdh0;
extern struct pxa_device_desc mmp2_device_sdh1;
extern struct pxa_device_desc mmp2_device_sdh2;
extern struct pxa_device_desc mmp2_device_sdh3;
static inline int mmp2_add_uart(int id)
{
@ -63,5 +69,21 @@ static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data,
return pxa_register_device(d, data, sizeof(*data));
}
static inline int mmp2_add_sdhost(int id, struct sdhci_pxa_platdata *data)
{
struct pxa_device_desc *d = NULL;
switch (id) {
case 0: d = &mmp2_device_sdh0; break;
case 1: d = &mmp2_device_sdh1; break;
case 2: d = &mmp2_device_sdh2; break;
case 3: d = &mmp2_device_sdh3; break;
default:
return -EINVAL;
}
return pxa_register_device(d, data, sizeof(*data));
}
#endif /* __ASM_MACH_MMP2_H */

2
arch/arm/mach-mmp/include/mach/regs-apmu.h
View File

@ -27,6 +27,8 @@
#define APMU_DMA APMU_REG(0x064)
#define APMU_GEU APMU_REG(0x068)
#define APMU_BUS APMU_REG(0x06c)
#define APMU_SDH2 APMU_REG(0x0e8)
#define APMU_SDH3 APMU_REG(0x0ec)
#define APMU_FNCLK_EN (1 << 4)
#define APMU_AXICLK_EN (1 << 3)

35
arch/arm/mach-mmp/jasper.c
View File

@ -67,6 +67,36 @@ static unsigned long jasper_pin_config[] __initdata = {
/* PMIC */
PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
/* MMC1 */
GPIO131_MMC1_DAT3,
GPIO132_MMC1_DAT2,
GPIO133_MMC1_DAT1,
GPIO134_MMC1_DAT0,
GPIO136_MMC1_CMD,
GPIO139_MMC1_CLK,
GPIO140_MMC1_CD,
GPIO141_MMC1_WP,
/* MMC2 */
GPIO37_MMC2_DAT3,
GPIO38_MMC2_DAT2,
GPIO39_MMC2_DAT1,
GPIO40_MMC2_DAT0,
GPIO41_MMC2_CMD,
GPIO42_MMC2_CLK,
/* MMC3 */
GPIO165_MMC3_DAT7,
GPIO162_MMC3_DAT6,
GPIO166_MMC3_DAT5,
GPIO163_MMC3_DAT4,
GPIO167_MMC3_DAT3,
GPIO164_MMC3_DAT2,
GPIO168_MMC3_DAT1,
GPIO111_MMC3_DAT0,
GPIO112_MMC3_CMD,
GPIO151_MMC3_CLK,
};
static struct regulator_consumer_supply max8649_supply[] = {
@ -123,6 +153,10 @@ static struct i2c_board_info jasper_twsi1_info[] = {
},
};
static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
.max_speed = 25000000,
};
static void __init jasper_init(void)
{
mfp_config(ARRAY_AND_SIZE(jasper_pin_config));
@ -131,6 +165,7 @@ static void __init jasper_init(void)
mmp2_add_uart(1);
mmp2_add_uart(3);
mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));
mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
regulator_has_full_constraints();
}

36
arch/arm/mach-mmp/mmp2.c
View File

@ -115,6 +115,29 @@ void __init mmp2_init_irq(void)
mmp2_init_gpio();
}
static void sdhc_clk_enable(struct clk *clk)
{
uint32_t clk_rst;
clk_rst = __raw_readl(clk->clk_rst);
clk_rst |= clk->enable_val;
__raw_writel(clk_rst, clk->clk_rst);
}
static void sdhc_clk_disable(struct clk *clk)
{
uint32_t clk_rst;
clk_rst = __raw_readl(clk->clk_rst);
clk_rst &= ~clk->enable_val;
__raw_writel(clk_rst, clk->clk_rst);
}
struct clkops sdhc_clk_ops = {
.enable = sdhc_clk_enable,
.disable = sdhc_clk_disable,
};
/* APB peripheral clocks */
static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
@ -126,9 +149,12 @@ static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
static APBC_CLK(rtc, MMP2_RTC, 0, 32768);
static APMU_CLK(nand, NAND, 0xbf, 100000000);
static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
static struct clk_lookup mmp2_clkregs[] = {
INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
@ -142,6 +168,10 @@ static struct clk_lookup mmp2_clkregs[] = {
INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
INIT_CLKREG(&clk_sdh0, "sdhci-pxa.0", "PXA-SDHCLK"),
INIT_CLKREG(&clk_sdh1, "sdhci-pxa.1", "PXA-SDHCLK"),
INIT_CLKREG(&clk_sdh2, "sdhci-pxa.2", "PXA-SDHCLK"),
INIT_CLKREG(&clk_sdh3, "sdhci-pxa.3", "PXA-SDHCLK"),
};
static int __init mmp2_init(void)
@ -192,4 +222,8 @@ MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
MMP2_DEVICE(sdh0, "sdhci-pxa", 0, MMC, 0xd4280000, 0x120);
MMP2_DEVICE(sdh1, "sdhci-pxa", 1, MMC2, 0xd4280800, 0x120);
MMP2_DEVICE(sdh2, "sdhci-pxa", 2, MMC3, 0xd4281000, 0x120);
MMP2_DEVICE(sdh3, "sdhci-pxa", 3, MMC4, 0xd4281800, 0x120);

2
arch/arm/mach-mmp/pxa910.c
View File

@ -111,6 +111,7 @@ static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
static APMU_CLK(nand, NAND, 0x01db, 208000000);
static APMU_CLK(u2o, USB, 0x1b, 480000000);
/* device and clock bindings */
static struct clk_lookup pxa910_clkregs[] = {
@ -123,6 +124,7 @@ static struct clk_lookup pxa910_clkregs[] = {
INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"),
};
static int __init pxa910_init(void)

2
arch/arm/mach-omap2/board-zoom-peripherals.c
View File

@ -216,7 +216,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
{
.name = "wl1271",
.mmc = 3,
.caps = MMC_CAP_4_BIT_DATA,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
.gpio_wp = -EINVAL,
.gpio_cd = -EINVAL,
.nonremovable = true,

2
arch/arm/mach-omap2/io.c
View File

@ -297,7 +297,7 @@ static int __init _omap2_init_reprogram_sdrc(void)
return 0;
dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
if (!dpll3_m2_ck)
if (IS_ERR(dpll3_m2_ck))
return -EINVAL;
rate = clk_get_rate(dpll3_m2_ck);

34
arch/arm/mach-omap2/pm-debug.c
View File

@ -161,6 +161,23 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
}
void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
{
u32 tick_rate, cycles;
if (!seconds && !milliseconds)
return;
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
omap_dm_timer_stop(gptimer_wakeup);
omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
pr_info("PM: Resume timer in %u.%03u secs"
" (%d ticks at %d ticks/sec.)\n",
seconds, milliseconds, cycles, tick_rate);
}
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/seq_file.h>
@ -354,23 +371,6 @@ void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
pwrdm->timer = t;
}
void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
{
u32 tick_rate, cycles;
if (!seconds && !milliseconds)
return;
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
omap_dm_timer_stop(gptimer_wakeup);
omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
pr_info("PM: Resume timer in %u.%03u secs"
" (%d ticks at %d ticks/sec.)\n",
seconds, milliseconds, cycles, tick_rate);
}
static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
{
struct seq_file *s = (struct seq_file *)user;

34
arch/arm/mach-omap2/pm24xx.c
View File

@ -53,6 +53,19 @@
#include <plat/powerdomain.h>
#include <plat/clockdomain.h>
#ifdef CONFIG_SUSPEND
static suspend_state_t suspend_state = PM_SUSPEND_ON;
static inline bool is_suspending(void)
{
return (suspend_state != PM_SUSPEND_ON);
}
#else
static inline bool is_suspending(void)
{
return false;
}
#endif
static void (*omap2_sram_idle)(void);
static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
void __iomem *sdrc_power);
@ -120,8 +133,9 @@ static void omap2_enter_full_retention(void)
goto no_sleep;
/* Block console output in case it is on one of the OMAP UARTs */
if (try_acquire_console_sem())
goto no_sleep;
if (!is_suspending())
if (try_acquire_console_sem())
goto no_sleep;
omap_uart_prepare_idle(0);
omap_uart_prepare_idle(1);
@ -136,7 +150,8 @@ static void omap2_enter_full_retention(void)
omap_uart_resume_idle(1);
omap_uart_resume_idle(0);
release_console_sem();
if (!is_suspending())
release_console_sem();
no_sleep:
if (omap2_pm_debug) {
@ -284,6 +299,12 @@ static void omap2_pm_idle(void)
local_irq_enable();
}
static int omap2_pm_begin(suspend_state_t state)
{
suspend_state = state;
return 0;
}
static int omap2_pm_prepare(void)
{
/* We cannot sleep in idle until we have resumed */
@ -333,10 +354,17 @@ static void omap2_pm_finish(void)
enable_hlt();
}
static void omap2_pm_end(void)
{
suspend_state = PM_SUSPEND_ON;
}
static struct platform_suspend_ops omap_pm_ops = {
.begin = omap2_pm_begin,
.prepare = omap2_pm_prepare,
.enter = omap2_pm_enter,
.finish = omap2_pm_finish,
.end = omap2_pm_end,
.valid = suspend_valid_only_mem,
};

27
arch/arm/mach-omap2/pm34xx.c
View File

@ -50,6 +50,19 @@
#include "sdrc.h"
#include "control.h"
#ifdef CONFIG_SUSPEND
static suspend_state_t suspend_state = PM_SUSPEND_ON;
static inline bool is_suspending(void)
{
return (suspend_state != PM_SUSPEND_ON);
}
#else
static inline bool is_suspending(void)
{
return false;
}
#endif
/* Scratchpad offsets */
#define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4
#define OMAP343X_TABLE_VALUE_OFFSET 0xc0
@ -387,10 +400,11 @@ void omap_sram_idle(void)
}
/* Block console output in case it is on one of the OMAP UARTs */
if (per_next_state < PWRDM_POWER_ON ||
core_next_state < PWRDM_POWER_ON)
if (try_acquire_console_sem())
goto console_still_active;
if (!is_suspending())
if (per_next_state < PWRDM_POWER_ON ||
core_next_state < PWRDM_POWER_ON)
if (try_acquire_console_sem())
goto console_still_active;
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
@ -470,7 +484,8 @@ void omap_sram_idle(void)
omap_uart_resume_idle(3);
}
release_console_sem();
if (!is_suspending())
release_console_sem();
console_still_active:
/* Disable IO-PAD and IO-CHAIN wakeup */
@ -514,8 +529,6 @@ static void omap3_pm_idle(void)
}
#ifdef CONFIG_SUSPEND
static suspend_state_t suspend_state;
static int omap3_pm_prepare(void)
{
disable_hlt();

11
arch/arm/mach-omap2/prcm-common.h
View File

@ -243,13 +243,14 @@
#define OMAP24XX_EN_GPT1_MASK (1 << 0)
/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
#define OMAP24XX_ST_GPIOS_SHIFT (1 << 2)
#define OMAP24XX_ST_GPIOS_MASK 2
#define OMAP24XX_ST_GPT1_SHIFT (1 << 0)
#define OMAP24XX_ST_GPT1_MASK 0
#define OMAP24XX_ST_GPIOS_SHIFT 2
#define OMAP24XX_ST_GPIOS_MASK (1 << 2)
#define OMAP24XX_ST_GPT1_SHIFT 0
#define OMAP24XX_ST_GPT1_MASK (1 << 0)
/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
#define OMAP2430_ST_MDM_SHIFT (1 << 0)
#define OMAP2430_ST_MDM_SHIFT 0
#define OMAP2430_ST_MDM_MASK (1 << 0)
/* 3430 register bits shared between CM & PRM registers */

24
arch/arm/mach-pxa/Kconfig
View File

@ -50,6 +50,10 @@ config MACH_SAAR
select PXA3xx
select CPU_PXA930
config MACH_SAARB
bool "PXA955 Handheld Platform (aka SAARB)"
select CPU_PXA955
comment "Third Party Dev Platforms (sorted by vendor name)"
config ARCH_PXA_IDP
@ -232,10 +236,6 @@ config MACH_COLIBRI
bool "Toradex Colibri PXA270"
select PXA27x
config MACH_COLIBRI_PXA270_EVALBOARD
bool "Toradex Colibri Evaluation Carrier Board support (PXA270)"
depends on MACH_COLIBRI
config MACH_COLIBRI_PXA270_INCOME
bool "Income s.r.o. PXA270 SBC"
depends on MACH_COLIBRI
@ -253,6 +253,10 @@ config MACH_COLIBRI320
select PXA3xx
select CPU_PXA320
config MACH_COLIBRI_EVALBOARD
bool "Toradex Colibri Evaluation Carrier Board support"
depends on MACH_COLIBRI || MACH_COLIBRI300 || MACH_COLIBRI320
config MACH_VPAC270
bool "Voipac PXA270"
select PXA27x
@ -651,11 +655,17 @@ config CPU_PXA935
help
PXA935 (codename Tavor-P65)
config CPU_PXA950
config PXA95x
bool
select CPU_PXA930
select CPU_PJ4
help
PXA950 (codename Tavor-PV2)
Select code specific to PXA95x variants
config CPU_PXA955
bool
select PXA95x
help
PXA950 (codename MG1)
config PXA_SHARP_C7xx
bool

10
arch/arm/mach-pxa/Makefile
View File

@ -16,9 +16,10 @@ endif
# Generic drivers that other drivers may depend upon
# SoC-specific code
obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o
obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o
obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o
obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o
obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
obj-$(CONFIG_PXA95x) += mfp-pxa3xx.o clock-pxa3xx.o pxa95x.o smemc.o
obj-$(CONFIG_CPU_PXA300) += pxa300.o
obj-$(CONFIG_CPU_PXA320) += pxa320.o
obj-$(CONFIG_CPU_PXA930) += pxa930.o
@ -34,6 +35,7 @@ obj-$(CONFIG_MACH_LITTLETON) += littleton.o
obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
obj-$(CONFIG_MACH_TAVOREVB3) += tavorevb3.o
obj-$(CONFIG_MACH_SAAR) += saar.o
obj-$(CONFIG_MACH_SAARB) += saarb.o
# 3rd Party Dev Platforms
obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
@ -60,7 +62,7 @@ obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
obj-$(CONFIG_MACH_PCM027) += pcm027.o
obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o
obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o
obj-$(CONFIG_MACH_COLIBRI_PXA270_EVALBOARD) += colibri-pxa270-evalboard.o
obj-$(CONFIG_MACH_COLIBRI_EVALBOARD) += colibri-evalboard.o
obj-$(CONFIG_MACH_COLIBRI_PXA270_INCOME) += colibri-pxa270-income.o
obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o
obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o

57
arch/arm/mach-pxa/balloon3.c
View File

@ -567,27 +567,29 @@ static inline void balloon3_i2c_init(void) {}
* NAND
******************************************************************************/
#if defined(CONFIG_MTD_NAND_PLATFORM)||defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
static uint16_t balloon3_ctl =
BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 |
BALLOON3_NAND_CONTROL_FLWP;
static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
uint8_t balloon3_ctl_set = 0, balloon3_ctl_clr = 0;
if (ctrl & NAND_CTRL_CHANGE) {
if (ctrl & NAND_CLE)
balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCLE;
balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLCLE;
else
balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLCLE;
balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLCLE;
if (ctrl & NAND_ALE)
balloon3_ctl |= BALLOON3_NAND_CONTROL_FLALE;
balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLALE;
else
balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLALE;
balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLALE;
__raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
if (balloon3_ctl_clr)
__raw_writel(balloon3_ctl_clr,
BALLOON3_NAND_CONTROL_REG);
if (balloon3_ctl_set)
__raw_writel(balloon3_ctl_set,
BALLOON3_NAND_CONTROL_REG |
BALLOON3_FPGA_SETnCLR);
}
if (cmd != NAND_CMD_NONE)
@ -599,28 +601,33 @@ static void balloon3_nand_select_chip(struct mtd_info *mtd, int chip)
if (chip < 0 || chip > 3)
return;
balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCE0 |
BALLOON3_NAND_CONTROL_FLCE1 |
BALLOON3_NAND_CONTROL_FLCE2 |
BALLOON3_NAND_CONTROL_FLCE3;
/* Assert all nCE lines */
__raw_writew(
BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3,
BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR);
/* Deassert correct nCE line */
balloon3_ctl &= ~(BALLOON3_NAND_CONTROL_FLCE0 << chip);
__raw_writew(BALLOON3_NAND_CONTROL_FLCE0 << chip,
BALLOON3_NAND_CONTROL_REG);
}
__raw_writew(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
static int balloon3_nand_dev_ready(struct mtd_info *mtd)
{
return __raw_readl(BALLOON3_NAND_STAT_REG) & BALLOON3_NAND_STAT_RNB;
}
static int balloon3_nand_probe(struct platform_device *pdev)
{
void __iomem *temp_map;
uint16_t ver;
int ret;
__raw_writew(BALLOON3_NAND_CONTROL2_16BIT, BALLOON3_NAND_CONTROL2_REG);
__raw_writew(BALLOON3_NAND_CONTROL2_16BIT,
BALLOON3_NAND_CONTROL2_REG | BALLOON3_FPGA_SETnCLR);
ver = __raw_readw(BALLOON3_FPGA_VER);
if (ver > 0x0201)
pr_warn("The FPGA code, version 0x%04x, is newer than rel-0.3. "
if (ver < 0x4f08)
pr_warn("The FPGA code, version 0x%04x, is too old. "
"NAND support might be broken in this version!", ver);
/* Power up the NAND chips */
@ -635,7 +642,11 @@ static int balloon3_nand_probe(struct platform_device *pdev)
gpio_set_value(BALLOON3_GPIO_RUN_NAND, 1);
/* Deassert all nCE lines and write protect line */
__raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
__raw_writel(
BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 |
BALLOON3_NAND_CONTROL_FLWP,
BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR);
return 0;
err2:
@ -677,7 +688,7 @@ struct platform_nand_data balloon3_nand_pdata = {
},
.ctrl = {
.hwcontrol = 0,
.dev_ready = 0,
.dev_ready = balloon3_nand_dev_ready,
.select_chip = balloon3_nand_select_chip,
.cmd_ctrl = balloon3_nand_cmd_ctl,
.probe = balloon3_nand_probe,
@ -802,7 +813,7 @@ static struct map_desc balloon3_io_desc[] __initdata = {
static void __init balloon3_map_io(void)
{
pxa_map_io();
pxa27x_map_io();
iotable_init(balloon3_io_desc, ARRAY_SIZE(balloon3_io_desc));
}

2
arch/arm/mach-pxa/capc7117.c
View File

@ -149,7 +149,7 @@ static void __init capc7117_init(void)
MACHINE_START(CAPC7117,
"Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
.timer = &pxa_timer,
.init_machine = capc7117_init

64
arch/arm/mach-pxa/clock-pxa2xx.c Normal file
View File

@ -0,0 +1,64 @@
/*
* linux/arch/arm/mach-pxa/clock-pxa2xx.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/sysdev.h>
#include <mach/pxa2xx-regs.h>
#include "clock.h"
void clk_pxa2xx_cken_enable(struct clk *clk)
{
CKEN |= 1 << clk->cken;
}
void clk_pxa2xx_cken_disable(struct clk *clk)
{
CKEN &= ~(1 << clk->cken);
}
const struct clkops clk_pxa2xx_cken_ops = {
.enable = clk_pxa2xx_cken_enable,
.disable = clk_pxa2xx_cken_disable,
};
#ifdef CONFIG_PM
static uint32_t saved_cken;
static int pxa2xx_clock_suspend(struct sys_device *d, pm_message_t state)
{
saved_cken = CKEN;
return 0;
}
static int pxa2xx_clock_resume(struct sys_device *d)
{
CKEN = saved_cken;
return 0;
}
#else
#define pxa2xx_clock_suspend NULL
#define pxa2xx_clock_resume NULL
#endif
struct sysdev_class pxa2xx_clock_sysclass = {
.name = "pxa2xx-clock",
.suspend = pxa2xx_clock_suspend,
.resume = pxa2xx_clock_resume,
};
static int __init pxa2xx_clock_init(void)
{
if (cpu_is_pxa2xx())
return sysdev_class_register(&pxa2xx_clock_sysclass);
return 0;
}
postcore_initcall(pxa2xx_clock_init);

218
arch/arm/mach-pxa/clock-pxa3xx.c Normal file
View File

@ -0,0 +1,218 @@
/*
* linux/arch/arm/mach-pxa/clock-pxa3xx.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <mach/smemc.h>
#include <mach/pxa3xx-regs.h>
#include "clock.h"
/* Crystal clock: 13MHz */
#define BASE_CLK 13000000
/* Ring Oscillator Clock: 60MHz */
#define RO_CLK 60000000
#define ACCR_D0CS (1 << 26)
#define ACCR_PCCE (1 << 11)
/* crystal frequency to HSIO bus frequency multiplier (HSS) */
static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
/*
* Get the clock frequency as reflected by CCSR and the turbo flag.
* We assume these values have been applied via a fcs.
* If info is not 0 we also display the current settings.
*/
unsigned int pxa3xx_get_clk_frequency_khz(int info)
{
unsigned long acsr, xclkcfg;
unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
/* Read XCLKCFG register turbo bit */
__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
t = xclkcfg & 0x1;
acsr = ACSR;
xl = acsr & 0x1f;
xn = (acsr >> 8) & 0x7;
hss = (acsr >> 14) & 0x3;
XL = xl * BASE_CLK;
XN = xn * XL;
ro = acsr & ACCR_D0CS;
CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
if (info) {
pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
(ro) ? "" : "in");
pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
XL / 1000000, (XL % 1000000) / 10000, xl);
pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
XN / 1000000, (XN % 1000000) / 10000, xn,
(t) ? "" : "in");
pr_info("HSIO bus clock: %d.%02dMHz\n",
HSS / 1000000, (HSS % 1000000) / 10000);
}
return CLK / 1000;
}
/*
* Return the current AC97 clock frequency.
*/
static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
{
unsigned long rate = 312000000;
unsigned long ac97_div;
ac97_div = AC97_DIV;
/* This may loose precision for some rates but won't for the
* standard 24.576MHz.
*/
rate /= (ac97_div >> 12) & 0x7fff;
rate *= (ac97_div & 0xfff);
return rate;
}
/*
* Return the current HSIO bus clock frequency
*/
static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
{
unsigned long acsr;
unsigned int hss, hsio_clk;
acsr = ACSR;
hss = (acsr >> 14) & 0x3;
hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
return hsio_clk;
}
/* crystal frequency to static memory controller multiplier (SMCFS) */
static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk)
{
unsigned long acsr = ACSR;
unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
unsigned int smcfs = (acsr >> 23) & 0x7;
return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] /
df_clkdiv[(memclkcfg >> 16) & 0x3];
}
void clk_pxa3xx_cken_enable(struct clk *clk)
{
unsigned long mask = 1ul << (clk->cken & 0x1f);
if (clk->cken < 32)
CKENA |= mask;
else
CKENB |= mask;
}
void clk_pxa3xx_cken_disable(struct clk *clk)
{
unsigned long mask = 1ul << (clk->cken & 0x1f);
if (clk->cken < 32)
CKENA &= ~mask;
else
CKENB &= ~mask;
}
const struct clkops clk_pxa3xx_cken_ops = {
.enable = clk_pxa3xx_cken_enable,
.disable = clk_pxa3xx_cken_disable,
};
const struct clkops clk_pxa3xx_hsio_ops = {
.enable = clk_pxa3xx_cken_enable,
.disable = clk_pxa3xx_cken_disable,
.getrate = clk_pxa3xx_hsio_getrate,
};
const struct clkops clk_pxa3xx_ac97_ops = {
.enable = clk_pxa3xx_cken_enable,
.disable = clk_pxa3xx_cken_disable,
.getrate = clk_pxa3xx_ac97_getrate,
};
const struct clkops clk_pxa3xx_smemc_ops = {
.enable = clk_pxa3xx_cken_enable,
.disable = clk_pxa3xx_cken_disable,
.getrate = clk_pxa3xx_smemc_getrate,
};
static void clk_pout_enable(struct clk *clk)
{
OSCC |= OSCC_PEN;
}
static void clk_pout_disable(struct clk *clk)
{
OSCC &= ~OSCC_PEN;
}
const struct clkops clk_pxa3xx_pout_ops = {
.enable = clk_pout_enable,
.disable = clk_pout_disable,
};
#ifdef CONFIG_PM
static uint32_t cken[2];
static uint32_t accr;
static int pxa3xx_clock_suspend(struct sys_device *d, pm_message_t state)
{
cken[0] = CKENA;
cken[1] = CKENB;
accr = ACCR;
return 0;
}
static int pxa3xx_clock_resume(struct sys_device *d)
{
ACCR = accr;
CKENA = cken[0];
CKENB = cken[1];
return 0;
}
#else
#define pxa3xx_clock_suspend NULL
#define pxa3xx_clock_resume NULL
#endif
struct sysdev_class pxa3xx_clock_sysclass = {
.name = "pxa3xx-clock",
.suspend = pxa3xx_clock_suspend,
.resume = pxa3xx_clock_resume,
};
static int __init pxa3xx_clock_init(void)
{
if (cpu_is_pxa3xx() || cpu_is_pxa95x())
return sysdev_class_register(&pxa3xx_clock_sysclass);
return 0;
}
postcore_initcall(pxa3xx_clock_init);

26
arch/arm/mach-pxa/clock.c
View File

@ -3,21 +3,12 @@
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <asm/clkdev.h>
#include <mach/pxa2xx-regs.h>
#include <mach/hardware.h>
#include "devices.h"
#include "generic.h"
#include "clock.h"
static DEFINE_SPINLOCK(clocks_lock);
@ -63,18 +54,19 @@ unsigned long clk_get_rate(struct clk *clk)
}
EXPORT_SYMBOL(clk_get_rate);
void clk_cken_enable(struct clk *clk)
void clk_dummy_enable(struct clk *clk)
{
CKEN |= 1 << clk->cken;
}
void clk_cken_disable(struct clk *clk)
void clk_dummy_disable(struct clk *clk)
{
CKEN &= ~(1 << clk->cken);
}
const struct clkops clk_cken_ops = {
.enable = clk_cken_enable,
.disable = clk_cken_disable,
const struct clkops clk_dummy_ops = {
.enable = clk_dummy_enable,
.disable = clk_dummy_disable,
};
struct clk clk_dummy = {
.ops = &clk_dummy_ops,
};

47
arch/arm/mach-pxa/clock.h
View File

@ -1,3 +1,4 @@
#include <linux/sysdev.h>
#include <asm/clkdev.h>
struct clkops {
@ -14,6 +15,12 @@ struct clk {
unsigned int enabled;
};
void clk_dummy_enable(struct clk *);
void clk_dummy_disable(struct clk *);
extern const struct clkops clk_dummy_ops;
extern struct clk clk_dummy;
#define INIT_CLKREG(_clk,_devname,_conname) \
{ \
.clk = _clk, \
@ -21,14 +28,6 @@ struct clk {
.con_id = _conname, \
}
#define DEFINE_CKEN(_name, _cken, _rate, _delay) \
struct clk clk_##_name = { \
.ops = &clk_cken_ops, \
.rate = _rate, \
.cken = CKEN_##_cken, \
.delay = _delay, \
}
#define DEFINE_CK(_name, _cken, _ops) \
struct clk clk_##_name = { \
.ops = _ops, \
@ -42,12 +41,22 @@ struct clk clk_##_name = { \
.delay = _delay, \
}
extern const struct clkops clk_cken_ops;
#define DEFINE_PXA2_CKEN(_name, _cken, _rate, _delay) \
struct clk clk_##_name = { \
.ops = &clk_pxa2xx_cken_ops, \
.rate = _rate, \
.cken = CKEN_##_cken, \
.delay = _delay, \
}
void clk_cken_enable(struct clk *clk);
void clk_cken_disable(struct clk *clk);
extern const struct clkops clk_pxa2xx_cken_ops;
#ifdef CONFIG_PXA3xx
void clk_pxa2xx_cken_enable(struct clk *clk);
void clk_pxa2xx_cken_disable(struct clk *clk);
extern struct sysdev_class pxa2xx_clock_sysclass;
#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay) \
struct clk clk_##_name = { \
.ops = &clk_pxa3xx_cken_ops, \
@ -56,14 +65,14 @@ struct clk clk_##_name = { \
.delay = _delay, \
}
#define DEFINE_PXA3_CK(_name, _cken, _ops) \
struct clk clk_##_name = { \
.ops = _ops, \
.cken = CKEN_##_cken, \
}
extern const struct clkops clk_pxa3xx_cken_ops;
extern const struct clkops clk_pxa3xx_hsio_ops;
extern const struct clkops clk_pxa3xx_ac97_ops;
extern const struct clkops clk_pxa3xx_pout_ops;
extern const struct clkops clk_pxa3xx_smemc_ops;
extern void clk_pxa3xx_cken_enable(struct clk *);
extern void clk_pxa3xx_cken_disable(struct clk *);
#endif
extern struct sysdev_class pxa3xx_clock_sysclass;
#endif

26
arch/arm/mach-pxa/cm-x2xx.c
View File

@ -24,6 +24,7 @@
#include <mach/pxa2xx-regs.h>
#include <mach/audio.h>
#include <mach/pxafb.h>
#include <mach/smemc.h>
#include <asm/hardware/it8152.h>
@ -392,9 +393,9 @@ static int cmx2xx_suspend(struct sys_device *dev, pm_message_t state)
cmx2xx_pci_suspend();
/* save MSC registers */
sleep_save_msc[0] = MSC0;
sleep_save_msc[1] = MSC1;
sleep_save_msc[2] = MSC2;
sleep_save_msc[0] = __raw_readl(MSC0);
sleep_save_msc[1] = __raw_readl(MSC1);
sleep_save_msc[2] = __raw_readl(MSC2);
/* setup power saving mode registers */
PCFR = 0x0;
@ -416,9 +417,9 @@ static int cmx2xx_resume(struct sys_device *dev)
cmx2xx_pci_resume();
/* restore MSC registers */
MSC0 = sleep_save_msc[0];
MSC1 = sleep_save_msc[1];
MSC2 = sleep_save_msc[2];
__raw_writel(sleep_save_msc[0], MSC0);
__raw_writel(sleep_save_msc[1], MSC1);
__raw_writel(sleep_save_msc[2], MSC2);
return 0;
}
@ -498,7 +499,12 @@ static struct map_desc cmx2xx_io_desc[] __initdata = {
static void __init cmx2xx_map_io(void)
{
pxa_map_io();
if (cpu_is_pxa25x())
pxa25x_map_io();
if (cpu_is_pxa27x())
pxa27x_map_io();
iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc));
it8152_base_address = CMX2XX_IT8152_VIRT;
@ -506,7 +512,11 @@ static void __init cmx2xx_map_io(void)
#else
static void __init cmx2xx_map_io(void)
{
pxa_map_io();
if (cpu_is_pxa25x())
pxa25x_map_io();
if (cpu_is_pxa27x())
pxa27x_map_io();
}
#endif

2
arch/arm/mach-pxa/cm-x300.c
View File

@ -857,7 +857,7 @@ static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags,
MACHINE_START(CM_X300, "CM-X300 module")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
.timer = &pxa_timer,
.init_machine = cm_x300_init,

96
arch/arm/mach-pxa/colibri-pxa270-evalboard.c → arch/arm/mach-pxa/colibri-evalboard.c
View File

@ -1,7 +1,7 @@
/*
* linux/arch/arm/mach-pxa/colibri-pxa270-evalboard.c
* linux/arch/arm/mach-pxa/colibri-evalboard.c
*
* Support for Toradex PXA270 based Colibri Evaluation Carrier Board
* Support for Toradex Colibri Evaluation Carrier Board
* Daniel Mack <daniel@caiaq.de>
* Marek Vasut <marek.vasut@gmail.com>
*
@ -19,6 +19,7 @@
#include <asm/mach-types.h>
#include <mach/hardware.h>
#include <asm/mach/arch.h>
#include <linux/i2c.h>
#include <mach/pxa27x.h>
#include <mach/colibri.h>
@ -26,86 +27,95 @@
#include <mach/ohci.h>
#include <mach/pxa27x-udc.h>
#include <plat/i2c.h>
#include "generic.h"
#include "devices.h"
/******************************************************************************
* Pin configuration
******************************************************************************/
static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = {
/* MMC */
GPIO32_MMC_CLK,
GPIO92_MMC_DAT_0,
GPIO109_MMC_DAT_1,
GPIO110_MMC_DAT_2,
GPIO111_MMC_DAT_3,
GPIO112_MMC_CMD,
GPIO0_GPIO, /* SD detect */
/* FFUART */
GPIO39_FFUART_TXD,
GPIO34_FFUART_RXD,
/* UHC */
GPIO88_USBH1_PWR,
GPIO89_USBH1_PEN,
GPIO119_USBH2_PWR,
GPIO120_USBH2_PEN,
};
/******************************************************************************
* SD/MMC card controller
******************************************************************************/
#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
static struct pxamci_platform_data colibri_pxa270_mci_platform_data = {
static struct pxamci_platform_data colibri_mci_platform_data = {
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
.gpio_power = -1,
.gpio_card_detect = GPIO0_COLIBRI_PXA270_SD_DETECT,
.gpio_card_ro = -1,
.detect_delay_ms = 200,
};
static void __init colibri_pxa270_mmc_init(void)
static void __init colibri_mmc_init(void)
{
pxa_set_mci_info(&colibri_pxa270_mci_platform_data);
if (machine_is_colibri()) /* PXA270 Colibri */
colibri_mci_platform_data.gpio_card_detect =
GPIO0_COLIBRI_PXA270_SD_DETECT;
if (machine_is_colibri300()) /* PXA300 Colibri */
colibri_mci_platform_data.gpio_card_detect =
GPIO39_COLIBRI_PXA300_SD_DETECT;
else /* PXA320 Colibri */
colibri_mci_platform_data.gpio_card_detect =
GPIO28_COLIBRI_PXA320_SD_DETECT;
pxa_set_mci_info(&colibri_mci_platform_data);
}
#else
static inline void colibri_pxa270_mmc_init(void) {}
static inline void colibri_mmc_init(void) {}
#endif
/******************************************************************************
* USB Host
******************************************************************************/
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
static int colibri_pxa270_ohci_init(struct device *dev)
static int colibri_ohci_init(struct device *dev)
{
UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
return 0;
}
static struct pxaohci_platform_data colibri_pxa270_ohci_info = {
static struct pxaohci_platform_data colibri_ohci_info = {
.port_mode = PMM_PERPORT_MODE,
.flags = ENABLE_PORT1 | ENABLE_PORT2 |
.flags = ENABLE_PORT1 |
POWER_CONTROL_LOW | POWER_SENSE_LOW,
.init = colibri_pxa270_ohci_init,
.init = colibri_ohci_init,
};
static void __init colibri_pxa270_uhc_init(void)
static void __init colibri_uhc_init(void)
{
pxa_set_ohci_info(&colibri_pxa270_ohci_info);
/* Colibri PXA270 has two usb ports, TBA for 320 */
if (machine_is_colibri())
colibri_ohci_info.flags |= ENABLE_PORT2;
pxa_set_ohci_info(&colibri_ohci_info);
}
#else
static inline void colibri_pxa270_uhc_init(void) {}
static inline void colibri_uhc_init(void) {}
#endif
void __init colibri_pxa270_evalboard_init(void)
/******************************************************************************
* I2C RTC
******************************************************************************/
#if defined(CONFIG_RTC_DRV_DS1307) || defined(CONFIG_RTC_DRV_DS1307_MODULE)
static struct i2c_board_info __initdata colibri_i2c_devs[] = {
{
I2C_BOARD_INFO("m41t00", 0x68),
},
};
static void __init colibri_rtc_init(void)
{
pxa_set_i2c_info(NULL);
i2c_register_board_info(0, ARRAY_AND_SIZE(colibri_i2c_devs));
}
#else
static inline void colibri_rtc_init(void) {}
#endif
void __init colibri_evalboard_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_evalboard_pin_config));
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
pxa_set_stuart_info(NULL);
colibri_pxa270_mmc_init();
colibri_pxa270_uhc_init();
colibri_mmc_init();
colibri_uhc_init();
colibri_rtc_init();
}

47
arch/arm/mach-pxa/colibri-pxa270-income.c
View File

@ -45,52 +45,6 @@
#define GPIO55_INCOME_LED_B (55)
#define GPIO113_INCOME_TS_IRQ (113)
/******************************************************************************
* Pin configuration
******************************************************************************/
static mfp_cfg_t income_pin_config[] __initdata = {
/* MMC */
GPIO32_MMC_CLK,
GPIO92_MMC_DAT_0,
GPIO109_MMC_DAT_1,
GPIO110_MMC_DAT_2,
GPIO111_MMC_DAT_3,
GPIO112_MMC_CMD,
GPIO0_GPIO, /* SD detect */
GPIO1_GPIO, /* SD read-only */
/* FFUART */
GPIO39_FFUART_TXD,
GPIO34_FFUART_RXD,
/* BFUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO45_BTUART_RTS,
/* STUART */
GPIO46_STUART_RXD,
GPIO47_STUART_TXD,
/* UHC */
GPIO88_USBH1_PWR,
GPIO89_USBH1_PEN,
/* LCD */
GPIOxx_LCD_TFT_16BPP,
/* PWM */
GPIO16_PWM0_OUT,
/* I2C */
GPIO117_I2C_SCL,
GPIO118_I2C_SDA,
/* LED */
GPIO54_GPIO, /* LED A */
GPIO55_GPIO, /* LED B */
};
/******************************************************************************
* SD/MMC card controller
******************************************************************************/
@ -257,7 +211,6 @@ static inline void income_pwm_init(void) {}
void __init colibri_pxa270_income_boardinit(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(income_pin_config));
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
pxa_set_stuart_info(NULL);

108
arch/arm/mach-pxa/colibri-pxa270.c
View File

@ -32,6 +32,103 @@
#include "devices.h"
#include "generic.h"
/******************************************************************************
* Evaluation board MFP
******************************************************************************/
#ifdef CONFIG_MACH_COLIBRI_EVALBOARD
static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = {
/* MMC */
GPIO32_MMC_CLK,
GPIO92_MMC_DAT_0,
GPIO109_MMC_DAT_1,
GPIO110_MMC_DAT_2,
GPIO111_MMC_DAT_3,
GPIO112_MMC_CMD,
GPIO0_GPIO, /* SD detect */
/* FFUART */
GPIO39_FFUART_TXD,
GPIO34_FFUART_RXD,
/* UHC */
GPIO88_USBH1_PWR,
GPIO89_USBH1_PEN,
GPIO119_USBH2_PWR,
GPIO120_USBH2_PEN,
/* PCMCIA */
GPIO85_nPCE_1,
GPIO54_nPCE_2,
GPIO55_nPREG,
GPIO50_nPIOR,
GPIO51_nPIOW,
GPIO49_nPWE,
GPIO48_nPOE,
GPIO57_nIOIS16,
GPIO56_nPWAIT,
GPIO104_PSKTSEL,
GPIO53_GPIO, /* RESET */
GPIO83_GPIO, /* BVD1 */
GPIO82_GPIO, /* BVD2 */
GPIO1_GPIO, /* READY */
GPIO84_GPIO, /* DETECT */
GPIO107_GPIO, /* PPEN */
/* I2C */
GPIO117_I2C_SCL,
GPIO118_I2C_SDA,
};
#else
static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = {};
#endif
#ifdef CONFIG_MACH_COLIBRI_PXA270_INCOME
static mfp_cfg_t income_pin_config[] __initdata = {
/* MMC */
GPIO32_MMC_CLK,
GPIO92_MMC_DAT_0,
GPIO109_MMC_DAT_1,
GPIO110_MMC_DAT_2,
GPIO111_MMC_DAT_3,
GPIO112_MMC_CMD,
GPIO0_GPIO, /* SD detect */
GPIO1_GPIO, /* SD read-only */
/* FFUART */
GPIO39_FFUART_TXD,
GPIO34_FFUART_RXD,
/* BFUART */
GPIO42_BTUART_RXD,
GPIO43_BTUART_TXD,
GPIO45_BTUART_RTS,
/* STUART */
GPIO46_STUART_RXD,
GPIO47_STUART_TXD,
/* UHC */
GPIO88_USBH1_PWR,
GPIO89_USBH1_PEN,
/* LCD */
GPIOxx_LCD_TFT_16BPP,
/* PWM */
GPIO16_PWM0_OUT,
/* I2C */
GPIO117_I2C_SCL,
GPIO118_I2C_SDA,
/* LED */
GPIO54_GPIO, /* LED A */
GPIO55_GPIO, /* LED B */
};
#else
static mfp_cfg_t income_pin_config[] __initdata = {};
#endif
/******************************************************************************
* Pin configuration
******************************************************************************/
@ -184,10 +281,13 @@ static void __init colibri_pxa270_init(void)
colibri_pxa270_tsc_init();
switch (colibri_pxa270_baseboard) {
case COLIBRI_PXA270_EVALBOARD:
colibri_pxa270_evalboard_init();
case COLIBRI_EVALBOARD:
pxa2xx_mfp_config(ARRAY_AND_SIZE(
colibri_pxa270_evalboard_pin_config));
colibri_evalboard_init();
break;
case COLIBRI_PXA270_INCOME:
pxa2xx_mfp_config(ARRAY_AND_SIZE(income_pin_config));
colibri_pxa270_income_boardinit();
break;
default:
@ -209,7 +309,7 @@ static void __init colibri_pxa270_income_init(void)
MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
.boot_params = COLIBRI_SDRAM_BASE + 0x100,
.init_machine = colibri_pxa270_init,
.map_io = pxa_map_io,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
MACHINE_END
@ -217,7 +317,7 @@ MACHINE_END
MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC")
.boot_params = 0xa0000100,
.init_machine = colibri_pxa270_income_init,
.map_io = pxa_map_io,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
MACHINE_END

73
arch/arm/mach-pxa/colibri-pxa300.c
View File

@ -31,9 +31,38 @@
#include "generic.h"
#include "devices.h"
#ifdef CONFIG_MACH_COLIBRI_EVALBOARD
static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = {
/* MMC */
GPIO7_MMC1_CLK,
GPIO14_MMC1_CMD,
GPIO3_MMC1_DAT0,
GPIO4_MMC1_DAT1,
GPIO5_MMC1_DAT2,
GPIO6_MMC1_DAT3,
GPIO39_GPIO, /* SD detect */
/* UHC */
GPIO0_2_USBH_PEN,
GPIO1_2_USBH_PWR,
GPIO77_USB_P3_1,
GPIO78_USB_P3_2,
GPIO79_USB_P3_3,
GPIO80_USB_P3_4,
GPIO81_USB_P3_5,
GPIO82_USB_P3_6,
/* I2C */
GPIO21_I2C_SCL,
GPIO22_I2C_SDA,
};
#else
static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = {};
#endif
#if defined(CONFIG_AX88796)
#define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO26_GPIO)
/*
* Asix AX88796 Ethernet
*/
@ -80,35 +109,6 @@ static void __init colibri_pxa300_init_eth(void)
static inline void __init colibri_pxa300_init_eth(void) {}
#endif /* CONFIG_AX88796 */
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
static mfp_cfg_t colibri_pxa300_usb_pin_config[] __initdata = {
GPIO0_2_USBH_PEN,
GPIO1_2_USBH_PWR,
};
static struct pxaohci_platform_data colibri_pxa300_ohci_info = {
.port_mode = PMM_GLOBAL_MODE,
.flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
};
void __init colibri_pxa300_init_ohci(void)
{
pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_usb_pin_config));
pxa_set_ohci_info(&colibri_pxa300_ohci_info);
}
#else
static inline void colibri_pxa300_init_ohci(void) {}
#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
static mfp_cfg_t colibri_pxa300_mmc_pin_config[] __initdata = {
GPIO7_MMC1_CLK,
GPIO14_MMC1_CMD,
GPIO3_MMC1_DAT0,
GPIO4_MMC1_DAT1,
GPIO5_MMC1_DAT2,
GPIO6_MMC1_DAT3,
};
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static mfp_cfg_t colibri_pxa300_lcd_pin_config[] __initdata = {
GPIO54_LCD_LDD_0,
@ -171,24 +171,21 @@ static inline void colibri_pxa310_init_ac97(void) {}
void __init colibri_pxa300_init(void)
{
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
pxa_set_stuart_info(NULL);
colibri_pxa300_init_eth();
colibri_pxa300_init_ohci();
colibri_pxa3xx_init_nand();
colibri_pxa300_init_lcd();
colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO39_GPIO));
colibri_pxa310_init_ac97();
colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa300_mmc_pin_config),
mfp_to_gpio(MFP_PIN_GPIO13));
/* Evalboard init */
pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_evalboard_pin_config));
colibri_evalboard_init();
}
MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
.boot_params = COLIBRI_SDRAM_BASE + 0x100,
.init_machine = colibri_pxa300_init,
.map_io = pxa_map_io,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
.timer = &pxa_timer,
MACHINE_END

139
arch/arm/mach-pxa/colibri-pxa320.c
View File

@ -35,9 +35,72 @@
#include "generic.h"
#include "devices.h"
#ifdef CONFIG_MACH_COLIBRI_EVALBOARD
static mfp_cfg_t colibri_pxa320_evalboard_pin_config[] __initdata = {
/* MMC */
GPIO22_MMC1_CLK,
GPIO23_MMC1_CMD,
GPIO18_MMC1_DAT0,
GPIO19_MMC1_DAT1,
GPIO20_MMC1_DAT2,
GPIO21_MMC1_DAT3,
GPIO28_GPIO, /* SD detect */
/* UART 1 configuration (may be set by bootloader) */
GPIO99_UART1_CTS,
GPIO104_UART1_RTS,
GPIO97_UART1_RXD,
GPIO98_UART1_TXD,
GPIO101_UART1_DTR,
GPIO103_UART1_DSR,
GPIO100_UART1_DCD,
GPIO102_UART1_RI,
/* UART 2 configuration */
GPIO109_UART2_CTS,
GPIO112_UART2_RTS,
GPIO110_UART2_RXD,
GPIO111_UART2_TXD,
/* UART 3 configuration */
GPIO30_UART3_RXD,
GPIO31_UART3_TXD,
/* UHC */
GPIO2_2_USBH_PEN,
GPIO3_2_USBH_PWR,
/* I2C */
GPIO32_I2C_SCL,
GPIO33_I2C_SDA,
/* PCMCIA */
MFP_CFG(GPIO59, AF7), /* PRST ; AF7 to tristate */
MFP_CFG(GPIO61, AF7), /* PCE1 ; AF7 to tristate */
MFP_CFG(GPIO60, AF7), /* PCE2 ; AF7 to tristate */
MFP_CFG(GPIO62, AF7), /* PCD ; AF7 to tristate */
MFP_CFG(GPIO56, AF7), /* PSKTSEL ; AF7 to tristate */
GPIO27_GPIO, /* RDnWR ; input/tristate */
GPIO50_GPIO, /* PREG ; input/tristate */
GPIO2_RDY,
GPIO5_NPIOR,
GPIO6_NPIOW,
GPIO7_NPIOS16,
GPIO8_NPWAIT,
GPIO29_GPIO, /* PRDY (READY GPIO) */
GPIO57_GPIO, /* PPEN (POWER GPIO) */
GPIO81_GPIO, /* PCD (DETECT GPIO) */
GPIO77_GPIO, /* PRST (RESET GPIO) */
GPIO53_GPIO, /* PBVD1 */
GPIO79_GPIO, /* PBVD2 */
GPIO54_GPIO, /* POE */
};
#else
static mfp_cfg_t colibri_pxa320_evalboard_pin_config[] __initdata = {};
#endif
#if defined(CONFIG_AX88796)
#define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO36_GPIO)
/*
* Asix AX88796 Ethernet
*/
@ -84,26 +147,6 @@ static void __init colibri_pxa320_init_eth(void)
static inline void __init colibri_pxa320_init_eth(void) {}
#endif /* CONFIG_AX88796 */
#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
static mfp_cfg_t colibri_pxa320_usb_pin_config[] __initdata = {
GPIO2_2_USBH_PEN,
GPIO3_2_USBH_PWR,
};
static struct pxaohci_platform_data colibri_pxa320_ohci_info = {
.port_mode = PMM_GLOBAL_MODE,
.flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
};
void __init colibri_pxa320_init_ohci(void)
{
pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_usb_pin_config));
pxa_set_ohci_info(&colibri_pxa320_ohci_info);
}
#else
static inline void colibri_pxa320_init_ohci(void) {}
#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE)
static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = {
.gpio_vbus = mfp_to_gpio(MFP_PIN_GPIO96),
@ -140,15 +183,6 @@ static void __init colibri_pxa320_init_udc(void)
static inline void colibri_pxa320_init_udc(void) {}
#endif
static mfp_cfg_t colibri_pxa320_mmc_pin_config[] __initdata = {
GPIO22_MMC1_CLK,
GPIO23_MMC1_CMD,
GPIO18_MMC1_DAT0,
GPIO19_MMC1_DAT1,
GPIO20_MMC1_DAT2,
GPIO21_MMC1_DAT3
};
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static mfp_cfg_t colibri_pxa320_lcd_pin_config[] __initdata = {
GPIO6_2_LCD_LDD_0,
@ -205,59 +239,24 @@ static inline void __init colibri_pxa320_init_ac97(void)
static inline void colibri_pxa320_init_ac97(void) {}
#endif
/*
* The following configuration is verified to work with the Toradex Orchid
* carrier board
*/
static mfp_cfg_t colibri_pxa320_uart_pin_config[] __initdata = {
/* UART 1 configuration (may be set by bootloader) */
GPIO99_UART1_CTS,
GPIO104_UART1_RTS,
GPIO97_UART1_RXD,
GPIO98_UART1_TXD,
GPIO101_UART1_DTR,
GPIO103_UART1_DSR,
GPIO100_UART1_DCD,
GPIO102_UART1_RI,
/* UART 2 configuration */
GPIO109_UART2_CTS,
GPIO112_UART2_RTS,
GPIO110_UART2_RXD,
GPIO111_UART2_TXD,
/* UART 3 configuration */
GPIO30_UART3_RXD,
GPIO31_UART3_TXD,
};
static void __init colibri_pxa320_init_uart(void)
{
pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_uart_pin_config));
}
void __init colibri_pxa320_init(void)
{
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
pxa_set_stuart_info(NULL);
colibri_pxa320_init_eth();
colibri_pxa320_init_ohci();
colibri_pxa3xx_init_nand();
colibri_pxa320_init_lcd();
colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO49_GPIO));
colibri_pxa320_init_ac97();
colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config),
mfp_to_gpio(MFP_PIN_GPIO28));
colibri_pxa320_init_uart();
colibri_pxa320_init_udc();
/* Evalboard init */
pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_evalboard_pin_config));
colibri_evalboard_init();
}
MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
.boot_params = COLIBRI_SDRAM_BASE + 0x100,
.init_machine = colibri_pxa320_init,
.map_io = pxa_map_io,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
.timer = &pxa_timer,
MACHINE_END

49
arch/arm/mach-pxa/colibri-pxa3xx.c
View File

@ -64,55 +64,6 @@ void __init colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data)
}
#endif
#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
static int mmc_detect_pin;
static int colibri_pxa3xx_mci_init(struct device *dev,
irq_handler_t colibri_mmc_detect_int,
void *data)
{
int ret;
ret = gpio_request(mmc_detect_pin, "mmc card detect");
if (ret)
return ret;
gpio_direction_input(mmc_detect_pin);
ret = request_irq(gpio_to_irq(mmc_detect_pin), colibri_mmc_detect_int,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC card detect", data);
if (ret) {
gpio_free(mmc_detect_pin);
return ret;
}
return 0;
}
static void colibri_pxa3xx_mci_exit(struct device *dev, void *data)
{
free_irq(mmc_detect_pin, data);
gpio_free(gpio_to_irq(mmc_detect_pin));
}
static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = {
.detect_delay_ms = 200,
.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
.init = colibri_pxa3xx_mci_init,
.exit = colibri_pxa3xx_mci_exit,
.gpio_card_detect = -1,
.gpio_card_ro = -1,
.gpio_power = -1,
};
void __init colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin)
{
pxa3xx_mfp_config(pins, len);
mmc_detect_pin = detect_pin;
pxa_set_mci_info(&colibri_pxa3xx_mci_platform_data);
}
#endif /* CONFIG_MMC_PXA || CONFIG_MMC_PXA_MODULE */
#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
static int lcd_bl_pin;

6
arch/arm/mach-pxa/corgi.c
View File

@ -721,7 +721,7 @@ static void __init fixup_corgi(struct machine_desc *desc,
#ifdef CONFIG_MACH_CORGI
MACHINE_START(CORGI, "SHARP Corgi")
.fixup = fixup_corgi,
.map_io = pxa_map_io,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
.init_machine = corgi_init,
.timer = &pxa_timer,
@ -731,7 +731,7 @@ MACHINE_END
#ifdef CONFIG_MACH_SHEPHERD
MACHINE_START(SHEPHERD, "SHARP Shepherd")
.fixup = fixup_corgi,
.map_io = pxa_map_io,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
.init_machine = corgi_init,
.timer = &pxa_timer,
@ -741,7 +741,7 @@ MACHINE_END
#ifdef CONFIG_MACH_HUSKY
MACHINE_START(HUSKY, "SHARP Husky")
.fixup = fixup_corgi,
.map_io = pxa_map_io,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
.init_machine = corgi_init,
.timer = &pxa_timer,

10
arch/arm/mach-pxa/cpufreq-pxa2xx.c
View File

@ -38,8 +38,10 @@
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/regulator/consumer.h>
#include <linux/io.h>
#include <mach/pxa2xx-regs.h>
#include <mach/smemc.h>
#ifdef DEBUG
static unsigned int freq_debug;
@ -242,7 +244,7 @@ static void pxa27x_guess_max_freq(void)
static void init_sdram_rows(void)
{
uint32_t mdcnfg = MDCNFG;
uint32_t mdcnfg = __raw_readl(MDCNFG);
unsigned int drac2 = 0, drac0 = 0;
if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
@ -331,8 +333,8 @@ static int pxa_set_target(struct cpufreq_policy *policy,
* we need to preset the smaller DRI before the change. If we're
* speeding up we need to set the larger DRI value after the change.
*/
preset_mdrefr = postset_mdrefr = MDREFR;
if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR);
if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
preset_mdrefr |= mdrefr_dri(new_freq_mem);
}
@ -370,7 +372,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
3: nop \n\
"
: "=&r" (unused)
: "r" (&MDREFR), "r" (cclkcfg),
: "r" (MDREFR), "r" (cclkcfg),
"r" (preset_mdrefr), "r" (postset_mdrefr)
: "r4", "r5");
local_irq_restore(flags);

9
arch/arm/mach-pxa/csb726.c
View File

@ -27,6 +27,7 @@
#include <mach/ohci.h>
#include <mach/pxa2xx-regs.h>
#include <mach/audio.h>
#include <mach/smemc.h>
#include "generic.h"
#include "devices.h"
@ -255,9 +256,9 @@ static struct platform_device *devices[] __initdata = {
static void __init csb726_init(void)
{
pxa2xx_mfp_config(ARRAY_AND_SIZE(csb726_pin_config));
/* MSC1 = 0x7ffc3ffc; *//* LAN9215/EXP_CS */
/* MSC2 = 0x06697ff4; *//* none/SM501 */
MSC2 = (MSC2 & ~0xffff) | 0x7ff4; /* SM501 */
/* __raw_writel(0x7ffc3ffc, MSC1); *//* LAN9215/EXP_CS */
/* __raw_writel(0x06697ff4, MSC2); *//* none/SM501 */
__raw_writel((__raw_readl(MSC2) & ~0xffff) | 0x7ff4, MSC2); /* SM501 */
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
@ -273,7 +274,7 @@ static void __init csb726_init(void)
MACHINE_START(CSB726, "Cogent CSB726")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
.init_machine = csb726_init,
.timer = &pxa_timer,

251
arch/arm/mach-pxa/devices.c
View File

@ -342,27 +342,6 @@ struct platform_device pxa27x_device_i2c_power = {
};
#endif
#ifdef CONFIG_PXA3xx
static struct resource pxa3xx_resources_i2c_power[] = {
{
.start = 0x40f500c0,
.end = 0x40f500d3,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PWRI2C,
.end = IRQ_PWRI2C,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device pxa3xx_device_i2c_power = {
.name = "pxa3xx-pwri2c",
.id = 1,
.resource = pxa3xx_resources_i2c_power,
.num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
};
#endif
static struct resource pxai2s_resources[] = {
{
.start = 0x40400000,
@ -633,30 +612,35 @@ struct platform_device pxa25x_device_assp = {
#endif /* CONFIG_PXA25x */
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
static struct resource pxa27x_resource_keypad[] = {
static struct resource pxa27x_resource_camera[] = {
[0] = {
.start = 0x41500000,
.end = 0x4150004c,
.start = 0x50000000,
.end = 0x50000fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_KEYPAD,
.end = IRQ_KEYPAD,
.start = IRQ_CAMERA,
.end = IRQ_CAMERA,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device pxa27x_device_keypad = {
.name = "pxa27x-keypad",
.id = -1,
.resource = pxa27x_resource_keypad,
.num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
static struct platform_device pxa27x_device_camera = {
.name = "pxa27x-camera",
.id = 0, /* This is used to put cameras on this interface */
.dev = {
.dma_mask = &pxa27x_dma_mask_camera,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(pxa27x_resource_camera),
.resource = pxa27x_resource_camera,
};
void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
{
pxa_register_device(&pxa27x_device_keypad, info);
pxa_register_device(&pxa27x_device_camera, info);
}
static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
@ -689,6 +673,33 @@ void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
{
pxa_register_device(&pxa27x_device_ohci, info);
}
#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
static struct resource pxa27x_resource_keypad[] = {
[0] = {
.start = 0x41500000,
.end = 0x4150004c,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_KEYPAD,
.end = IRQ_KEYPAD,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device pxa27x_device_keypad = {
.name = "pxa27x-keypad",
.id = -1,
.resource = pxa27x_resource_keypad,
.num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
};
void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
{
pxa_register_device(&pxa27x_device_keypad, info);
}
static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
@ -833,79 +844,9 @@ struct platform_device pxa27x_device_pwm1 = {
.resource = pxa27x_resource_pwm1,
.num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
};
static struct resource pxa27x_resource_camera[] = {
[0] = {
.start = 0x50000000,
.end = 0x50000fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_CAMERA,
.end = IRQ_CAMERA,
.flags = IORESOURCE_IRQ,
},
};
static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
static struct platform_device pxa27x_device_camera = {
.name = "pxa27x-camera",
.id = 0, /* This is used to put cameras on this interface */
.dev = {
.dma_mask = &pxa27x_dma_mask_camera,
.coherent_dma_mask = 0xffffffff,
},
.num_resources = ARRAY_SIZE(pxa27x_resource_camera),
.resource = pxa27x_resource_camera,
};
void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
{
pxa_register_device(&pxa27x_device_camera, info);
}
#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
#endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/
#ifdef CONFIG_PXA3xx
static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa3xx_resource_ssp4[] = {
[0] = {
.start = 0x41a00000,
.end = 0x41a0003f,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_SSP4,
.end = IRQ_SSP4,
.flags = IORESOURCE_IRQ,
},
[2] = {
/* DRCMR for RX */
.start = 2,
.end = 2,
.flags = IORESOURCE_DMA,
},
[3] = {
/* DRCMR for TX */
.start = 3,
.end = 3,
.flags = IORESOURCE_DMA,
},
};
struct platform_device pxa3xx_device_ssp4 = {
/* PXA3xx SSP is basically equivalent to PXA27x */
.name = "pxa27x-ssp",
.id = 3,
.dev = {
.dma_mask = &pxa3xx_ssp4_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = pxa3xx_resource_ssp4,
.num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
};
static struct resource pxa3xx_resources_mci2[] = {
[0] = {
.start = 0x42000000,
@ -984,6 +925,54 @@ void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
pxa_register_device(&pxa3xx_device_mci3, info);
}
static struct resource pxa3xx_resources_gcu[] = {
{
.start = 0x54000000,
.end = 0x54000fff,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_GCU,
.end = IRQ_GCU,
.flags = IORESOURCE_IRQ,
},
};
static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
struct platform_device pxa3xx_device_gcu = {
.name = "pxa3xx-gcu",
.id = -1,
.num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
.resource = pxa3xx_resources_gcu,
.dev = {
.dma_mask = &pxa3xx_gcu_dmamask,
.coherent_dma_mask = 0xffffffff,
},
};
#endif /* CONFIG_PXA3xx */
#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
static struct resource pxa3xx_resources_i2c_power[] = {
{
.start = 0x40f500c0,
.end = 0x40f500d3,
.flags = IORESOURCE_MEM,
}, {
.start = IRQ_PWRI2C,
.end = IRQ_PWRI2C,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device pxa3xx_device_i2c_power = {
.name = "pxa3xx-pwri2c",
.id = 1,
.resource = pxa3xx_resources_i2c_power,
.num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
};
static struct resource pxa3xx_resources_nand[] = {
[0] = {
.start = 0x43100000,
@ -1027,33 +1016,45 @@ void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
pxa_register_device(&pxa3xx_device_nand, info);
}
static struct resource pxa3xx_resources_gcu[] = {
{
.start = 0x54000000,
.end = 0x54000fff,
static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
static struct resource pxa3xx_resource_ssp4[] = {
[0] = {
.start = 0x41a00000,
.end = 0x41a0003f,
.flags = IORESOURCE_MEM,
},
{
.start = IRQ_GCU,
.end = IRQ_GCU,
[1] = {
.start = IRQ_SSP4,
.end = IRQ_SSP4,
.flags = IORESOURCE_IRQ,
},
};
static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
struct platform_device pxa3xx_device_gcu = {
.name = "pxa3xx-gcu",
.id = -1,
.num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
.resource = pxa3xx_resources_gcu,
.dev = {
.dma_mask = &pxa3xx_gcu_dmamask,
.coherent_dma_mask = 0xffffffff,
[2] = {
/* DRCMR for RX */
.start = 2,
.end = 2,
.flags = IORESOURCE_DMA,
},
[3] = {
/* DRCMR for TX */
.start = 3,
.end = 3,
.flags = IORESOURCE_DMA,
},
};
#endif /* CONFIG_PXA3xx */
struct platform_device pxa3xx_device_ssp4 = {
/* PXA3xx SSP is basically equivalent to PXA27x */
.name = "pxa27x-ssp",
.id = 3,
.dev = {
.dma_mask = &pxa3xx_ssp4_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
.resource = pxa3xx_resource_ssp4,
.num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
};
#endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
/* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
* See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */

4
arch/arm/mach-pxa/em-x270.c
View File

@ -1300,7 +1300,7 @@ static void __init em_x270_init(void)
MACHINE_START(EM_X270, "Compulab EM-X270")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
.init_machine = em_x270_init,
@ -1308,7 +1308,7 @@ MACHINE_END
MACHINE_START(EXEDA, "Compulab eXeda")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
.init_machine = em_x270_init,

12
arch/arm/mach-pxa/eseries.c
View File

@ -181,7 +181,7 @@ static void __init e330_init(void)
MACHINE_START(E330, "Toshiba e330")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa25x_map_io,
.nr_irqs = ESERIES_NR_IRQS,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
@ -230,7 +230,7 @@ static void __init e350_init(void)
MACHINE_START(E350, "Toshiba e350")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa25x_map_io,
.nr_irqs = ESERIES_NR_IRQS,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
@ -352,7 +352,7 @@ static void __init e400_init(void)
MACHINE_START(E400, "Toshiba e400")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa25x_map_io,
.nr_irqs = ESERIES_NR_IRQS,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
@ -540,7 +540,7 @@ static void __init e740_init(void)
MACHINE_START(E740, "Toshiba e740")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa25x_map_io,
.nr_irqs = ESERIES_NR_IRQS,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
@ -731,7 +731,7 @@ static void __init e750_init(void)
MACHINE_START(E750, "Toshiba e750")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa25x_map_io,
.nr_irqs = ESERIES_NR_IRQS,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,
@ -926,7 +926,7 @@ static void __init e800_init(void)
MACHINE_START(E800, "Toshiba e800")
/* Maintainer: Ian Molton (spyro@f2s.com) */
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa25x_map_io,
.nr_irqs = ESERIES_NR_IRQS,
.init_irq = pxa25x_init_irq,
.fixup = eseries_fixup,

12
arch/arm/mach-pxa/ezx.c
View File

@ -798,7 +798,7 @@ static void __init a780_init(void)
MACHINE_START(EZX_A780, "Motorola EZX A780")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa27x_map_io,
.nr_irqs = EZX_NR_IRQS,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
@ -863,7 +863,7 @@ static void __init e680_init(void)
MACHINE_START(EZX_E680, "Motorola EZX E680")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa27x_map_io,
.nr_irqs = EZX_NR_IRQS,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
@ -928,7 +928,7 @@ static void __init a1200_init(void)
MACHINE_START(EZX_A1200, "Motorola EZX A1200")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa27x_map_io,
.nr_irqs = EZX_NR_IRQS,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
@ -1118,7 +1118,7 @@ static void __init a910_init(void)
MACHINE_START(EZX_A910, "Motorola EZX A910")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa27x_map_io,
.nr_irqs = EZX_NR_IRQS,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
@ -1183,7 +1183,7 @@ static void __init e6_init(void)
MACHINE_START(EZX_E6, "Motorola EZX E6")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa27x_map_io,
.nr_irqs = EZX_NR_IRQS,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,
@ -1222,7 +1222,7 @@ static void __init e2_init(void)
MACHINE_START(EZX_E2, "Motorola EZX E2")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa27x_map_io,
.nr_irqs = EZX_NR_IRQS,
.init_irq = pxa27x_init_irq,
.timer = &pxa_timer,

48
arch/arm/mach-pxa/generic.c
View File

@ -28,6 +28,8 @@
#include <mach/reset.h>
#include <mach/gpio.h>
#include <mach/smemc.h>
#include <mach/pxa3xx-regs.h>
#include "generic.h"
@ -35,9 +37,10 @@ void clear_reset_status(unsigned int mask)
{
if (cpu_is_pxa2xx())
pxa2xx_clear_reset_status(mask);
if (cpu_is_pxa3xx())
pxa3xx_clear_reset_status(mask);
else {
/* RESET_STATUS_* has a 1:1 mapping with ARSR */
ARSR = mask;
}
}
unsigned long get_clock_tick_rate(void)
@ -70,48 +73,18 @@ unsigned int get_clk_frequency_khz(int info)
}
EXPORT_SYMBOL(get_clk_frequency_khz);
/*
* Return the current memory clock frequency in units of 10kHz
*/
unsigned int get_memclk_frequency_10khz(void)
{
if (cpu_is_pxa25x())
return pxa25x_get_memclk_frequency_10khz();
else if (cpu_is_pxa27x())
return pxa27x_get_memclk_frequency_10khz();
return 0;
}
EXPORT_SYMBOL(get_memclk_frequency_10khz);
/*
* Intel PXA2xx internal register mapping.
*
* Note 1: not all PXA2xx variants implement all those addresses.
*
* Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
* and cache flush area.
* Note: virtual 0xfffe0000-0xffffffff is reserved for the vector table
* and cache flush area.
*/
static struct map_desc standard_io_desc[] __initdata = {
static struct map_desc common_io_desc[] __initdata = {
{ /* Devs */
.virtual = 0xf2000000,
.pfn = __phys_to_pfn(0x40000000),
.length = 0x02000000,
.type = MT_DEVICE
}, { /* Mem Ctl */
.virtual = 0xf6000000,
.pfn = __phys_to_pfn(0x48000000),
.length = 0x00200000,
.type = MT_DEVICE
}, { /* Camera */
.virtual = 0xfa000000,
.pfn = __phys_to_pfn(0x50000000),
.length = 0x00100000,
.type = MT_DEVICE
}, { /* IMem ctl */
.virtual = 0xfe000000,
.pfn = __phys_to_pfn(0x58000000),
.length = 0x00100000,
.type = MT_DEVICE
}, { /* UNCACHED_PHYS_0 */
.virtual = 0xff000000,
.pfn = __phys_to_pfn(0x00000000),
@ -122,6 +95,5 @@ static struct map_desc standard_io_desc[] __initdata = {
void __init pxa_map_io(void)
{
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
get_clk_frequency_khz(1);
iotable_init(ARRAY_AND_SIZE(common_io_desc));
}

11
arch/arm/mach-pxa/generic.h
View File

@ -20,7 +20,12 @@ extern void __init pxa26x_init_irq(void);
#endif
extern void __init pxa27x_init_irq(void);
extern void __init pxa3xx_init_irq(void);
extern void __init pxa95x_init_irq(void);
extern void __init pxa_map_io(void);
extern void __init pxa25x_map_io(void);
extern void __init pxa27x_map_io(void);
extern void __init pxa3xx_map_io(void);
extern unsigned int get_clk_frequency_khz(int info);
@ -32,18 +37,14 @@ extern unsigned int get_clk_frequency_khz(int info);
#ifdef CONFIG_PXA25x
extern unsigned pxa25x_get_clk_frequency_khz(int);
extern unsigned pxa25x_get_memclk_frequency_10khz(void);
#else
#define pxa25x_get_clk_frequency_khz(x) (0)
#define pxa25x_get_memclk_frequency_10khz() (0)
#endif
#ifdef CONFIG_PXA27x
extern unsigned pxa27x_get_clk_frequency_khz(int);
extern unsigned pxa27x_get_memclk_frequency_10khz(void);
#else
#define pxa27x_get_clk_frequency_khz(x) (0)
#define pxa27x_get_memclk_frequency_10khz() (0)
#endif
#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
@ -54,10 +55,8 @@ static inline void pxa2xx_clear_reset_status(unsigned int mask) {}
#ifdef CONFIG_PXA3xx
extern unsigned pxa3xx_get_clk_frequency_khz(int);
extern void pxa3xx_clear_reset_status(unsigned int);
#else
#define pxa3xx_get_clk_frequency_khz(x) (0)
static inline void pxa3xx_clear_reset_status(unsigned int mask) {}
#endif
extern struct sysdev_class pxa_irq_sysclass;

2
arch/arm/mach-pxa/gumstix.c
View File

@ -225,7 +225,7 @@ static void __init gumstix_init(void)
MACHINE_START(GUMSTIX, "Gumstix")
.boot_params = 0xa0000100, /* match u-boot bi_boot_params */
.map_io = pxa_map_io,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
.timer = &pxa_timer,
.init_machine = gumstix_init,

11
arch/arm/mach-pxa/h5000.c
View File

@ -32,6 +32,7 @@
#include <mach/pxa25x.h>
#include <mach/h5000.h>
#include <mach/udc.h>
#include <mach/smemc.h>
#include "generic.h"
@ -172,11 +173,11 @@ static unsigned long h5000_pin_config[] __initdata = {
static void fix_msc(void)
{
MSC0 = 0x129c24f2;
MSC1 = 0x7ff424fa;
MSC2 = 0x7ff47ff4;
__raw_writel(0x129c24f2, MSC0);
__raw_writel(0x7ff424fa, MSC1);
__raw_writel(0x7ff47ff4, MSC2);
MDREFR |= 0x02080000;
__raw_writel(__raw_readl(MDREFR) | 0x02080000, MDREFR);
}
/*
@ -202,7 +203,7 @@ static void __init h5000_init(void)
MACHINE_START(H5400, "HP iPAQ H5000")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
.timer = &pxa_timer,
.init_machine = h5000_init,

2
arch/arm/mach-pxa/himalaya.c
View File

@ -160,7 +160,7 @@ static void __init himalaya_init(void)
MACHINE_START(HIMALAYA, "HTC Himalaya")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
.init_machine = himalaya_init,
.timer = &pxa_timer,

2
arch/arm/mach-pxa/hx4700.c
View File

@ -871,7 +871,7 @@ static void __init hx4700_init(void)
MACHINE_START(H4700, "HP iPAQ HX4700")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa27x_map_io,
.nr_irqs = HX4700_NR_IRQS,
.init_irq = pxa27x_init_irq,
.init_machine = hx4700_init,

2
arch/arm/mach-pxa/icontrol.c
View File

@ -192,7 +192,7 @@ static void __init icontrol_init(void)
MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
.boot_params = 0xa0000100,
.map_io = pxa_map_io,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
.timer = &pxa_timer,
.init_machine = icontrol_init

2
arch/arm/mach-pxa/idp.c
View File

@ -187,7 +187,7 @@ static struct map_desc idp_io_desc[] __initdata = {
static void __init idp_map_io(void)
{
pxa_map_io();
pxa25x_map_io();
iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
}

48
arch/arm/mach-pxa/include/mach/addr-map.h Normal file
View File

@ -0,0 +1,48 @@
#ifndef __ASM_MACH_ADDR_MAP_H
#define __ASM_MACH_ADDR_MAP_H
/*
* Chip Selects
*/
#define PXA_CS0_PHYS 0x00000000
#define PXA_CS1_PHYS 0x04000000
#define PXA_CS2_PHYS 0x08000000
#define PXA_CS3_PHYS 0x0C000000
#define PXA_CS4_PHYS 0x10000000
#define PXA_CS5_PHYS 0x14000000
#define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
#define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
#define PXA3xx_CS2_PHYS 0x10000000
#define PXA3xx_CS3_PHYS 0x14000000
/*
* Peripheral Bus
*/
#define PERIPH_PHYS 0x40000000
#define PERIPH_VIRT 0xf2000000
#define PERIPH_SIZE 0x02000000
/*
* Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x)
*/
#define PXA2XX_SMEMC_PHYS 0x48000000
#define PXA3XX_SMEMC_PHYS 0x4a000000
#define SMEMC_VIRT 0xf6000000
#define SMEMC_SIZE 0x00100000
/*
* Dynamic Memory Controller (only on PXA3xx)
*/
#define DMEMC_PHYS 0x48100000
#define DMEMC_VIRT 0xf6100000
#define DMEMC_SIZE 0x00100000
/*
* Internal Memory Controller (PXA27x and later)
*/
#define IMEMC_PHYS 0x58000000
#define IMEMC_VIRT 0xfe000000
#define IMEMC_SIZE 0x00100000
#endif /* __ASM_MACH_ADDR_MAP_H */

6
arch/arm/mach-pxa/include/mach/balloon3.h
View File

@ -26,6 +26,8 @@ enum balloon3_features {
#define BALLOON3_FPGA_VIRT (0xf1000000) /* as per balloon2 */
#define BALLOON3_FPGA_LENGTH 0x01000000
#define BALLOON3_FPGA_SETnCLR (0x1000)
/* FPGA / CPLD registers for CF socket */
#define BALLOON3_CF_STATUS_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
#define BALLOON3_CF_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00008)
@ -35,7 +37,7 @@ enum balloon3_features {
#define BALLOON3_NAND_BASE (PXA_CS4_PHYS + 0x00e00000)
#define BALLOON3_NAND_IO_REG (BALLOON3_FPGA_VIRT + 0x00e00000)
#define BALLOON3_NAND_CONTROL2_REG (BALLOON3_FPGA_VIRT + 0x00e00010)
#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00010)
#define BALLOON3_NAND_STAT_REG (BALLOON3_FPGA_VIRT + 0x00e00014)
#define BALLOON3_NAND_CONTROL_REG (BALLOON3_FPGA_VIRT + 0x00e00014)
/* fpga/cpld interrupt control register */
@ -174,7 +176,7 @@ enum balloon3_features {
#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD)
#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 4)
#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 16)
extern int balloon3_has(enum balloon3_features feature);

14
arch/arm/mach-pxa/include/mach/colibri.h
View File

@ -9,14 +9,14 @@
*/
enum {
COLIBRI_PXA270_EVALBOARD = 0,
COLIBRI_EVALBOARD = 0,
COLIBRI_PXA270_INCOME,
};
#if defined(CONFIG_MACH_COLIBRI_PXA270_EVALBOARD)
extern void colibri_pxa270_evalboard_init(void);
#if defined(CONFIG_MACH_COLIBRI_EVALBOARD)
extern void colibri_evalboard_init(void);
#else
static inline void colibri_pxa270_evalboard_init(void) {}
static inline void colibri_evalboard_init(void) {}
#endif
#if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME)
@ -59,5 +59,11 @@ static inline void colibri_pxa3xx_init_nand(void) {}
#define GPIO0_COLIBRI_PXA270_SD_DETECT 0
#define GPIO113_COLIBRI_PXA270_TS_IRQ 113
/* GPIO definitions for Colibri PXA300/310 */
#define GPIO39_COLIBRI_PXA300_SD_DETECT 39
/* GPIO definitions for Colibri PXA320 */
#define GPIO28_COLIBRI_PXA320_SD_DETECT 28
#endif /* _COLIBRI_H_ */

47
arch/arm/mach-pxa/include/mach/hardware.h
View File

@ -13,6 +13,8 @@
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <mach/addr-map.h>
/*
* Workarounds for at least 2 errata so far require this.
* The mapping is set in mach-pxa/generic.c.
@ -193,14 +195,15 @@
#define __cpu_is_pxa935(id) (0)
#endif
#ifdef CONFIG_CPU_PXA950
#define __cpu_is_pxa950(id) \
({ \
#ifdef CONFIG_CPU_PXA955
#define __cpu_is_pxa955(id) \
({ \
unsigned int _id = (id) >> 4 & 0xfff; \
_id == 0x697; \
})
_id == 0x581 || _id == 0xc08 \
|| _id == 0xb76; \
})
#else
#define __cpu_is_pxa950(id) (0)
#define __cpu_is_pxa955(id) (0)
#endif
#define cpu_is_pxa210() \
@ -253,16 +256,15 @@
__cpu_is_pxa935(read_cpuid_id()); \
})
#define cpu_is_pxa950() \
#define cpu_is_pxa955() \
({ \
__cpu_is_pxa950(read_cpuid_id()); \
})
__cpu_is_pxa955(read_cpuid_id()); \
})
/*
* CPUID Core Generation Bit
* <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
* == 0x3 for pxa300/pxa310/pxa320
*/
#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
#define __cpu_is_pxa2xx(id) \
@ -277,8 +279,10 @@
#ifdef CONFIG_PXA3xx
#define __cpu_is_pxa3xx(id) \
({ \
unsigned int _id = (id) >> 13 & 0x7; \
_id == 0x3; \
__cpu_is_pxa300(id) \
|| __cpu_is_pxa310(id) \
|| __cpu_is_pxa320(id) \
|| __cpu_is_pxa93x(id); \
})
#else
#define __cpu_is_pxa3xx(id) (0)
@ -287,13 +291,22 @@
#if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
#define __cpu_is_pxa93x(id) \
({ \
unsigned int _id = (id) >> 4 & 0xfff; \
_id == 0x683 || _id == 0x693; \
__cpu_is_pxa930(id) \
|| __cpu_is_pxa935(id); \
})
#else
#define __cpu_is_pxa93x(id) (0)
#endif
#ifdef CONFIG_PXA95x
#define __cpu_is_pxa95x(id) \
({ \
__cpu_is_pxa955(id); \
})
#else
#define __cpu_is_pxa95x(id) (0)
#endif
#define cpu_is_pxa2xx() \
({ \
__cpu_is_pxa2xx(read_cpuid_id()); \
@ -308,6 +321,12 @@
({ \
__cpu_is_pxa93x(read_cpuid_id()); \
})
#define cpu_is_pxa95x() \
({ \
__cpu_is_pxa95x(read_cpuid_id()); \
})
/*
* return current memory and LCD clock frequency in units of 10kHz
*/

48
arch/arm/mach-pxa/include/mach/irqs.h
View File

@ -21,16 +21,14 @@
#define PXA_IRQ(x) (PXA_ISA_IRQ_NUM + (x))
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */
#define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */
#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI) */
#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI) */
#define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */
#define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */
#define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */
#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt */
#define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */
#define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */
#define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */
#endif
#define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */
#define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
#define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */
@ -38,7 +36,8 @@
#define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */
#define IRQ_USB PXA_IRQ(11) /* USB Service */
#define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */
#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt */
#define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt (PXA27x) */
#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */
#define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */
#define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */
#define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */
@ -47,6 +46,7 @@
#define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */
#define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */
#define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */
#define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */
#define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */
#define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */
#define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/
@ -60,19 +60,17 @@
#define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */
#define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */
#define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */
#endif
#ifdef CONFIG_PXA3xx
#define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request */
#define IRQ_CIR PXA_IRQ(34) /* Consumer IR */
#define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */
#define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */
#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */
#define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */
#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller */
#define IRQ_GCU PXA_IRQ(39) /* Graphics Controller (PXA3xx) */
#define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */
#define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */
#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball (PXA930) */
#define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */
#define IRQ_NAND PXA_IRQ(45) /* NAND Controller */
#define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */
@ -80,30 +78,14 @@
#define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */
#define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */
#define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */
#endif
#ifdef CONFIG_CPU_PXA935
#define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */
#define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */
#define IRQ_MMC3_PXA935 PXA_IRQ(72) /* MMC3 Controller (PXA935) */
#define IRQ_MMC4_PXA935 PXA_IRQ(73) /* MMC4 Controller (PXA935) */
#define IRQ_MMC5_PXA935 PXA_IRQ(74) /* MMC5 Controller (PXA935) */
#define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */
#define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */
#define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */
#define IRQ_PXA955_MMC3 PXA_IRQ(75) /* MMC3 Controller (PXA955) */
#define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */
#endif
#ifdef CONFIG_CPU_PXA930
#define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */
#define IRQ_ACIPC0 PXA_IRQ(5)
#define IRQ_ACIPC1 PXA_IRQ(40)
#define IRQ_ACIPC2 PXA_IRQ(19)
#define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball */
#endif
#ifdef CONFIG_CPU_PXA950
#define IRQ_GC500 PXA_IRQ(70) /* Graphics Controller (PXA950) */
#endif
#define PXA_GPIO_IRQ_BASE PXA_IRQ(96)
#define PXA_GPIO_IRQ_NUM (192)

66
arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
View File

@ -16,72 +16,6 @@
#include <mach/hardware.h>
/*
* PXA Chip selects
*/
#define PXA_CS0_PHYS 0x00000000
#define PXA_CS1_PHYS 0x04000000
#define PXA_CS2_PHYS 0x08000000
#define PXA_CS3_PHYS 0x0C000000
#define PXA_CS4_PHYS 0x10000000
#define PXA_CS5_PHYS 0x14000000
/*
* Memory controller
*/
#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
/*
* More handy macros for PCMCIA
*
* Arg is socket number
*/
#define MCMEM(s) __REG2(0x48000028, (s)<<2 ) /* Card interface Common Memory Space Socket s Timing */
#define MCATT(s) __REG2(0x48000030, (s)<<2 ) /* Card interface Attribute Space Socket s Timing Configuration */
#define MCIO(s) __REG2(0x48000038, (s)<<2 ) /* Card interface I/O Space Socket s Timing Configuration */
/* MECR register defines */
#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
/*
* Power Manager
*/

9
arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
View File

@ -15,15 +15,6 @@
#include <mach/hardware.h>
/*
* Static Chip Selects
*/
#define PXA300_CS0_PHYS (0x00000000) /* PXA300/PXA310 _only_ */
#define PXA300_CS1_PHYS (0x30000000) /* PXA300/PXA310 _only_ */
#define PXA3xx_CS2_PHYS (0x10000000)
#define PXA3xx_CS3_PHYS (0x14000000)
/*
* Oscillator Configuration Register (OSCC)
*/

4
arch/arm/mach-pxa/include/mach/regs-intc.h
View File

@ -27,8 +27,4 @@
#define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */
#define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */
#define IPR(x) __REG(0x40D0001C + (x < 32 ? (x << 2) \
: (x < 64 ? (0x94 + ((x - 32) << 2)) \
: (0x128 + ((x - 64) << 2)))))
#endif /* __ASM_MACH_REGS_INTC_H */

74
arch/arm/mach-pxa/include/mach/smemc.h Normal file
View File

@ -0,0 +1,74 @@
/*
* Static memory controller register definitions for PXA CPUs
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __SMEMC_REGS_H
#define __SMEMC_REGS_H
#define PXA2XX_SMEMC_BASE 0x48000000
#define PXA3XX_SMEMC_BASE 0x4a000000
#define SMEMC_VIRT 0xf6000000
#define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
#define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
#define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */
#define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */
#define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */
#define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
#define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
#define SXCNFG (SMEMC_VIRT + 0x1C) /* Synchronous Static Memory Control Register */
#define SXMRS (SMEMC_VIRT + 0x24) /* MRS value to be written to Synchronous Flash or SMROM */
#define MCMEM0 (SMEMC_VIRT + 0x28) /* Card interface Common Memory Space Socket 0 Timing */
#define MCMEM1 (SMEMC_VIRT + 0x2C) /* Card interface Common Memory Space Socket 1 Timing */
#define MCATT0 (SMEMC_VIRT + 0x30) /* Card interface Attribute Space Socket 0 Timing Configuration */
#define MCATT1 (SMEMC_VIRT + 0x34) /* Card interface Attribute Space Socket 1 Timing Configuration */
#define MCIO0 (SMEMC_VIRT + 0x38) /* Card interface I/O Space Socket 0 Timing Configuration */
#define MCIO1 (SMEMC_VIRT + 0x3C) /* Card interface I/O Space Socket 1 Timing Configuration */
#define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */
#define BOOT_DEF (SMEMC_VIRT + 0x44) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
#define MEMCLKCFG (SMEMC_VIRT + 0x68) /* Clock Configuration */
#define CSADRCFG0 (SMEMC_VIRT + 0x80) /* Address Configuration Register for CS0 */
#define CSADRCFG1 (SMEMC_VIRT + 0x84) /* Address Configuration Register for CS1 */
#define CSADRCFG2 (SMEMC_VIRT + 0x88) /* Address Configuration Register for CS2 */
#define CSADRCFG3 (SMEMC_VIRT + 0x8C) /* Address Configuration Register for CS3 */
/*
* More handy macros for PCMCIA
*
* Arg is socket number
*/
#define MCMEM(s) (SMEMC_VIRT + 0x28 + ((s)<<2)) /* Card interface Common Memory Space Socket s Timing */
#define MCATT(s) (SMEMC_VIRT + 0x30 + ((s)<<2)) /* Card interface Attribute Space Socket s Timing Configuration */
#define MCIO(s) (SMEMC_VIRT + 0x38 + ((s)<<2)) /* Card interface I/O Space Socket s Timing Configuration */
/* MECR register defines */
#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
#endif

129
arch/arm/mach-pxa/irq.c
View File

@ -16,20 +16,31 @@
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/sysdev.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <mach/irqs.h>
#include <mach/gpio.h>
#include <mach/regs-intc.h>
#include "generic.h"
#define MAX_INTERNAL_IRQS 128
#define IRQ_BASE (void __iomem *)io_p2v(0x40d00000)
#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
#define _ICMR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
#define _ICLR(n) (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
#define ICIP (0x000)
#define ICMR (0x004)
#define ICLR (0x008)
#define ICFR (0x00c)
#define ICPR (0x010)
#define ICCR (0x014)
#define ICHP (0x018)
#define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \
((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \
(0x144 + (((i) - 64) << 2)))
#define IPR_VALID (1 << 31)
#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
#define MAX_INTERNAL_IRQS 128
/*
* This is for peripheral IRQs internal to the PXA chip.
@ -37,14 +48,27 @@
static int pxa_internal_irq_nr;
static inline int cpu_has_ipr(void)
{
return !cpu_is_pxa25x();
}
static void pxa_mask_irq(unsigned int irq)
{
_ICMR(irq) &= ~(1 << IRQ_BIT(irq));
void __iomem *base = get_irq_chip_data(irq);
uint32_t icmr = __raw_readl(base + ICMR);
icmr &= ~(1 << IRQ_BIT(irq));
__raw_writel(icmr, base + ICMR);
}
static void pxa_unmask_irq(unsigned int irq)
{
_ICMR(irq) |= 1 << IRQ_BIT(irq);
void __iomem *base = get_irq_chip_data(irq);
uint32_t icmr = __raw_readl(base + ICMR);
icmr |= 1 << IRQ_BIT(irq);
__raw_writel(icmr, base + ICMR);
}
static struct irq_chip pxa_internal_irq_chip = {
@ -86,12 +110,16 @@ static void pxa_ack_low_gpio(unsigned int irq)
static void pxa_mask_low_gpio(unsigned int irq)
{
ICMR &= ~(1 << (irq - PXA_IRQ(0)));
struct irq_desc *desc = irq_to_desc(irq);
desc->chip->mask(irq);
}
static void pxa_unmask_low_gpio(unsigned int irq)
{
ICMR |= 1 << (irq - PXA_IRQ(0));
struct irq_desc *desc = irq_to_desc(irq);
desc->chip->unmask(irq);
}
static struct irq_chip pxa_low_gpio_chip = {
@ -120,33 +148,45 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)
pxa_low_gpio_chip.set_wake = fn;
}
static inline void __iomem *irq_base(int i)
{
static unsigned long phys_base[] = {
0x40d00000,
0x40d0009c,
0x40d00130,
};
return (void __iomem *)io_p2v(phys_base[i >> 5]);
}
void __init pxa_init_irq(int irq_nr, set_wake_t fn)
{
int irq, i;
int irq, i, n;
BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
pxa_internal_irq_nr = irq_nr;
for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) {
_ICMR(irq) = 0; /* disable all IRQs */
_ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
}
for (n = 0; n < irq_nr; n += 32) {
void __iomem *base = irq_base(n);
/* initialize interrupt priority */
if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
for (i = 0; i < irq_nr; i++)
IPR(i) = i | (1 << 31);
__raw_writel(0, base + ICMR); /* disable all IRQs */
__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
/* initialize interrupt priority */
if (cpu_has_ipr())
__raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
irq = PXA_IRQ(i);
set_irq_chip(irq, &pxa_internal_irq_chip);
set_irq_chip_data(irq, base);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
}
/* only unmasked interrupts kick us out of idle */
ICCR = 1;
for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
set_irq_chip(irq, &pxa_internal_irq_chip);
set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
__raw_writel(1, irq_base(0) + ICCR);
pxa_internal_irq_chip.set_wake = fn;
pxa_init_low_gpio_irq(fn);
@ -158,16 +198,18 @@ static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
{
int i, irq = PXA_IRQ(0);
int i;
for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
saved_icmr[i] = _ICMR(irq);
_ICMR(irq) = 0;
for (i = 0; i < pxa_internal_irq_nr; i += 32) {
void __iomem *base = irq_base(i);
saved_icmr[i] = __raw_readl(base + ICMR);
__raw_writel(0, base + ICMR);
}
if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
if (cpu_has_ipr()) {
for (i = 0; i < pxa_internal_irq_nr; i++)
saved_ipr[i] = IPR(i);
saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
}
return 0;
@ -175,19 +217,20 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
static int pxa_irq_resume(struct sys_device *dev)
{
int i, irq = PXA_IRQ(0);
int i;
if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
for (i = 0; i < pxa_internal_irq_nr; i += 32) {
void __iomem *base = irq_base(i);
__raw_writel(saved_icmr[i], base + ICMR);
__raw_writel(0, base + ICLR);
}
if (!cpu_is_pxa25x())
for (i = 0; i < pxa_internal_irq_nr; i++)
IPR(i) = saved_ipr[i];
}
__raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
_ICMR(irq) = saved_icmr[i];
_ICLR(irq) = 0;
}
ICCR = 1;
__raw_writel(1, IRQ_BASE + ICCR);
return 0;
}
#else

Some files were not shown because too many files have changed in this diff Show More