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drm/i915: fix pnv display core clock readout out

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We need the correct clock to accurately assess whether we need to
enable the double wide pipe mode or not.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Stéphane Marchesin <marcheu@chromium.org>
Cc: Stuart Abercrombie <sabercrombie@google.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2013-07-26 08:35:42 +02:00
parent de51f04f06
commit 257a7ffcfa
2 changed files with 34 additions and 1 deletions
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6
drivers/gpu/drm/i915/i915_reg.h
View File

@ -61,6 +61,12 @@
#define GC_LOW_FREQUENCY_ENABLE (1 << 7) #define GC_LOW_FREQUENCY_ENABLE (1 << 7)
#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
#define GC_DISPLAY_CLOCK_MASK (7 << 4) #define GC_DISPLAY_CLOCK_MASK (7 << 4)
#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)

29
drivers/gpu/drm/i915/intel_display.c
View File

@ -4163,6 +4163,30 @@ static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
return 200000; return 200000;
} }
static int pnv_get_display_clock_speed(struct drm_device *dev)
{
u16 gcfgc = 0;
pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
case GC_DISPLAY_CLOCK_267_MHZ_PNV:
return 267000;
case GC_DISPLAY_CLOCK_333_MHZ_PNV:
return 333000;
case GC_DISPLAY_CLOCK_444_MHZ_PNV:
return 444000;
case GC_DISPLAY_CLOCK_200_MHZ_PNV:
return 200000;
default:
DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
case GC_DISPLAY_CLOCK_133_MHZ_PNV:
return 133000;
case GC_DISPLAY_CLOCK_167_MHZ_PNV:
return 167000;
}
}
static int i915gm_get_display_clock_speed(struct drm_device *dev) static int i915gm_get_display_clock_speed(struct drm_device *dev)
{ {
u16 gcfgc = 0; u16 gcfgc = 0;
@ -9605,9 +9629,12 @@ static void intel_init_display(struct drm_device *dev)
else if (IS_I915G(dev)) else if (IS_I915G(dev))
dev_priv->display.get_display_clock_speed = dev_priv->display.get_display_clock_speed =
i915_get_display_clock_speed; i915_get_display_clock_speed;
else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) else if (IS_I945GM(dev) || IS_845G(dev))
dev_priv->display.get_display_clock_speed = dev_priv->display.get_display_clock_speed =
i9xx_misc_get_display_clock_speed; i9xx_misc_get_display_clock_speed;
else if (IS_PINEVIEW(dev))
dev_priv->display.get_display_clock_speed =
pnv_get_display_clock_speed;
else if (IS_I915GM(dev)) else if (IS_I915GM(dev))
dev_priv->display.get_display_clock_speed = dev_priv->display.get_display_clock_speed =
i915gm_get_display_clock_speed; i915gm_get_display_clock_speed;