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net: hns3: fix for vport->bw_limit overflow problem

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When setting vport->bw_limit to hdev->tm_info.pg_info[0].bw_limit
in hclge_tm_vport_tc_info_update, vport->bw_limit can be as big as
HCLGE_ETHER_MAX_RATE (100000), which can not fit into u16 (65535).

So this patch fixes it by using u32 for vport->bw_limit.

Fixes: 848440544b ("net: hns3: Add support of TX Scheduler & Shaper to HNS3 driver")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yunsheng Lin 2019-04-15 21:48:39 +08:00 committed by David S. Miller
parent 8a9a654b5b
commit 2566f10676
1 changed files with 1 additions and 1 deletions
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2
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
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@ -854,7 +854,7 @@ struct hclge_vport {
u16 alloc_rss_size;
u16 qs_offset;
u16 bw_limit; /* VSI BW Limit (0 = disabled) */
u32 bw_limit; /* VSI BW Limit (0 = disabled) */
u8 dwrr;
struct hclge_port_base_vlan_config port_base_vlan_cfg;