Merge branch 'for-4.21/dt-bindings' into for-4.21/arm64/dt

This commit is contained in:
Thierry Reding 2018-11-27 18:43:59 +01:00
commit 252babf3a1
4 changed files with 29 additions and 1 deletions

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@ -10,6 +10,8 @@ Properties:
and chosen using the ramcode board selector. If omitted, only one
set of tables can be present and said tables will be used
irrespective of ram-code configuration.
- interrupts : Should contain EMC General interrupt.
- clocks : Should contain EMC clock.
Child device nodes describe the memory settings for different configurations and clock rates.
@ -20,6 +22,8 @@ Example:
#size-cells = < 0 >;
compatible = "nvidia,tegra20-emc";
reg = <0x7000f4000 0x200>;
interrupts = <0 78 0x04>;
clocks = <&tegra_car TEGRA20_CLK_EMC>;
}

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@ -15,7 +15,8 @@ Required properties:
- compatible:
Array of strings.
One of:
- "nvidia,tegra186-bpmp-thermal".
- "nvidia,tegra186-bpmp-thermal"
- "nvidia,tegra194-bpmp-thermal"
- #thermal-sensor-cells: Cell for sensor index.
Single-cell integer.
Must be <1>.

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@ -59,6 +59,14 @@ For Tegra210:
- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
- power-domains: A list of PM domain specifiers that reference each power-domain
used by the xHCI controller. This list must comprise of a specifier for the
XUSBA and XUSBC power-domains. See ../power/power_domain.txt and
../arm/tegra/nvidia,tegra20-pmc.txt for details.
- power-domain-names: A list of names that represent each of the specifiers in
the 'power-domains' property. Must include 'xusb_ss' and 'xusb_host' which
represent the power-domains XUSBA and XUSBC, respectively. See
../power/power_domain.txt for details.
Optional properties:
--------------------

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@ -0,0 +1,15 @@
/*
* This header provides constants for binding nvidia,tegra194-bpmp-thermal.
*/
#ifndef _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H
#define _DT_BINDINGS_THERMAL_TEGRA194_BPMP_THERMAL_H
#define TEGRA194_BPMP_THERMAL_ZONE_CPU 2
#define TEGRA194_BPMP_THERMAL_ZONE_GPU 3
#define TEGRA194_BPMP_THERMAL_ZONE_AUX 4
#define TEGRA194_BPMP_THERMAL_ZONE_PLLX 5
#define TEGRA194_BPMP_THERMAL_ZONE_AO 6
#define TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX 7
#endif