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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-17 22:46:40 +07:00
powerpc: use mm zones more sensibly
Powerpc has somewhat odd usage where ZONE_DMA is used for all memory on common 64-bit configfs, and ZONE_DMA32 is used for 31-bit schemes. Move to a scheme closer to what other architectures use (and I dare to say the intent of the system): - ZONE_DMA: optionally for memory < 31-bit (64-bit embedded only) - ZONE_NORMAL: everything addressable by the kernel - ZONE_HIGHMEM: memory > 32-bit for 32-bit kernels Also provide information on how ZONE_DMA is used by defining ARCH_ZONE_DMA_BITS. Contains various fixes from Benjamin Herrenschmidt. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -375,9 +375,9 @@ config PPC_ADV_DEBUG_DAC_RANGE
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depends on PPC_ADV_DEBUG_REGS && 44x
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default y
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config ZONE_DMA32
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config ZONE_DMA
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bool
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default y if PPC64
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default y if PPC_BOOK3E_64
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config PGTABLE_LEVELS
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int
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@ -870,10 +870,6 @@ config ISA
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have an IBM RS/6000 or pSeries machine, say Y. If you have an
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embedded board, consult your board documentation.
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config ZONE_DMA
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bool
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default y
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config GENERIC_ISA_DMA
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bool
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depends on ISA_DMA_API
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@ -340,4 +340,6 @@ struct vm_area_struct;
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#endif /* __ASSEMBLY__ */
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#include <asm/slice.h>
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#define ARCH_ZONE_DMA_BITS 31
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#endif /* _ASM_POWERPC_PAGE_H */
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@ -66,7 +66,6 @@ extern unsigned long empty_zero_page[];
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extern pgd_t swapper_pg_dir[];
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void limit_zone_pfn(enum zone_type zone, unsigned long max_pfn);
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int dma_pfn_limit_to_zone(u64 pfn_limit);
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extern void paging_init(void);
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@ -108,12 +108,8 @@ int __init swiotlb_setup_bus_notifier(void)
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void __init swiotlb_detect_4g(void)
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{
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if ((memblock_end_of_DRAM() - 1) > 0xffffffff) {
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if ((memblock_end_of_DRAM() - 1) > 0xffffffff)
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ppc_swiotlb_enable = 1;
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#ifdef CONFIG_ZONE_DMA32
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limit_zone_pfn(ZONE_DMA32, (1ULL << 32) >> PAGE_SHIFT);
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#endif
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}
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}
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static int __init check_swiotlb_enabled(void)
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@ -50,7 +50,8 @@ static int dma_nommu_dma_supported(struct device *dev, u64 mask)
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return 1;
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#ifdef CONFIG_FSL_SOC
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/* Freescale gets another chance via ZONE_DMA/ZONE_DMA32, however
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/*
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* Freescale gets another chance via ZONE_DMA, however
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* that will have to be refined if/when they support iommus
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*/
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return 1;
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@ -88,13 +89,10 @@ void *__dma_nommu_alloc_coherent(struct device *dev, size_t size,
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}
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switch (zone) {
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#ifdef CONFIG_ZONE_DMA
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case ZONE_DMA:
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flag |= GFP_DMA;
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break;
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#ifdef CONFIG_ZONE_DMA32
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case ZONE_DMA32:
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flag |= GFP_DMA32;
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break;
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#endif
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};
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#endif /* CONFIG_FSL_SOC */
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@ -246,35 +246,19 @@ static int __init mark_nonram_nosave(void)
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}
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#endif
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static bool zone_limits_final;
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/*
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* The memory zones past TOP_ZONE are managed by generic mm code.
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* These should be set to zero since that's what every other
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* architecture does.
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* Zones usage:
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*
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* We setup ZONE_DMA to be 31-bits on all platforms and ZONE_NORMAL to be
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* everything else. GFP_DMA32 page allocations automatically fall back to
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* ZONE_DMA.
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*
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* By using 31-bit unconditionally, we can exploit ARCH_ZONE_DMA_BITS to
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* inform the generic DMA mapping code. 32-bit only devices (if not handled
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* by an IOMMU anyway) will take a first dip into ZONE_NORMAL and get
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* otherwise served by ZONE_DMA.
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*/
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static unsigned long max_zone_pfns[MAX_NR_ZONES] = {
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[0 ... TOP_ZONE ] = ~0UL,
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[TOP_ZONE + 1 ... MAX_NR_ZONES - 1] = 0
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};
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/*
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* Restrict the specified zone and all more restrictive zones
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* to be below the specified pfn. May not be called after
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* paging_init().
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*/
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void __init limit_zone_pfn(enum zone_type zone, unsigned long pfn_limit)
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{
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int i;
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if (WARN_ON(zone_limits_final))
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return;
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for (i = zone; i >= 0; i--) {
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if (max_zone_pfns[i] > pfn_limit)
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max_zone_pfns[i] = pfn_limit;
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}
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}
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static unsigned long max_zone_pfns[MAX_NR_ZONES];
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/*
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* Find the least restrictive zone that is entirely below the
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@ -324,11 +308,14 @@ void __init paging_init(void)
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printk(KERN_DEBUG "Memory hole size: %ldMB\n",
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(long int)((top_of_ram - total_ram) >> 20));
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#ifdef CONFIG_HIGHMEM
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limit_zone_pfn(ZONE_NORMAL, lowmem_end_addr >> PAGE_SHIFT);
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#ifdef CONFIG_ZONE_DMA
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max_zone_pfns[ZONE_DMA] = min(max_low_pfn, 0x7fffffffUL >> PAGE_SHIFT);
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#endif
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limit_zone_pfn(TOP_ZONE, top_of_ram >> PAGE_SHIFT);
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zone_limits_final = true;
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max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
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#ifdef CONFIG_HIGHMEM
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max_zone_pfns[ZONE_HIGHMEM] = max_pfn;
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#endif
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free_area_init_nodes(max_zone_pfns);
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mark_nonram_nosave();
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@ -68,16 +68,6 @@ void __init corenet_gen_setup_arch(void)
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swiotlb_detect_4g();
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#if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
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/*
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* Inbound windows don't cover the full lower 4 GiB
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* due to conflicts with PCICSRBAR and outbound windows,
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* so limit the DMA32 zone to 2 GiB, to allow consistent
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* allocations to succeed.
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*/
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limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
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#endif
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pr_info("%s board\n", ppc_md.name);
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mpc85xx_qe_init();
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@ -45,15 +45,6 @@ static void __init qemu_e500_setup_arch(void)
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fsl_pci_assign_primary();
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swiotlb_detect_4g();
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#if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
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/*
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* Inbound windows don't cover the full lower 4 GiB
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* due to conflicts with PCICSRBAR and outbound windows,
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* so limit the DMA32 zone to 2 GiB, to allow consistent
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* allocations to succeed.
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*/
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limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
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#endif
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mpc85xx_smp_init();
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}
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@ -314,7 +314,7 @@ enum zone_type {
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* Architecture Limit
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* ---------------------------
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* parisc, ia64, sparc <4G
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* s390 <2G
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* s390, powerpc <2G
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* arm Various
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* alpha Unlimited or 0-16MB.
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*
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