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Merge branch 'xgene-v2'

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Iyappan Subramanian says:

====================
drivers: net: xgene-v2: Add RGMII based 1G driver

This patch set adds support for RGMII based 1GbE hardware which uses a linked
list of DMA descriptor architecture (v2) for APM X-Gene SoCs.

v4: Address review comments from v3
	- fixed local variable declarations to reverse christmas tree order

v3: Address review comments from v2
	- fixed kbuild warnings (this 'if' clause does not guard)

v2: Address review comments from v1
	- moved create_desc_ring and delete_desc_ring to open() and close()
	  respectively
	- changed to use dma_zalloc APIs
	- fixed tx_timeout()
	- removed tx completion polling upper bound
	- added error checking on rx packets
	- added netif_stop_queue() and netif_wake_queue()

v1:
	- Initial version
====================

Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2017-03-09 13:25:05 -08:00
commit 24d79ce0dc
13 changed files with 1396 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
MAINTAINERS
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@ -902,6 +902,12 @@ F: drivers/net/phy/mdio-xgene.c
F: Documentation/devicetree/bindings/net/apm-xgene-enet.txt
F: Documentation/devicetree/bindings/net/apm-xgene-mdio.txt
APPLIED MICRO (APM) X-GENE SOC ETHERNET (V2) DRIVER
M: Iyappan Subramanian <isubramanian@apm.com>
M: Keyur Chudgar <kchudgar@apm.com>
S: Supported
F: drivers/net/ethernet/apm/xgene-v2/
APPLIED MICRO (APM) X-GENE SOC PMU
M: Tai Nguyen <ttnguyen@apm.com>
S: Supported

1
drivers/net/ethernet/apm/Kconfig
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@ -1 +1,2 @@
source "drivers/net/ethernet/apm/xgene/Kconfig"
source "drivers/net/ethernet/apm/xgene-v2/Kconfig"

1
drivers/net/ethernet/apm/Makefile
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@ -3,3 +3,4 @@
#
obj-$(CONFIG_NET_XGENE) += xgene/
obj-$(CONFIG_NET_XGENE_V2) += xgene-v2/

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drivers/net/ethernet/apm/xgene-v2/Kconfig Normal file
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@ -0,0 +1,11 @@
config NET_XGENE_V2
tristate "APM X-Gene SoC Ethernet-v2 Driver"
depends on HAS_DMA
depends on ARCH_XGENE || COMPILE_TEST
help
This is the Ethernet driver for the on-chip ethernet interface
which uses a linked list of DMA descriptor architecture (v2) for
APM X-Gene SoCs.
To compile this driver as a module, choose M here. This module will
be called xgene-enet-v2.

6
drivers/net/ethernet/apm/xgene-v2/Makefile Normal file
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@ -0,0 +1,6 @@
#
# Makefile for APM X-Gene Ethernet v2 driver
#
xgene-enet-v2-objs := main.o mac.o enet.o ring.o
obj-$(CONFIG_NET_XGENE_V2) += xgene-enet-v2.o

71
drivers/net/ethernet/apm/xgene-v2/enet.c Normal file
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/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "main.h"
void xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val)
{
void __iomem *addr = pdata->resources.base_addr + offset;
iowrite32(val, addr);
}
u32 xge_rd_csr(struct xge_pdata *pdata, u32 offset)
{
void __iomem *addr = pdata->resources.base_addr + offset;
return ioread32(addr);
}
int xge_port_reset(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
xge_wr_csr(pdata, ENET_SRST, 0x3);
xge_wr_csr(pdata, ENET_SRST, 0x2);
xge_wr_csr(pdata, ENET_SRST, 0x0);
xge_wr_csr(pdata, ENET_SHIM, DEVM_ARAUX_COH | DEVM_AWAUX_COH);
return 0;
}
static void xge_traffic_resume(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
xge_wr_csr(pdata, CFG_FORCE_LINK_STATUS_EN, 1);
xge_wr_csr(pdata, FORCE_LINK_STATUS, 1);
xge_wr_csr(pdata, CFG_LINK_AGGR_RESUME, 1);
xge_wr_csr(pdata, RX_DV_GATE_REG, 1);
}
int xge_port_init(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
pdata->phy_speed = SPEED_1000;
xge_mac_init(pdata);
xge_traffic_resume(ndev);
return 0;
}

43
drivers/net/ethernet/apm/xgene-v2/enet.h Normal file
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@ -0,0 +1,43 @@
/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __XGENE_ENET_V2_ENET_H__
#define __XGENE_ENET_V2_ENET_H__
#define ENET_CLKEN 0xc008
#define ENET_SRST 0xc000
#define ENET_SHIM 0xc010
#define CFG_MEM_RAM_SHUTDOWN 0xd070
#define BLOCK_MEM_RDY 0xd074
#define DEVM_ARAUX_COH BIT(19)
#define DEVM_AWAUX_COH BIT(3)
#define CFG_FORCE_LINK_STATUS_EN 0x229c
#define FORCE_LINK_STATUS 0x22a0
#define CFG_LINK_AGGR_RESUME 0x27c8
#define RX_DV_GATE_REG 0x2dfc
void xge_wr_csr(struct xge_pdata *pdata, u32 offset, u32 val);
u32 xge_rd_csr(struct xge_pdata *pdata, u32 offset);
int xge_port_reset(struct net_device *ndev);
#endif /* __XGENE_ENET_V2_ENET__H__ */

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drivers/net/ethernet/apm/xgene-v2/mac.c Normal file
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/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "main.h"
void xge_mac_reset(struct xge_pdata *pdata)
{
xge_wr_csr(pdata, MAC_CONFIG_1, SOFT_RESET);
xge_wr_csr(pdata, MAC_CONFIG_1, 0);
}
static void xge_mac_set_speed(struct xge_pdata *pdata)
{
u32 icm0, icm2, ecm0, mc2;
u32 intf_ctrl, rgmii;
icm0 = xge_rd_csr(pdata, ICM_CONFIG0_REG_0);
icm2 = xge_rd_csr(pdata, ICM_CONFIG2_REG_0);
ecm0 = xge_rd_csr(pdata, ECM_CONFIG0_REG_0);
rgmii = xge_rd_csr(pdata, RGMII_REG_0);
mc2 = xge_rd_csr(pdata, MAC_CONFIG_2);
intf_ctrl = xge_rd_csr(pdata, INTERFACE_CONTROL);
icm2 |= CFG_WAITASYNCRD_EN;
switch (pdata->phy_speed) {
case SPEED_10:
SET_REG_BITS(&mc2, INTF_MODE, 1);
SET_REG_BITS(&intf_ctrl, HD_MODE, 0);
SET_REG_BITS(&icm0, CFG_MACMODE, 0);
SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 500);
SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
break;
case SPEED_100:
SET_REG_BITS(&mc2, INTF_MODE, 1);
SET_REG_BITS(&intf_ctrl, HD_MODE, 1);
SET_REG_BITS(&icm0, CFG_MACMODE, 1);
SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 80);
SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
break;
default:
SET_REG_BITS(&mc2, INTF_MODE, 2);
SET_REG_BITS(&intf_ctrl, HD_MODE, 2);
SET_REG_BITS(&icm0, CFG_MACMODE, 2);
SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 16);
SET_REG_BIT(&rgmii, CFG_SPEED_125, 1);
break;
}
mc2 |= FULL_DUPLEX | CRC_EN | PAD_CRC;
SET_REG_BITS(&ecm0, CFG_WFIFOFULLTHR, 0x32);
xge_wr_csr(pdata, MAC_CONFIG_2, mc2);
xge_wr_csr(pdata, INTERFACE_CONTROL, intf_ctrl);
xge_wr_csr(pdata, RGMII_REG_0, rgmii);
xge_wr_csr(pdata, ICM_CONFIG0_REG_0, icm0);
xge_wr_csr(pdata, ICM_CONFIG2_REG_0, icm2);
xge_wr_csr(pdata, ECM_CONFIG0_REG_0, ecm0);
}
void xge_mac_set_station_addr(struct xge_pdata *pdata)
{
u8 *dev_addr = pdata->ndev->dev_addr;
u32 addr0, addr1;
addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
(dev_addr[1] << 8) | dev_addr[0];
addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
xge_wr_csr(pdata, STATION_ADDR0, addr0);
xge_wr_csr(pdata, STATION_ADDR1, addr1);
}
void xge_mac_init(struct xge_pdata *pdata)
{
xge_mac_reset(pdata);
xge_mac_set_speed(pdata);
xge_mac_set_station_addr(pdata);
}
void xge_mac_enable(struct xge_pdata *pdata)
{
u32 data;
data = xge_rd_csr(pdata, MAC_CONFIG_1);
data |= TX_EN | RX_EN;
xge_wr_csr(pdata, MAC_CONFIG_1, data);
data = xge_rd_csr(pdata, MAC_CONFIG_1);
}
void xge_mac_disable(struct xge_pdata *pdata)
{
u32 data;
data = xge_rd_csr(pdata, MAC_CONFIG_1);
data &= ~(TX_EN | RX_EN);
xge_wr_csr(pdata, MAC_CONFIG_1, data);
}

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drivers/net/ethernet/apm/xgene-v2/mac.h Normal file
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/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __XGENE_ENET_V2_MAC_H__
#define __XGENE_ENET_V2_MAC_H__
/* Register offsets */
#define MAC_CONFIG_1 0xa000
#define MAC_CONFIG_2 0xa004
#define MII_MGMT_CONFIG 0xa020
#define MII_MGMT_COMMAND 0xa024
#define MII_MGMT_ADDRESS 0xa028
#define MII_MGMT_CONTROL 0xa02c
#define MII_MGMT_STATUS 0xa030
#define MII_MGMT_INDICATORS 0xa034
#define INTERFACE_CONTROL 0xa038
#define STATION_ADDR0 0xa040
#define STATION_ADDR1 0xa044
#define RBYT 0xa09c
#define RPKT 0xa0a0
#define RFCS 0xa0a4
#define RGMII_REG_0 0x27e0
#define ICM_CONFIG0_REG_0 0x2c00
#define ICM_CONFIG2_REG_0 0x2c08
#define ECM_CONFIG0_REG_0 0x2d00
/* Register fields */
#define SOFT_RESET BIT(31)
#define TX_EN BIT(0)
#define RX_EN BIT(2)
#define PAD_CRC BIT(2)
#define CRC_EN BIT(1)
#define FULL_DUPLEX BIT(0)
#define INTF_MODE_POS 8
#define INTF_MODE_LEN 2
#define HD_MODE_POS 25
#define HD_MODE_LEN 2
#define CFG_MACMODE_POS 18
#define CFG_MACMODE_LEN 2
#define CFG_WAITASYNCRD_POS 0
#define CFG_WAITASYNCRD_LEN 16
#define CFG_SPEED_125_POS 24
#define CFG_WFIFOFULLTHR_POS 0
#define CFG_WFIFOFULLTHR_LEN 7
#define MGMT_CLOCK_SEL_POS 0
#define MGMT_CLOCK_SEL_LEN 3
#define PHY_ADDR_POS 8
#define PHY_ADDR_LEN 5
#define REG_ADDR_POS 0
#define REG_ADDR_LEN 5
#define MII_MGMT_BUSY BIT(0)
#define MII_READ_CYCLE BIT(0)
#define CFG_WAITASYNCRD_EN BIT(16)
static inline void xgene_set_reg_bits(u32 *var, int pos, int len, u32 val)
{
u32 mask = GENMASK(pos + len, pos);
*var &= ~mask;
*var |= ((val << pos) & mask);
}
static inline u32 xgene_get_reg_bits(u32 var, int pos, int len)
{
u32 mask = GENMASK(pos + len, pos);
return (var & mask) >> pos;
}
#define SET_REG_BITS(var, field, val) \
xgene_set_reg_bits(var, field ## _POS, field ## _LEN, val)
#define SET_REG_BIT(var, field, val) \
xgene_set_reg_bits(var, field ## _POS, 1, val)
#define GET_REG_BITS(var, field) \
xgene_get_reg_bits(var, field ## _POS, field ## _LEN)
#define GET_REG_BIT(var, field) ((var) & (field))
struct xge_pdata;
void xge_mac_reset(struct xge_pdata *pdata);
void xge_mac_enable(struct xge_pdata *pdata);
void xge_mac_disable(struct xge_pdata *pdata);
void xge_mac_init(struct xge_pdata *pdata);
int xge_port_init(struct net_device *ndev);
void xge_mac_set_station_addr(struct xge_pdata *pdata);
#endif /* __XGENE_ENET_V2_MAC_H__ */

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drivers/net/ethernet/apm/xgene-v2/main.c Normal file
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/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "main.h"
static const struct acpi_device_id xge_acpi_match[];
static int xge_get_resources(struct xge_pdata *pdata)
{
struct platform_device *pdev;
struct net_device *ndev;
int phy_mode, ret = 0;
struct resource *res;
struct device *dev;
pdev = pdata->pdev;
dev = &pdev->dev;
ndev = pdata->ndev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, "Resource enet_csr not defined\n");
return -ENODEV;
}
pdata->resources.base_addr = devm_ioremap(dev, res->start,
resource_size(res));
if (!pdata->resources.base_addr) {
dev_err(dev, "Unable to retrieve ENET Port CSR region\n");
return -ENOMEM;
}
if (!device_get_mac_address(dev, ndev->dev_addr, ETH_ALEN))
eth_hw_addr_random(ndev);
memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
phy_mode = device_get_phy_mode(dev);
if (phy_mode < 0) {
dev_err(dev, "Unable to get phy-connection-type\n");
return phy_mode;
}
pdata->resources.phy_mode = phy_mode;
if (pdata->resources.phy_mode != PHY_INTERFACE_MODE_RGMII) {
dev_err(dev, "Incorrect phy-connection-type specified\n");
return -ENODEV;
}
ret = platform_get_irq(pdev, 0);
if (ret <= 0) {
dev_err(dev, "Unable to get ENET IRQ\n");
ret = ret ? : -ENXIO;
return ret;
}
pdata->resources.irq = ret;
return 0;
}
static int xge_refill_buffers(struct net_device *ndev, u32 nbuf)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct xge_desc_ring *ring = pdata->rx_ring;
const u8 slots = XGENE_ENET_NUM_DESC - 1;
struct device *dev = &pdata->pdev->dev;
struct xge_raw_desc *raw_desc;
u64 addr_lo, addr_hi;
u8 tail = ring->tail;
struct sk_buff *skb;
dma_addr_t dma_addr;
u16 len;
int i;
for (i = 0; i < nbuf; i++) {
raw_desc = &ring->raw_desc[tail];
len = XGENE_ENET_STD_MTU;
skb = netdev_alloc_skb(ndev, len);
if (unlikely(!skb))
return -ENOMEM;
dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE);
if (dma_mapping_error(dev, dma_addr)) {
netdev_err(ndev, "DMA mapping error\n");
dev_kfree_skb_any(skb);
return -EINVAL;
}
ring->pkt_info[tail].skb = skb;
ring->pkt_info[tail].dma_addr = dma_addr;
addr_hi = GET_BITS(NEXT_DESC_ADDRH, le64_to_cpu(raw_desc->m1));
addr_lo = GET_BITS(NEXT_DESC_ADDRL, le64_to_cpu(raw_desc->m1));
raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, addr_lo) |
SET_BITS(NEXT_DESC_ADDRH, addr_hi) |
SET_BITS(PKT_ADDRH,
upper_32_bits(dma_addr)));
dma_wmb();
raw_desc->m0 = cpu_to_le64(SET_BITS(PKT_ADDRL, dma_addr) |
SET_BITS(E, 1));
tail = (tail + 1) & slots;
}
ring->tail = tail;
return 0;
}
static int xge_init_hw(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
int ret;
ret = xge_port_reset(ndev);
if (ret)
return ret;
xge_port_init(ndev);
pdata->nbufs = NUM_BUFS;
return 0;
}
static irqreturn_t xge_irq(const int irq, void *data)
{
struct xge_pdata *pdata = data;
if (napi_schedule_prep(&pdata->napi)) {
xge_intr_disable(pdata);
__napi_schedule(&pdata->napi);
}
return IRQ_HANDLED;
}
static int xge_request_irq(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct device *dev = &pdata->pdev->dev;
int ret;
snprintf(pdata->irq_name, IRQ_ID_SIZE, "%s", ndev->name);
ret = devm_request_irq(dev, pdata->resources.irq, xge_irq,
0, pdata->irq_name, pdata);
if (ret)
netdev_err(ndev, "Failed to request irq %s\n", pdata->irq_name);
return ret;
}
static void xge_free_irq(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct device *dev = &pdata->pdev->dev;
devm_free_irq(dev, pdata->resources.irq, pdata);
}
static bool is_tx_slot_available(struct xge_raw_desc *raw_desc)
{
if (GET_BITS(E, le64_to_cpu(raw_desc->m0)) &&
(GET_BITS(PKT_SIZE, le64_to_cpu(raw_desc->m0)) == SLOT_EMPTY))
return true;
return false;
}
static netdev_tx_t xge_start_xmit(struct sk_buff *skb, struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct device *dev = &pdata->pdev->dev;
struct xge_desc_ring *tx_ring;
struct xge_raw_desc *raw_desc;
static dma_addr_t dma_addr;
u64 addr_lo, addr_hi;
void *pkt_buf;
u8 tail;
u16 len;
tx_ring = pdata->tx_ring;
tail = tx_ring->tail;
len = skb_headlen(skb);
raw_desc = &tx_ring->raw_desc[tail];
if (!is_tx_slot_available(raw_desc)) {
netif_stop_queue(ndev);
return NETDEV_TX_BUSY;
}
/* Packet buffers should be 64B aligned */
pkt_buf = dma_zalloc_coherent(dev, XGENE_ENET_STD_MTU, &dma_addr,
GFP_ATOMIC);
if (unlikely(!pkt_buf)) {
dev_kfree_skb_any(skb);
return NETDEV_TX_OK;
}
memcpy(pkt_buf, skb->data, len);
addr_hi = GET_BITS(NEXT_DESC_ADDRH, le64_to_cpu(raw_desc->m1));
addr_lo = GET_BITS(NEXT_DESC_ADDRL, le64_to_cpu(raw_desc->m1));
raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, addr_lo) |
SET_BITS(NEXT_DESC_ADDRH, addr_hi) |
SET_BITS(PKT_ADDRH,
upper_32_bits(dma_addr)));
tx_ring->pkt_info[tail].skb = skb;
tx_ring->pkt_info[tail].dma_addr = dma_addr;
tx_ring->pkt_info[tail].pkt_buf = pkt_buf;
dma_wmb();
raw_desc->m0 = cpu_to_le64(SET_BITS(PKT_ADDRL, dma_addr) |
SET_BITS(PKT_SIZE, len) |
SET_BITS(E, 0));
skb_tx_timestamp(skb);
xge_wr_csr(pdata, DMATXCTRL, 1);
tx_ring->tail = (tail + 1) & (XGENE_ENET_NUM_DESC - 1);
return NETDEV_TX_OK;
}
static bool is_tx_hw_done(struct xge_raw_desc *raw_desc)
{
if (GET_BITS(E, le64_to_cpu(raw_desc->m0)) &&
!GET_BITS(PKT_SIZE, le64_to_cpu(raw_desc->m0)))
return true;
return false;
}
static void xge_txc_poll(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct device *dev = &pdata->pdev->dev;
struct xge_desc_ring *tx_ring;
struct xge_raw_desc *raw_desc;
dma_addr_t dma_addr;
struct sk_buff *skb;
void *pkt_buf;
u32 data;
u8 head;
tx_ring = pdata->tx_ring;
head = tx_ring->head;
data = xge_rd_csr(pdata, DMATXSTATUS);
if (!GET_BITS(TXPKTCOUNT, data))
return;
while (1) {
raw_desc = &tx_ring->raw_desc[head];
if (!is_tx_hw_done(raw_desc))
break;
dma_rmb();
skb = tx_ring->pkt_info[head].skb;
dma_addr = tx_ring->pkt_info[head].dma_addr;
pkt_buf = tx_ring->pkt_info[head].pkt_buf;
pdata->stats.tx_packets++;
pdata->stats.tx_bytes += skb->len;
dma_free_coherent(dev, XGENE_ENET_STD_MTU, pkt_buf, dma_addr);
dev_kfree_skb_any(skb);
/* clear pktstart address and pktsize */
raw_desc->m0 = cpu_to_le64(SET_BITS(E, 1) |
SET_BITS(PKT_SIZE, SLOT_EMPTY));
xge_wr_csr(pdata, DMATXSTATUS, 1);
head = (head + 1) & (XGENE_ENET_NUM_DESC - 1);
}
if (netif_queue_stopped(ndev))
netif_wake_queue(ndev);
tx_ring->head = head;
}
static int xge_rx_poll(struct net_device *ndev, unsigned int budget)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct device *dev = &pdata->pdev->dev;
struct xge_desc_ring *rx_ring;
struct xge_raw_desc *raw_desc;
struct sk_buff *skb;
dma_addr_t dma_addr;
int processed = 0;
u8 head, rx_error;
int i, ret;
u32 data;
u16 len;
rx_ring = pdata->rx_ring;
head = rx_ring->head;
data = xge_rd_csr(pdata, DMARXSTATUS);
if (!GET_BITS(RXPKTCOUNT, data))
return 0;
for (i = 0; i < budget; i++) {
raw_desc = &rx_ring->raw_desc[head];
if (GET_BITS(E, le64_to_cpu(raw_desc->m0)))
break;
dma_rmb();
skb = rx_ring->pkt_info[head].skb;
rx_ring->pkt_info[head].skb = NULL;
dma_addr = rx_ring->pkt_info[head].dma_addr;
len = GET_BITS(PKT_SIZE, le64_to_cpu(raw_desc->m0));
dma_unmap_single(dev, dma_addr, XGENE_ENET_STD_MTU,
DMA_FROM_DEVICE);
rx_error = GET_BITS(D, le64_to_cpu(raw_desc->m2));
if (unlikely(rx_error)) {
pdata->stats.rx_errors++;
dev_kfree_skb_any(skb);
goto out;
}
skb_put(skb, len);
skb->protocol = eth_type_trans(skb, ndev);
pdata->stats.rx_packets++;
pdata->stats.rx_bytes += len;
napi_gro_receive(&pdata->napi, skb);
out:
ret = xge_refill_buffers(ndev, 1);
xge_wr_csr(pdata, DMARXSTATUS, 1);
xge_wr_csr(pdata, DMARXCTRL, 1);
if (ret)
break;
head = (head + 1) & (XGENE_ENET_NUM_DESC - 1);
processed++;
}
rx_ring->head = head;
return processed;
}
static void xge_delete_desc_ring(struct net_device *ndev,
struct xge_desc_ring *ring)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct device *dev = &pdata->pdev->dev;
u16 size;
if (!ring)
return;
size = XGENE_ENET_DESC_SIZE * XGENE_ENET_NUM_DESC;
if (ring->desc_addr)
dma_free_coherent(dev, size, ring->desc_addr, ring->dma_addr);
kfree(ring->pkt_info);
kfree(ring);
}
static void xge_free_buffers(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct xge_desc_ring *ring = pdata->rx_ring;
struct device *dev = &pdata->pdev->dev;
struct sk_buff *skb;
dma_addr_t dma_addr;
int i;
for (i = 0; i < XGENE_ENET_NUM_DESC; i++) {
skb = ring->pkt_info[i].skb;
dma_addr = ring->pkt_info[i].dma_addr;
if (!skb)
continue;
dma_unmap_single(dev, dma_addr, XGENE_ENET_STD_MTU,
DMA_FROM_DEVICE);
dev_kfree_skb_any(skb);
}
}
static void xge_delete_desc_rings(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
xge_txc_poll(ndev);
xge_delete_desc_ring(ndev, pdata->tx_ring);
xge_rx_poll(ndev, 64);
xge_free_buffers(ndev);
xge_delete_desc_ring(ndev, pdata->rx_ring);
}
static struct xge_desc_ring *xge_create_desc_ring(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct device *dev = &pdata->pdev->dev;
struct xge_desc_ring *ring;
u16 size;
ring = kzalloc(sizeof(struct xge_desc_ring), GFP_KERNEL);
if (!ring)
return NULL;
ring->ndev = ndev;
size = XGENE_ENET_DESC_SIZE * XGENE_ENET_NUM_DESC;
ring->desc_addr = dma_zalloc_coherent(dev, size, &ring->dma_addr,
GFP_KERNEL);
if (!ring->desc_addr)
goto err;
ring->pkt_info = kcalloc(XGENE_ENET_NUM_DESC, sizeof(struct pkt_info),
GFP_KERNEL);
if (!ring->pkt_info)
goto err;
xge_setup_desc(ring);
return ring;
err:
xge_delete_desc_ring(ndev, ring);
return NULL;
}
static int xge_create_desc_rings(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct xge_desc_ring *ring;
int ret;
/* create tx ring */
ring = xge_create_desc_ring(ndev);
if (!ring)
goto err;
pdata->tx_ring = ring;
xge_update_tx_desc_addr(pdata);
/* create rx ring */
ring = xge_create_desc_ring(ndev);
if (!ring)
goto err;
pdata->rx_ring = ring;
xge_update_rx_desc_addr(pdata);
ret = xge_refill_buffers(ndev, XGENE_ENET_NUM_DESC);
if (ret)
goto err;
return 0;
err:
xge_delete_desc_rings(ndev);
return -ENOMEM;
}
static int xge_open(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
int ret;
ret = xge_create_desc_rings(ndev);
if (ret)
return ret;
napi_enable(&pdata->napi);
ret = xge_request_irq(ndev);
if (ret)
return ret;
xge_intr_enable(pdata);
xge_wr_csr(pdata, DMARXCTRL, 1);
xge_mac_enable(pdata);
netif_start_queue(ndev);
netif_carrier_on(ndev);
return 0;
}
static int xge_close(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
netif_carrier_off(ndev);
netif_stop_queue(ndev);
xge_mac_disable(pdata);
xge_intr_disable(pdata);
xge_free_irq(ndev);
napi_disable(&pdata->napi);
xge_delete_desc_rings(ndev);
return 0;
}
static int xge_napi(struct napi_struct *napi, const int budget)
{
struct net_device *ndev = napi->dev;
struct xge_pdata *pdata;
int processed;
pdata = netdev_priv(ndev);
xge_txc_poll(ndev);
processed = xge_rx_poll(ndev, budget);
if (processed < budget) {
napi_complete_done(napi, processed);
xge_intr_enable(pdata);
}
return processed;
}
static int xge_set_mac_addr(struct net_device *ndev, void *addr)
{
struct xge_pdata *pdata = netdev_priv(ndev);
int ret;
ret = eth_mac_addr(ndev, addr);
if (ret)
return ret;
xge_mac_set_station_addr(pdata);
return 0;
}
static bool is_tx_pending(struct xge_raw_desc *raw_desc)
{
if (!GET_BITS(E, le64_to_cpu(raw_desc->m0)))
return true;
return false;
}
static void xge_free_pending_skb(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct device *dev = &pdata->pdev->dev;
struct xge_desc_ring *tx_ring;
struct xge_raw_desc *raw_desc;
dma_addr_t dma_addr;
struct sk_buff *skb;
void *pkt_buf;
int i;
tx_ring = pdata->tx_ring;
for (i = 0; i < XGENE_ENET_NUM_DESC; i++) {
raw_desc = &tx_ring->raw_desc[i];
if (!is_tx_pending(raw_desc))
continue;
skb = tx_ring->pkt_info[i].skb;
dma_addr = tx_ring->pkt_info[i].dma_addr;
pkt_buf = tx_ring->pkt_info[i].pkt_buf;
dma_free_coherent(dev, XGENE_ENET_STD_MTU, pkt_buf, dma_addr);
dev_kfree_skb_any(skb);
}
}
static void xge_timeout(struct net_device *ndev)
{
struct xge_pdata *pdata = netdev_priv(ndev);
rtnl_lock();
if (netif_running(ndev)) {
netif_carrier_off(ndev);
netif_stop_queue(ndev);
xge_intr_disable(pdata);
napi_disable(&pdata->napi);
xge_wr_csr(pdata, DMATXCTRL, 0);
xge_txc_poll(ndev);
xge_free_pending_skb(ndev);
xge_wr_csr(pdata, DMATXSTATUS, ~0U);
xge_setup_desc(pdata->tx_ring);
xge_update_tx_desc_addr(pdata);
xge_mac_init(pdata);
napi_enable(&pdata->napi);
xge_intr_enable(pdata);
xge_mac_enable(pdata);
netif_start_queue(ndev);
netif_carrier_on(ndev);
}
rtnl_unlock();
}
static void xge_get_stats64(struct net_device *ndev,
struct rtnl_link_stats64 *storage)
{
struct xge_pdata *pdata = netdev_priv(ndev);
struct xge_stats *stats = &pdata->stats;
storage->tx_packets += stats->tx_packets;
storage->tx_bytes += stats->tx_bytes;
storage->rx_packets += stats->rx_packets;
storage->rx_bytes += stats->rx_bytes;
storage->rx_errors += stats->rx_errors;
}
static const struct net_device_ops xgene_ndev_ops = {
.ndo_open = xge_open,
.ndo_stop = xge_close,
.ndo_start_xmit = xge_start_xmit,
.ndo_set_mac_address = xge_set_mac_addr,
.ndo_tx_timeout = xge_timeout,
.ndo_get_stats64 = xge_get_stats64,
};
static int xge_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct net_device *ndev;
struct xge_pdata *pdata;
int ret;
ndev = alloc_etherdev(sizeof(struct xge_pdata));
if (!ndev)
return -ENOMEM;
pdata = netdev_priv(ndev);
pdata->pdev = pdev;
pdata->ndev = ndev;
SET_NETDEV_DEV(ndev, dev);
platform_set_drvdata(pdev, pdata);
ndev->netdev_ops = &xgene_ndev_ops;
ndev->features |= NETIF_F_GSO |
NETIF_F_GRO;
ret = xge_get_resources(pdata);
if (ret)
goto err;
ndev->hw_features = ndev->features;
ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
if (ret) {
netdev_err(ndev, "No usable DMA configuration\n");
goto err;
}
ret = xge_init_hw(ndev);
if (ret)
goto err;
netif_napi_add(ndev, &pdata->napi, xge_napi, NAPI_POLL_WEIGHT);
netif_carrier_off(ndev);
ret = register_netdev(ndev);
if (ret) {
netdev_err(ndev, "Failed to register netdev\n");
goto err;
}
return 0;
err:
free_netdev(ndev);
return ret;
}
static int xge_remove(struct platform_device *pdev)
{
struct xge_pdata *pdata;
struct net_device *ndev;
pdata = platform_get_drvdata(pdev);
ndev = pdata->ndev;
rtnl_lock();
if (netif_running(ndev))
dev_close(ndev);
rtnl_unlock();
unregister_netdev(ndev);
free_netdev(ndev);
return 0;
}
static void xge_shutdown(struct platform_device *pdev)
{
struct xge_pdata *pdata;
pdata = platform_get_drvdata(pdev);
if (!pdata)
return;
if (!pdata->ndev)
return;
xge_remove(pdev);
}
static const struct acpi_device_id xge_acpi_match[] = {
{ "APMC0D80" },
{ }
};
MODULE_DEVICE_TABLE(acpi, xge_acpi_match);
static struct platform_driver xge_driver = {
.driver = {
.name = "xgene-enet-v2",
.acpi_match_table = ACPI_PTR(xge_acpi_match),
},
.probe = xge_probe,
.remove = xge_remove,
.shutdown = xge_shutdown,
};
module_platform_driver(xge_driver);
MODULE_DESCRIPTION("APM X-Gene SoC Ethernet v2 driver");
MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>");
MODULE_VERSION(XGENE_ENET_V2_VERSION);
MODULE_LICENSE("GPL");

75
drivers/net/ethernet/apm/xgene-v2/main.h Normal file
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/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __XGENE_ENET_V2_MAIN_H__
#define __XGENE_ENET_V2_MAIN_H__
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/efi.h>
#include <linux/if_vlan.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/of_net.h>
#include <linux/of_mdio.h>
#include <linux/prefetch.h>
#include <linux/phy.h>
#include <net/ip.h>
#include "mac.h"
#include "enet.h"
#include "ring.h"
#define XGENE_ENET_V2_VERSION "v1.0"
#define XGENE_ENET_STD_MTU 1536
#define XGENE_ENET_MIN_FRAME 60
#define IRQ_ID_SIZE 16
struct xge_resource {
void __iomem *base_addr;
int phy_mode;
u32 irq;
};
struct xge_stats {
u64 tx_packets;
u64 tx_bytes;
u64 rx_packets;
u64 rx_bytes;
u64 rx_errors;
};
/* ethernet private data */
struct xge_pdata {
struct xge_resource resources;
struct xge_desc_ring *tx_ring;
struct xge_desc_ring *rx_ring;
struct platform_device *pdev;
char irq_name[IRQ_ID_SIZE];
struct net_device *ndev;
struct napi_struct napi;
struct xge_stats stats;
int phy_speed;
u8 nbufs;
};
#endif /* __XGENE_ENET_V2_MAIN_H__ */

81
drivers/net/ethernet/apm/xgene-v2/ring.c Normal file
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/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "main.h"
/* create circular linked list of descriptors */
void xge_setup_desc(struct xge_desc_ring *ring)
{
struct xge_raw_desc *raw_desc;
dma_addr_t dma_h, next_dma;
u16 offset;
int i;
for (i = 0; i < XGENE_ENET_NUM_DESC; i++) {
raw_desc = &ring->raw_desc[i];
offset = (i + 1) & (XGENE_ENET_NUM_DESC - 1);
next_dma = ring->dma_addr + (offset * XGENE_ENET_DESC_SIZE);
raw_desc->m0 = cpu_to_le64(SET_BITS(E, 1) |
SET_BITS(PKT_SIZE, SLOT_EMPTY));
dma_h = upper_32_bits(next_dma);
raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, next_dma) |
SET_BITS(NEXT_DESC_ADDRH, dma_h));
}
}
void xge_update_tx_desc_addr(struct xge_pdata *pdata)
{
struct xge_desc_ring *ring = pdata->tx_ring;
dma_addr_t dma_addr = ring->dma_addr;
xge_wr_csr(pdata, DMATXDESCL, dma_addr);
xge_wr_csr(pdata, DMATXDESCH, upper_32_bits(dma_addr));
ring->head = 0;
ring->tail = 0;
}
void xge_update_rx_desc_addr(struct xge_pdata *pdata)
{
struct xge_desc_ring *ring = pdata->rx_ring;
dma_addr_t dma_addr = ring->dma_addr;
xge_wr_csr(pdata, DMARXDESCL, dma_addr);
xge_wr_csr(pdata, DMARXDESCH, upper_32_bits(dma_addr));
ring->head = 0;
ring->tail = 0;
}
void xge_intr_enable(struct xge_pdata *pdata)
{
u32 data;
data = RX_PKT_RCVD | TX_PKT_SENT;
xge_wr_csr(pdata, DMAINTRMASK, data);
}
void xge_intr_disable(struct xge_pdata *pdata)
{
xge_wr_csr(pdata, DMAINTRMASK, 0);
}

119
drivers/net/ethernet/apm/xgene-v2/ring.h Normal file
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/*
* Applied Micro X-Gene SoC Ethernet v2 Driver
*
* Copyright (c) 2017, Applied Micro Circuits Corporation
* Author(s): Iyappan Subramanian <isubramanian@apm.com>
* Keyur Chudgar <kchudgar@apm.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __XGENE_ENET_V2_RING_H__
#define __XGENE_ENET_V2_RING_H__
#define XGENE_ENET_DESC_SIZE 64
#define XGENE_ENET_NUM_DESC 256
#define NUM_BUFS 8
#define SLOT_EMPTY 0xfff
#define DMATXCTRL 0xa180
#define DMATXDESCL 0xa184
#define DMATXDESCH 0xa1a0
#define DMATXSTATUS 0xa188
#define DMARXCTRL 0xa18c
#define DMARXDESCL 0xa190
#define DMARXDESCH 0xa1a4
#define DMARXSTATUS 0xa194
#define DMAINTRMASK 0xa198
#define DMAINTERRUPT 0xa19c
#define D_POS 62
#define D_LEN 2
#define E_POS 63
#define E_LEN 1
#define PKT_ADDRL_POS 0
#define PKT_ADDRL_LEN 32
#define PKT_ADDRH_POS 32
#define PKT_ADDRH_LEN 10
#define PKT_SIZE_POS 32
#define PKT_SIZE_LEN 12
#define NEXT_DESC_ADDRL_POS 0
#define NEXT_DESC_ADDRL_LEN 32
#define NEXT_DESC_ADDRH_POS 48
#define NEXT_DESC_ADDRH_LEN 10
#define TXPKTCOUNT_POS 16
#define TXPKTCOUNT_LEN 8
#define RXPKTCOUNT_POS 16
#define RXPKTCOUNT_LEN 8
#define TX_PKT_SENT BIT(0)
#define TX_BUS_ERROR BIT(3)
#define RX_PKT_RCVD BIT(4)
#define RX_BUS_ERROR BIT(7)
#define RXSTATUS_RXPKTRCVD BIT(0)
struct xge_raw_desc {
__le64 m0;
__le64 m1;
__le64 m2;
__le64 m3;
__le64 m4;
__le64 m5;
__le64 m6;
__le64 m7;
};
struct pkt_info {
struct sk_buff *skb;
dma_addr_t dma_addr;
void *pkt_buf;
};
/* software context of a descriptor ring */
struct xge_desc_ring {
struct net_device *ndev;
dma_addr_t dma_addr;
u8 head;
u8 tail;
union {
void *desc_addr;
struct xge_raw_desc *raw_desc;
};
struct pkt_info (*pkt_info);
};
static inline u64 xge_set_desc_bits(int pos, int len, u64 val)
{
return (val & ((1ULL << len) - 1)) << pos;
}
static inline u64 xge_get_desc_bits(int pos, int len, u64 src)
{
return (src >> pos) & ((1ULL << len) - 1);
}
#define SET_BITS(field, val) \
xge_set_desc_bits(field ## _POS, field ## _LEN, val)
#define GET_BITS(field, src) \
xge_get_desc_bits(field ## _POS, field ## _LEN, src)
void xge_setup_desc(struct xge_desc_ring *ring);
void xge_update_tx_desc_addr(struct xge_pdata *pdata);
void xge_update_rx_desc_addr(struct xge_pdata *pdata);
void xge_intr_enable(struct xge_pdata *pdata);
void xge_intr_disable(struct xge_pdata *pdata);
#endif /* __XGENE_ENET_V2_RING_H__ */