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Our usual bunch of patches to support the Allwinner SoCs, this time

Browse Source 
adding:
   - Allwinner A100 initial support
   - Mali, DMA, cedrus and IR Support for the R40
   - Crypto support for the v3s
   - New board: Allwinner A100 Perf1
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Merge tag 'sunxi-dt-for-5.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt

Our usual bunch of patches to support the Allwinner SoCs, this time
adding:
  - Allwinner A100 initial support
  - Mali, DMA, cedrus and IR Support for the R40
  - Crypto support for the v3s
  - New board: Allwinner A100 Perf1

* tag 'sunxi-dt-for-5.10-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (24 commits)
  ARM: dts: sun8i: v3s: Enable crypto engine
  dt-bindings: crypto: Add compatible for V3s
  dt-bindings: crypto: Specify that allwinner, sun8i-a33-crypto needs reset
  arm64: dts: allwinner: a64: Update the audio codec compatible
  arm64: dts: allwinner: a64: Update codec widget names
  ARM: dts: sun8i: a33: Update codec widget names
  ARM: dts: sun8i: r40: Add video engine node
  ARM: dts: sun8i: r40: Add node for system controller
  dt-bindings: sram: allwinner, sun4i-a10-system-control: Add R40 compatibles
  ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable IR
  ARM: dts: sun8i: r40: Add IR nodes
  dt-bindings: media: allwinner, sun4i-a10-ir: Add R40 compatible
  ARM: dts: sun8i: r40: Add DMA node
  dt-bindings: dma: allwinner,sun50i-a64-dma: Add R40 compatible
  arm64: allwinner: A100: add support for Allwinner Perf1 board
  dt-bindings: arm: sunxi: Add Allwinner A100 Perf1 Board bindings
  arm64: allwinner: A100: add the basical Allwinner A100 DTSI file
  dt-bindings: irq: sun7i-nmi: Add binding for A100's NMI controller
  dt-bindings: irq: sun7i-nmi: fix dt-binding for a80 nmi
  ARM: dts: sun4i: Enable HDMI support on the Mele A1000
  ...

Link: https://lore.kernel.org/r/ac39ee89-ea3a-4971-8cd7-8c4b2ecef39d.lettre@localhost
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2020-10-03 12:34:01 -07:00
commit 2494ad156d
27 changed files with 770 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/devicetree/bindings/arm/sunxi.yaml
View File

@ -16,6 +16,11 @@ properties:
compatible:
oneOf:
- description: Allwinner A100 Perf1 Board
items:
- const: allwinner,a100-perf1
- const: allwinner,sun50i-a100
- description: Allwinner A23 Evaluation Board
items:
- const: allwinner,sun8i-a23-evb

6
Documentation/devicetree/bindings/crypto/allwinner,sun4i-a10-crypto.yaml
View File

@ -23,7 +23,9 @@ properties:
- items:
- const: allwinner,sun7i-a20-crypto
- const: allwinner,sun4i-a10-crypto
- const: allwinner,sun8i-a33-crypto
- items:
- const: allwinner,sun8i-v3s-crypto
- const: allwinner,sun8i-a33-crypto
reg:
@ -59,7 +61,9 @@ if:
properties:
compatible:
contains:
const: allwinner,sun6i-a31-crypto
enum:
- allwinner,sun6i-a31-crypto
- allwinner,sun8i-a33-crypto
then:
required:

9
Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
View File

@ -19,9 +19,12 @@ properties:
description: The cell is the request line number.
compatible:
enum:
- allwinner,sun50i-a64-dma
- allwinner,sun50i-h6-dma
oneOf:
- const: allwinner,sun50i-a64-dma
- const: allwinner,sun50i-h6-dma
- items:
- const: allwinner,sun8i-r40-dma
- const: allwinner,sun50i-a64-dma
reg:
maxItems: 1

2
Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
View File

@ -25,6 +25,7 @@ properties:
- allwinner,sun4i-a10-mali
- allwinner,sun7i-a20-mali
- allwinner,sun8i-h3-mali
- allwinner,sun8i-r40-mali
- allwinner,sun50i-a64-mali
- rockchip,rk3036-mali
- rockchip,rk3066-mali
@ -129,6 +130,7 @@ allOf:
enum:
- allwinner,sun4i-a10-mali
- allwinner,sun7i-a20-mali
- allwinner,sun8i-r40-mali
- allwinner,sun50i-a64-mali
- allwinner,sun50i-h5-mali
- amlogic,meson8-mali

5
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
View File

@ -29,10 +29,13 @@ properties:
- items:
- const: allwinner,sun8i-a83t-r-intc
- const: allwinner,sun6i-a31-r-intc
- const: allwinner,sun9i-a80-sc-nmi
- const: allwinner,sun9i-a80-nmi
- items:
- const: allwinner,sun50i-a64-r-intc
- const: allwinner,sun6i-a31-r-intc
- items:
- const: allwinner,sun50i-a100-nmi
- const: allwinner,sun9i-a80-nmi
- items:
- const: allwinner,sun50i-h6-r-intc
- const: allwinner,sun6i-a31-r-intc

5
Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml
View File

@ -18,10 +18,13 @@ properties:
oneOf:
- const: allwinner,sun4i-a10-ir
- const: allwinner,sun5i-a13-ir
- const: allwinner,sun6i-a31-ir
- items:
- const: allwinner,sun8i-a83t-ir
- const: allwinner,sun6i-a31-ir
- const: allwinner,sun6i-a31-ir
- items:
- const: allwinner,sun8i-r40-ir
- const: allwinner,sun6i-a31-ir
- items:
- const: allwinner,sun50i-a64-ir
- const: allwinner,sun6i-a31-ir

6
Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
View File

@ -33,6 +33,9 @@ properties:
- const: allwinner,sun4i-a10-system-control
- const: allwinner,sun8i-a23-system-control
- const: allwinner,sun8i-h3-system-control
- items:
- const: allwinner,sun8i-r40-system-control
- const: allwinner,sun4i-a10-system-control
- const: allwinner,sun50i-a64-sram-controller
deprecated: true
- const: allwinner,sun50i-a64-system-control
@ -86,6 +89,9 @@ patternProperties:
- items:
- const: allwinner,sun8i-h3-sram-c1
- const: allwinner,sun4i-a10-sram-c1
- items:
- const: allwinner,sun8i-r40-sram-c1
- const: allwinner,sun4i-a10-sram-c1
- items:
- const: allwinner,sun50i-a64-sram-c1
- const: allwinner,sun4i-a10-sram-c1

25
arch/arm/boot/dts/sun4i-a10-a1000.dts
View File

@ -60,6 +60,17 @@ chosen {
stdout-path = "serial0:115200n8";
};
hdmi-connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
@ -133,6 +144,20 @@ &emac_sram {
status = "okay";
};
&de {
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&i2c0 {
status = "okay";

4
arch/arm/boot/dts/sun8i-a33-olinuxino.dts
View File

@ -194,8 +194,8 @@ &sound {
"Headphone", "Headphone Jack";
/* Board level routing. First 2 routes copied from SoC level */
simple-audio-card,routing =
"Left DAC", "AIF1 Slot 0 Left",
"Right DAC", "AIF1 Slot 0 Right",
"Left DAC", "DACL",
"Right DAC", "DACR",
"HP", "HPCOM",
"Headphone Jack", "HP",
"MIC1", "Microphone Jack",

4
arch/arm/boot/dts/sun8i-a33.dtsi
View File

@ -189,8 +189,8 @@ sound: sound {
simple-audio-card,mclk-fs = <128>;
simple-audio-card,aux-devs = <&codec_analog>;
simple-audio-card,routing =
"Left DAC", "AIF1 Slot 0 Left",
"Right DAC", "AIF1 Slot 0 Right";
"Left DAC", "DACL",
"Right DAC", "DACR";
status = "disabled";
simple-audio-card,cpu {

4
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
View File

@ -164,6 +164,10 @@ axp22x: pmic@34 {
#include "axp22x.dtsi"
&ir0 {
status = "okay";
};
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;

104
arch/arm/boot/dts/sun8i-r40.dtsi
View File

@ -190,6 +190,29 @@ mixer1_out_tcon_top: endpoint {
};
};
syscon: system-control@1c00000 {
compatible = "allwinner,sun8i-r40-system-control",
"allwinner,sun4i-a10-system-control";
reg = <0x01c00000 0x30>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram_c: sram@1d00000 {
compatible = "mmio-sram";
reg = <0x01d00000 0xd0000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x01d00000 0xd0000>;
ve_sram: sram-section@0 {
compatible = "allwinner,sun8i-r40-sram-c1",
"allwinner,sun4i-a10-sram-c1";
reg = <0x000000 0x80000>;
};
};
};
nmi_intc: interrupt-controller@1c00030 {
compatible = "allwinner,sun7i-a20-sc-nmi";
interrupt-controller;
@ -198,6 +221,18 @@ nmi_intc: interrupt-controller@1c00030 {
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
dma: dma-controller@1c02000 {
compatible = "allwinner,sun8i-r40-dma",
"allwinner,sun50i-a64-dma";
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_DMA>;
dma-channels = <16>;
dma-requests = <31>;
resets = <&ccu RST_BUS_DMA>;
#dma-cells = <1>;
};
spi0: spi@1c05000 {
compatible = "allwinner,sun8i-r40-spi",
"allwinner,sun8i-h3-spi";
@ -238,6 +273,17 @@ csi0: csi@1c09000 {
status = "disabled";
};
video-codec@1c0e000 {
compatible = "allwinner,sun8i-r40-video-engine";
reg = <0x01c0e000 0x1000>;
clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
<&ccu CLK_DRAM_VE>;
clock-names = "ahb", "mod", "ram";
resets = <&ccu RST_BUS_VE>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
allwinner,sram = <&ve_sram 1>;
};
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun8i-r40-mmc",
"allwinner,sun50i-a64-mmc";
@ -501,6 +547,16 @@ i2c4_pins: i2c4-pins {
function = "i2c4";
};
ir0_pins: ir0-pins {
pins = "PB4";
function = "ir0";
};
ir1_pins: ir1-pins {
pins = "PB23";
function = "ir1";
};
mmc0_pins: mmc0-pins {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
@ -579,6 +635,32 @@ wdt: watchdog@1c20c90 {
clocks = <&osc24M>;
};
ir0: ir@1c21800 {
compatible = "allwinner,sun8i-r40-ir",
"allwinner,sun6i-a31-ir";
reg = <0x01c21800 0x400>;
pinctrl-0 = <&ir0_pins>;
pinctrl-names = "default";
clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
clock-names = "apb", "ir";
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ccu RST_BUS_IR0>;
status = "disabled";
};
ir1: ir@1c21c00 {
compatible = "allwinner,sun8i-r40-ir",
"allwinner,sun6i-a31-ir";
reg = <0x01c21c00 0x400>;
pinctrl-0 = <&ir1_pins>;
pinctrl-names = "default";
clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
clock-names = "apb", "ir";
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
resets = <&ccu RST_BUS_IR1>;
status = "disabled";
};
ths: thermal-sensor@1c24c00 {
compatible = "allwinner,sun8i-r40-ths";
reg = <0x01c24c00 0x100>;
@ -743,6 +825,28 @@ i2c4: i2c@1c2c000 {
#size-cells = <0>;
};
mali: gpu@1c40000 {
compatible = "allwinner,sun8i-r40-mali", "arm,mali-400";
reg = <0x01c40000 0x10000>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
"pp0",
"ppmmu0",
"pp1",
"ppmmu1",
"pmu";
clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
clock-names = "bus", "core";
resets = <&ccu RST_BUS_GPU>;
};
gmac: ethernet@1c50000 {
compatible = "allwinner,sun8i-r40-gmac";
syscon = <&ccu>;

11
arch/arm/boot/dts/sun8i-v3s.dtsi
View File

@ -234,6 +234,17 @@ mmc2: mmc@1c11000 {
#size-cells = <0>;
};
crypto@1c15000 {
compatible = "allwinner,sun8i-v3s-crypto",
"allwinner,sun8i-a33-crypto";
reg = <0x01c15000 0x1000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
clock-names = "ahb", "mod";
resets = <&ccu RST_BUS_CE>;
reset-names = "ahb";
};
usb_otg: usb@1c19000 {
compatible = "allwinner,sun8i-h3-musb";
reg = <0x01c19000 0x0400>;

1
arch/arm64/boot/dts/allwinner/Makefile
View File

@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-emlid-neutis-n5-devboard.dtb

180
arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts Normal file
View File

@ -0,0 +1,180 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
*/
/dts-v1/;
#include "sun50i-a100.dtsi"
/{
model = "Allwinner A100 Perf1";
compatible = "allwinner,a100-perf1", "allwinner,sun50i-a100";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&pio {
vcc-pb-supply = <&reg_dcdc1>;
vcc-pc-supply = <&reg_eldo1>;
vcc-pd-supply = <&reg_dcdc1>;
vcc-pe-supply = <&reg_dldo2>;
vcc-pf-supply = <&reg_dcdc1>;
vcc-pg-supply = <&reg_dldo1>;
vcc-ph-supply = <&reg_dcdc1>;
};
&r_pio {
/*
* FIXME: We can't add that supply for now since it would
* create a circular dependency between pinctrl, the regulator
* and the RSB Bus.
*
* vcc-pl-supply = <&reg_aldo3>;
*/
};
&r_i2c0 {
status = "okay";
axp803: pmic@34 {
compatible = "x-powers,axp803";
reg = <0x34>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
};
};
#include "axp803.dtsi"
&ac_power_supply {
status = "okay";
};
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-pll-avcc";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-dram-1";
};
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-usb-pl";
};
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-io-usb-pd-emmc-nand-card";
};
&reg_dcdc2 {
regulator-always-on;
/*
* FIXME: update min and max before support dvfs.
*/
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1300000>;
regulator-name = "vdd-cpux";
};
/* DCDC3 is polyphased with DCDC2 */
&reg_dcdc4 {
regulator-always-on;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <950000>;
regulator-name = "vdd-sys-usb-dram";
};
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc-dram-2";
};
&reg_dldo1 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-pg-dcxo-wifi";
};
&reg_dldo2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vcc-pe-csi";
};
&reg_dldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "ldo-avdd-csi";
};
&reg_dldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "avcc-csi";
};
&reg_eldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-pc-lvds-csi-efuse-emmc-nand";
};
&reg_eldo2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dvdd-csi";
};
&reg_eldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-mipi-lcd";
};
&reg_fldo1 {
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdd-cpus-usb";
};
&reg_ldo_io0 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-ctp";
status = "okay";
};
&reg_drivevbus {
regulator-name = "usb0-vbus";
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};

364
arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi Normal file
View File

@ -0,0 +1,364 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun50i-a100-ccu.h>
#include <dt-bindings/clock/sun50i-a100-r-ccu.h>
#include <dt-bindings/reset/sun50i-a100-ccu.h>
#include <dt-bindings/reset/sun50i-a100-r-ccu.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0>;
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x1>;
enable-method = "psci";
};
cpu@2 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x2>;
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x3>;
enable-method = "psci";
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
dcxo24M: dcxo24M-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "dcxo24M";
#clock-cells = <0>;
};
iosc: internal-osc-clk {
compatible = "fixed-clock";
clock-frequency = <16000000>;
clock-accuracy = <300000000>;
clock-output-names = "iosc";
#clock-cells = <0>;
};
osc32k: osc32k-clk {
compatible = "fixed-clock";
clock-frequency = <32768>;
clock-output-names = "osc32k";
#clock-cells = <0>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x3fffffff>;
ccu: clock@3001000 {
compatible = "allwinner,sun50i-a100-ccu";
reg = <0x03001000 0x1000>;
clocks = <&dcxo24M>, <&osc32k>, <&iosc>;
clock-names = "hosc", "losc", "iosc";
#clock-cells = <1>;
#reset-cells = <1>;
};
gic: interrupt-controller@3021000 {
compatible = "arm,gic-400";
reg = <0x03021000 0x1000>, <0x03022000 0x2000>,
<0x03024000 0x2000>, <0x03026000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
interrupt-controller;
#interrupt-cells = <3>;
};
efuse@3006000 {
compatible = "allwinner,sun50i-a100-sid",
"allwinner,sun50i-a64-sid";
reg = <0x03006000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ths_calibration: calib@14 {
reg = <0x14 8>;
};
};
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-a100-pinctrl";
reg = <0x0300b000 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
uart0_pb_pins: uart0-pb-pins {
pins = "PB9", "PB10";
function = "uart0";
};
};
uart0: serial@5000000 {
compatible = "snps,dw-apb-uart";
reg = <0x05000000 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
uart1: serial@5000400 {
compatible = "snps,dw-apb-uart";
reg = <0x05000400 0x400>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
uart2: serial@5000800 {
compatible = "snps,dw-apb-uart";
reg = <0x05000800 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
uart3: serial@5000c00 {
compatible = "snps,dw-apb-uart";
reg = <0x05000c00 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART3>;
resets = <&ccu RST_BUS_UART3>;
status = "disabled";
};
uart4: serial@5001000 {
compatible = "snps,dw-apb-uart";
reg = <0x05001000 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART4>;
resets = <&ccu RST_BUS_UART4>;
status = "disabled";
};
i2c0: i2c@5002000 {
compatible = "allwinner,sun50i-a100-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002000 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@5002400 {
compatible = "allwinner,sun50i-a100-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002400 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@5002800 {
compatible = "allwinner,sun50i-a100-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002800 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c3: i2c@5002c00 {
compatible = "allwinner,sun50i-a100-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x05002c00 0x400>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C3>;
resets = <&ccu RST_BUS_I2C3>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
ths: thermal-sensor@5070400 {
compatible = "allwinner,sun50i-a100-ths";
reg = <0x05070400 0x100>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_THS>;
clock-names = "bus";
resets = <&ccu RST_BUS_THS>;
nvmem-cells = <&ths_calibration>;
nvmem-cell-names = "calibration";
#thermal-sensor-cells = <1>;
};
r_ccu: clock@7010000 {
compatible = "allwinner,sun50i-a100-r-ccu";
reg = <0x07010000 0x300>;
clocks = <&dcxo24M>, <&osc32k>, <&iosc>,
<&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
#reset-cells = <1>;
};
r_intc: interrupt-controller@7010320 {
compatible = "allwinner,sun50i-a100-nmi",
"allwinner,sun9i-a80-nmi";
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x07010320 0xc>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
};
r_pio: pinctrl@7022000 {
compatible = "allwinner,sun50i-a100-r-pinctrl";
reg = <0x07022000 0x400>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
#interrupt-cells = <3>;
r_i2c0_pins: r-i2c0-pins {
pins = "PL0", "PL1";
function = "s_i2c0";
};
r_i2c1_pins: r-i2c1-pins {
pins = "PL8", "PL9";
function = "s_i2c1";
};
};
r_uart: serial@7080000 {
compatible = "snps,dw-apb-uart";
reg = <0x07080000 0x400>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&r_ccu CLK_R_APB2_UART>;
resets = <&r_ccu RST_R_APB2_UART>;
status = "disabled";
};
r_i2c0: i2c@7081400 {
compatible = "allwinner,sun50i-a100-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x07081400 0x400>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB2_I2C0>;
resets = <&r_ccu RST_R_APB2_I2C0>;
pinctrl-names = "default";
pinctrl-0 = <&r_i2c0_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
r_i2c1: i2c@7081800 {
compatible = "allwinner,sun50i-a100-i2c",
"allwinner,sun6i-a31-i2c";
reg = <0x07081800 0x400>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_R_APB2_I2C1>;
resets = <&r_ccu RST_R_APB2_I2C1>;
pinctrl-names = "default";
pinctrl-0 = <&r_i2c1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
thermal-zones {
cpu-thermal-zone {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 0>;
};
ddr-thermal-zone {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 2>;
};
gpu-thermal-zone {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&ths 1>;
};
};
};

8
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
View File

@ -331,10 +331,10 @@ &sound {
"Microphone", "Microphone Jack",
"Microphone", "Onboard Microphone";
simple-audio-card,routing =
"Left DAC", "AIF1 Slot 0 Left",
"Right DAC", "AIF1 Slot 0 Right",
"AIF1 Slot 0 Left ADC", "Left ADC",
"AIF1 Slot 0 Right ADC", "Right ADC",
"Left DAC", "DACL",
"Right DAC", "DACR",
"ADCL", "Left ADC",
"ADCR", "Right ADC",
"Headphone Jack", "HP",
"MIC2", "Microphone Jack",
"Onboard Microphone", "MBIAS",

8
arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
View File

@ -330,10 +330,10 @@ &sound {
"Microphone", "Microphone Jack",
"Microphone", "Onboard Microphone";
simple-audio-card,routing =
"Left DAC", "AIF1 Slot 0 Left",
"Right DAC", "AIF1 Slot 0 Right",
"AIF1 Slot 0 Left ADC", "Left ADC",
"AIF1 Slot 0 Right ADC", "Right ADC",
"Left DAC", "DACL",
"Right DAC", "DACR",
"ADCL", "Left ADC",
"ADCR", "Right ADC",
"Headphone Jack", "HP",
"MIC2", "Microphone Jack",
"Onboard Microphone", "MBIAS",

8
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
View File

@ -261,11 +261,11 @@ &sound {
simple-audio-card,widgets = "Microphone", "Microphone Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Left DAC", "AIF1 Slot 0 Left",
"Right DAC", "AIF1 Slot 0 Right",
"Left DAC", "DACL",
"Right DAC", "DACR",
"Headphone Jack", "HP",
"AIF1 Slot 0 Left ADC", "Left ADC",
"AIF1 Slot 0 Right ADC", "Right ADC",
"ADCL", "Left ADC",
"ADCR", "Right ADC",
"MIC2", "Microphone Jack";
status = "okay";
};

8
arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
View File

@ -374,15 +374,15 @@ &sound {
"Headphone", "Headphone Jack",
"Speaker", "Internal Speaker";
simple-audio-card,routing =
"Left DAC", "AIF1 Slot 0 Left",
"Right DAC", "AIF1 Slot 0 Right",
"Left DAC", "DACL",
"Right DAC", "DACR",
"Speaker Amp INL", "LINEOUT",
"Speaker Amp INR", "LINEOUT",
"Internal Speaker", "Speaker Amp OUTL",
"Internal Speaker", "Speaker Amp OUTR",
"Headphone Jack", "HP",
"AIF1 Slot 0 Left ADC", "Left ADC",
"AIF1 Slot 0 Right ADC", "Right ADC",
"ADCL", "Left ADC",
"ADCR", "Right ADC",
"Internal Microphone Left", "MBIAS",
"MIC1", "Internal Microphone Left",
"Internal Microphone Right", "HBIAS",

8
arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
View File

@ -392,10 +392,10 @@ &sound {
"Internal Speaker", "Speaker Amp OUTR",
"Speaker Amp INL", "LINEOUT",
"Speaker Amp INR", "LINEOUT",
"Left DAC", "AIF1 Slot 0 Left",
"Right DAC", "AIF1 Slot 0 Right",
"AIF1 Slot 0 Left ADC", "Left ADC",
"AIF1 Slot 0 Right ADC", "Right ADC",
"Left DAC", "DACL",
"Right DAC", "DACR",
"ADCL", "Left ADC",
"ADCR", "Right ADC",
"Internal Microphone", "MBIAS",
"MIC1", "Internal Microphone",
"Headset Microphone", "HBIAS",

8
arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
View File

@ -421,15 +421,15 @@ &sound {
"Headphone", "Headphone Jack",
"Speaker", "Internal Speaker";
simple-audio-card,routing =
"Left DAC", "AIF1 Slot 0 Left",
"Right DAC", "AIF1 Slot 0 Right",
"Left DAC", "DACL",
"Right DAC", "DACR",
"Speaker Amp INL", "LINEOUT",
"Speaker Amp INR", "LINEOUT",
"Internal Speaker", "Speaker Amp OUTL",
"Internal Speaker", "Speaker Amp OUTR",
"Headphone Jack", "HP",
"AIF1 Slot 0 Left ADC", "Left ADC",
"AIF1 Slot 0 Right ADC", "Right ADC",
"ADCL", "Left ADC",
"ADCR", "Right ADC",
"Internal Microphone Left", "MBIAS",
"MIC1", "Internal Microphone Left",
"Internal Microphone Right", "HBIAS",

8
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
View File

@ -159,11 +159,11 @@ &sound {
simple-audio-card,widgets = "Microphone", "Microphone Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Left DAC", "AIF1 Slot 0 Left",
"Right DAC", "AIF1 Slot 0 Right",
"Left DAC", "DACL",
"Right DAC", "DACR",
"Headphone Jack", "HP",
"AIF1 Slot 0 Left ADC", "Left ADC",
"AIF1 Slot 0 Right ADC", "Right ADC",
"ADCL", "Left ADC",
"ADCR", "Right ADC",
"MIC2", "Microphone Jack";
status = "okay";
};

8
arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
View File

@ -340,10 +340,10 @@ &sound {
"Microphone", "Internal Microphone",
"Speaker", "Internal Speaker";
simple-audio-card,routing =
"Left DAC", "AIF1 Slot 0 Left",
"Right DAC", "AIF1 Slot 0 Right",
"AIF1 Slot 0 Left ADC", "Left ADC",
"AIF1 Slot 0 Right ADC", "Right ADC",
"Left DAC", "DACL",
"Right DAC", "DACR",
"ADCL", "Left ADC",
"ADCR", "Right ADC",
"Headphone Jack", "HP",
"Speaker Amp INL", "LINEOUT",
"Speaker Amp INR", "LINEOUT",

20
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View File

@ -51,7 +51,7 @@ cpu0: cpu@0 {
reg = <0>;
enable-method = "psci";
next-level-cache = <&L2>;
clocks = <&ccu 21>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
};
@ -62,7 +62,7 @@ cpu1: cpu@1 {
reg = <1>;
enable-method = "psci";
next-level-cache = <&L2>;
clocks = <&ccu 21>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
};
@ -73,7 +73,7 @@ cpu2: cpu@2 {
reg = <2>;
enable-method = "psci";
next-level-cache = <&L2>;
clocks = <&ccu 21>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
};
@ -84,7 +84,7 @@ cpu3: cpu@3 {
reg = <3>;
enable-method = "psci";
next-level-cache = <&L2>;
clocks = <&ccu 21>;
clocks = <&ccu CLK_CPUX>;
clock-names = "cpu";
#cooling-cells = <2>;
};
@ -139,10 +139,10 @@ sound: sound {
simple-audio-card,mclk-fs = <128>;
simple-audio-card,aux-devs = <&codec_analog>;
simple-audio-card,routing =
"Left DAC", "AIF1 Slot 0 Left",
"Right DAC", "AIF1 Slot 0 Right",
"AIF1 Slot 0 Left ADC", "Left ADC",
"AIF1 Slot 0 Right ADC", "Right ADC";
"Left DAC", "DACL",
"Right DAC", "DACR",
"ADCL", "Left ADC",
"ADCR", "Right ADC";
status = "disabled";
cpudai: simple-audio-card,cpu {
@ -157,6 +157,7 @@ link_codec: simple-audio-card,codec {
timer {
compatible = "arm,armv8-timer";
allwinner,erratum-unknown1;
arm,no-tick-in-suspend;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14
@ -860,7 +861,8 @@ dai: dai@1c22c00 {
codec: codec@1c22e00 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun8i-a33-codec";
compatible = "allwinner,sun50i-a64-codec",
"allwinner,sun8i-a33-codec";
reg = <0x01c22e00 0x600>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;

1
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
View File

@ -67,6 +67,7 @@ psci {
timer {
compatible = "arm,armv8-timer";
arm,no-tick-in-suspend;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14

1
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
View File

@ -90,6 +90,7 @@ psci {
timer {
compatible = "arm,armv8-timer";
arm,no-tick-in-suspend;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14