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perf/x86/intel/uncore: Add BW counters for GT, IA and IO breakdown

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Linux only has support to read total DDR reads and writes. Here we
add support to enable bandwidth breakdown-GT, IA and IO. Breakdown
of BW is important to debug and optimize memory access. This can also
be used for telemetry and improving the system software.The offsets for
GT, IA and IO are added and these free running counters can be accessed
via MMIO space.

The BW breakdown can be measured using the following cmd:

  perf stat -e uncore_imc/gt_requests/,uncore_imc/ia_requests/,uncore_imc/io_requests/

             30.57 MiB  uncore_imc/gt_requests/
           1346.13 MiB  uncore_imc/ia_requests/
            190.97 MiB  uncore_imc/io_requests/

       5.984572733 seconds time elapsed

     BW/s = <gt,ia,io>_requests/time elapsed

Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20200814022234.23605-1-vaibhav.shankar@intel.com
This commit is contained in:
Vaibhav Shankar 2020-08-13 19:22:34 -07:00 committed by Ingo Molnar
parent 50f6c7dbd9
commit 24633d901e
1 changed files with 49 additions and 3 deletions
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52
arch/x86/events/intel/uncore_snb.c
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@ -390,6 +390,18 @@ static struct uncore_event_desc snb_uncore_imc_events[] = {
INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"), INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"),
INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"), INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"),
INTEL_UNCORE_EVENT_DESC(gt_requests, "event=0x03"),
INTEL_UNCORE_EVENT_DESC(gt_requests.scale, "6.103515625e-5"),
INTEL_UNCORE_EVENT_DESC(gt_requests.unit, "MiB"),
INTEL_UNCORE_EVENT_DESC(ia_requests, "event=0x04"),
INTEL_UNCORE_EVENT_DESC(ia_requests.scale, "6.103515625e-5"),
INTEL_UNCORE_EVENT_DESC(ia_requests.unit, "MiB"),
INTEL_UNCORE_EVENT_DESC(io_requests, "event=0x05"),
INTEL_UNCORE_EVENT_DESC(io_requests.scale, "6.103515625e-5"),
INTEL_UNCORE_EVENT_DESC(io_requests.unit, "MiB"),
{ /* end: all zeroes */ }, { /* end: all zeroes */ },
}; };
@ -405,13 +417,35 @@ static struct uncore_event_desc snb_uncore_imc_events[] = {
#define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054 #define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054
#define SNB_UNCORE_PCI_IMC_CTR_BASE SNB_UNCORE_PCI_IMC_DATA_READS_BASE #define SNB_UNCORE_PCI_IMC_CTR_BASE SNB_UNCORE_PCI_IMC_DATA_READS_BASE
/* BW break down- legacy counters */
#define SNB_UNCORE_PCI_IMC_GT_REQUESTS 0x3
#define SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE 0x5040
#define SNB_UNCORE_PCI_IMC_IA_REQUESTS 0x4
#define SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE 0x5044
#define SNB_UNCORE_PCI_IMC_IO_REQUESTS 0x5
#define SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE 0x5048
enum perf_snb_uncore_imc_freerunning_types { enum perf_snb_uncore_imc_freerunning_types {
SNB_PCI_UNCORE_IMC_DATA = 0, SNB_PCI_UNCORE_IMC_DATA_READS = 0,
SNB_PCI_UNCORE_IMC_DATA_WRITES,
SNB_PCI_UNCORE_IMC_GT_REQUESTS,
SNB_PCI_UNCORE_IMC_IA_REQUESTS,
SNB_PCI_UNCORE_IMC_IO_REQUESTS,
SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX, SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
}; };
static struct freerunning_counters snb_uncore_imc_freerunning[] = { static struct freerunning_counters snb_uncore_imc_freerunning[] = {
[SNB_PCI_UNCORE_IMC_DATA] = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE, 0x4, 0x0, 2, 32 }, [SNB_PCI_UNCORE_IMC_DATA_READS] = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE,
0x0, 0x0, 1, 32 },
[SNB_PCI_UNCORE_IMC_DATA_READS] = { SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE,
0x0, 0x0, 1, 32 },
[SNB_PCI_UNCORE_IMC_GT_REQUESTS] = { SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE,
0x0, 0x0, 1, 32 },
[SNB_PCI_UNCORE_IMC_IA_REQUESTS] = { SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE,
0x0, 0x0, 1, 32 },
[SNB_PCI_UNCORE_IMC_IO_REQUESTS] = { SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE,
0x0, 0x0, 1, 32 },
}; };
static struct attribute *snb_uncore_imc_formats_attr[] = { static struct attribute *snb_uncore_imc_formats_attr[] = {
@ -525,6 +559,18 @@ static int snb_uncore_imc_event_init(struct perf_event *event)
base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE; base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
idx = UNCORE_PMC_IDX_FREERUNNING; idx = UNCORE_PMC_IDX_FREERUNNING;
break; break;
case SNB_UNCORE_PCI_IMC_GT_REQUESTS:
base = SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE;
idx = UNCORE_PMC_IDX_FREERUNNING;
break;
case SNB_UNCORE_PCI_IMC_IA_REQUESTS:
base = SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE;
idx = UNCORE_PMC_IDX_FREERUNNING;
break;
case SNB_UNCORE_PCI_IMC_IO_REQUESTS:
base = SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE;
idx = UNCORE_PMC_IDX_FREERUNNING;
break;
default: default:
return -EINVAL; return -EINVAL;
} }
@ -598,7 +644,7 @@ static struct intel_uncore_ops snb_uncore_imc_ops = {
static struct intel_uncore_type snb_uncore_imc = { static struct intel_uncore_type snb_uncore_imc = {
.name = "imc", .name = "imc",
.num_counters = 2, .num_counters = 5,
.num_boxes = 1, .num_boxes = 1,
.num_freerunning_types = SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX, .num_freerunning_types = SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
.mmio_map_size = SNB_UNCORE_PCI_IMC_MAP_SIZE, .mmio_map_size = SNB_UNCORE_PCI_IMC_MAP_SIZE,