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ath9k: add TX power per-rate tables
Add TX power per-rate tables for different MIMO modes (e.g STBC) in order to cap the maximum TX power value per-rate in the TX descriptor path. Cap TX power for self generated frames (ACK, RTS/CTS). Currently TPC is supported just by AR9003 based chips Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Lorenzo Bianconi
John W. Linville
parent
4f3fff1486
commit
23f53dd306
@ -4377,6 +4377,25 @@ static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
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targetPowerArray, numPiers);
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}
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static void ar9003_hw_selfgen_tpc_txpower(struct ath_hw *ah,
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struct ath9k_channel *chan,
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u8 *pwr_array)
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{
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u32 val;
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/* target power values for self generated frames (ACK,RTS/CTS) */
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if (IS_CHAN_2GHZ(chan)) {
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val = SM(pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_ACK) |
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SM(pwr_array[ALL_TARGET_LEGACY_1L_5L], AR_TPC_CTS) |
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SM(0x3f, AR_TPC_CHIRP) | SM(0x3f, AR_TPC_RPT);
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} else {
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val = SM(pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_ACK) |
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SM(pwr_array[ALL_TARGET_LEGACY_6_24], AR_TPC_CTS) |
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SM(0x3f, AR_TPC_CHIRP) | SM(0x3f, AR_TPC_RPT);
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}
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REG_WRITE(ah, AR_TPC, val);
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}
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/* Set tx power registers to array of values passed in */
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static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
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{
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@ -5312,6 +5331,7 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
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struct ar9300_modal_eep_header *modal_hdr;
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u8 targetPowerValT2[ar9300RateSize];
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u8 target_power_val_t2_eep[ar9300RateSize];
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u8 targetPowerValT2_tpc[ar9300RateSize];
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unsigned int i = 0, paprd_scale_factor = 0;
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u8 pwr_idx, min_pwridx = 0;
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@ -5363,6 +5383,9 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
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twiceAntennaReduction,
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powerLimit);
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memcpy(targetPowerValT2_tpc, targetPowerValT2,
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sizeof(targetPowerValT2));
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if (ar9003_is_paprd_enabled(ah)) {
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for (i = 0; i < ar9300RateSize; i++) {
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if ((ah->paprd_ratemask & (1 << i)) &&
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@ -5396,6 +5419,30 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
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ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
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ar9003_hw_calibration_apply(ah, chan->channel);
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ar9003_paprd_set_txpower(ah, chan, targetPowerValT2);
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ar9003_hw_selfgen_tpc_txpower(ah, chan, targetPowerValT2);
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/* TPC initializations */
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if (ah->tpc_enabled) {
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u32 val;
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ar9003_hw_init_rate_txpower(ah, targetPowerValT2_tpc, chan);
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/* Enable TPC */
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REG_WRITE(ah, AR_PHY_PWRTX_MAX,
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AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE);
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/* Disable per chain power reduction */
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val = REG_READ(ah, AR_PHY_POWER_TX_SUB);
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if (AR_SREV_9340(ah))
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REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
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val & 0xFFFFFFC0);
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else
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REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
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val & 0xFFFFF000);
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} else {
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/* Disable TPC */
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REG_WRITE(ah, AR_PHY_PWRTX_MAX, 0);
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}
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}
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static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
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@ -18,6 +18,21 @@
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#include "hw.h"
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#include "ar9003_phy.h"
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#define AR9300_OFDM_RATES 8
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#define AR9300_HT_SS_RATES 8
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#define AR9300_HT_DS_RATES 8
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#define AR9300_HT_TS_RATES 8
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#define AR9300_11NA_OFDM_SHIFT 0
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#define AR9300_11NA_HT_SS_SHIFT 8
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#define AR9300_11NA_HT_DS_SHIFT 16
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#define AR9300_11NA_HT_TS_SHIFT 24
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#define AR9300_11NG_OFDM_SHIFT 4
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#define AR9300_11NG_HT_SS_SHIFT 12
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#define AR9300_11NG_HT_DS_SHIFT 20
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#define AR9300_11NG_HT_TS_SHIFT 28
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static const int firstep_table[] =
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/* level: 0 1 2 3 4 5 6 7 8 */
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{ -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
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@ -40,6 +55,71 @@ static const int m2ThreshLowExt_off = 127;
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static const int m1ThreshExt_off = 127;
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static const int m2ThreshExt_off = 127;
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static const u8 ofdm2pwr[] = {
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ALL_TARGET_LEGACY_6_24,
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ALL_TARGET_LEGACY_6_24,
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ALL_TARGET_LEGACY_6_24,
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ALL_TARGET_LEGACY_6_24,
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ALL_TARGET_LEGACY_6_24,
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ALL_TARGET_LEGACY_36,
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ALL_TARGET_LEGACY_48,
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ALL_TARGET_LEGACY_54
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};
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static const u8 mcs2pwr_ht20[] = {
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ALL_TARGET_HT20_0_8_16,
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ALL_TARGET_HT20_1_3_9_11_17_19,
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ALL_TARGET_HT20_1_3_9_11_17_19,
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ALL_TARGET_HT20_1_3_9_11_17_19,
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ALL_TARGET_HT20_4,
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ALL_TARGET_HT20_5,
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ALL_TARGET_HT20_6,
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ALL_TARGET_HT20_7,
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ALL_TARGET_HT20_0_8_16,
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ALL_TARGET_HT20_1_3_9_11_17_19,
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ALL_TARGET_HT20_1_3_9_11_17_19,
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ALL_TARGET_HT20_1_3_9_11_17_19,
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ALL_TARGET_HT20_12,
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ALL_TARGET_HT20_13,
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ALL_TARGET_HT20_14,
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ALL_TARGET_HT20_15,
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ALL_TARGET_HT20_0_8_16,
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ALL_TARGET_HT20_1_3_9_11_17_19,
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ALL_TARGET_HT20_1_3_9_11_17_19,
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ALL_TARGET_HT20_1_3_9_11_17_19,
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ALL_TARGET_HT20_20,
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ALL_TARGET_HT20_21,
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ALL_TARGET_HT20_22,
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ALL_TARGET_HT20_23
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};
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static const u8 mcs2pwr_ht40[] = {
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ALL_TARGET_HT40_0_8_16,
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ALL_TARGET_HT40_1_3_9_11_17_19,
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ALL_TARGET_HT40_1_3_9_11_17_19,
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ALL_TARGET_HT40_1_3_9_11_17_19,
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ALL_TARGET_HT40_4,
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ALL_TARGET_HT40_5,
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ALL_TARGET_HT40_6,
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ALL_TARGET_HT40_7,
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ALL_TARGET_HT40_0_8_16,
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ALL_TARGET_HT40_1_3_9_11_17_19,
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ALL_TARGET_HT40_1_3_9_11_17_19,
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ALL_TARGET_HT40_1_3_9_11_17_19,
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ALL_TARGET_HT40_12,
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ALL_TARGET_HT40_13,
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ALL_TARGET_HT40_14,
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ALL_TARGET_HT40_15,
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ALL_TARGET_HT40_0_8_16,
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ALL_TARGET_HT40_1_3_9_11_17_19,
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ALL_TARGET_HT40_1_3_9_11_17_19,
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ALL_TARGET_HT40_1_3_9_11_17_19,
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ALL_TARGET_HT40_20,
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ALL_TARGET_HT40_21,
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ALL_TARGET_HT40_22,
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ALL_TARGET_HT40_23,
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};
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/**
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* ar9003_hw_set_channel - set channel on single-chip device
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* @ah: atheros hardware structure
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@ -1799,6 +1879,100 @@ static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
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ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14], 0));
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}
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static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array)
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{
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ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L];
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ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L];
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ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L],
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rate_array[ALL_TARGET_LEGACY_5S]);
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ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L],
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rate_array[ALL_TARGET_LEGACY_11S]);
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}
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static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array,
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int offset)
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{
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int i, j;
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for (i = offset; i < offset + AR9300_OFDM_RATES; i++) {
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/* OFDM rate to power table idx */
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j = ofdm2pwr[i - offset];
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ah->tx_power[i] = rate_array[j];
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}
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}
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static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array,
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int ss_offset, int ds_offset,
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int ts_offset, bool is_40)
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{
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int i, j, mcs_idx = 0;
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const u8 *mcs2pwr = (is_40) ? mcs2pwr_ht40 : mcs2pwr_ht20;
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for (i = ss_offset; i < ss_offset + AR9300_HT_SS_RATES; i++) {
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j = mcs2pwr[mcs_idx];
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ah->tx_power[i] = rate_array[j];
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mcs_idx++;
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}
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for (i = ds_offset; i < ds_offset + AR9300_HT_DS_RATES; i++) {
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j = mcs2pwr[mcs_idx];
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ah->tx_power[i] = rate_array[j];
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mcs_idx++;
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}
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for (i = ts_offset; i < ts_offset + AR9300_HT_TS_RATES; i++) {
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j = mcs2pwr[mcs_idx];
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ah->tx_power[i] = rate_array[j];
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mcs_idx++;
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}
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}
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static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset,
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int ds_offset, int ts_offset)
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{
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memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset],
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AR9300_HT_SS_RATES);
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memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset],
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AR9300_HT_DS_RATES);
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memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset],
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AR9300_HT_TS_RATES);
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}
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void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
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struct ath9k_channel *chan)
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{
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if (IS_CHAN_5GHZ(chan)) {
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ar9003_hw_init_txpower_ofdm(ah, rate_array,
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AR9300_11NA_OFDM_SHIFT);
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if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
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ar9003_hw_init_txpower_ht(ah, rate_array,
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AR9300_11NA_HT_SS_SHIFT,
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AR9300_11NA_HT_DS_SHIFT,
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AR9300_11NA_HT_TS_SHIFT,
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IS_CHAN_HT40(chan));
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ar9003_hw_init_txpower_stbc(ah,
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AR9300_11NA_HT_SS_SHIFT,
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AR9300_11NA_HT_DS_SHIFT,
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AR9300_11NA_HT_TS_SHIFT);
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}
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} else {
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ar9003_hw_init_txpower_cck(ah, rate_array);
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ar9003_hw_init_txpower_ofdm(ah, rate_array,
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AR9300_11NG_OFDM_SHIFT);
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if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
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ar9003_hw_init_txpower_ht(ah, rate_array,
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AR9300_11NG_HT_SS_SHIFT,
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AR9300_11NG_HT_DS_SHIFT,
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AR9300_11NG_HT_TS_SHIFT,
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IS_CHAN_HT40(chan));
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ar9003_hw_init_txpower_stbc(ah,
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AR9300_11NG_HT_SS_SHIFT,
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AR9300_11NG_HT_DS_SHIFT,
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AR9300_11NG_HT_TS_SHIFT);
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}
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}
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}
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void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
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{
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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@ -940,6 +940,10 @@ struct ath_hw {
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const struct firmware *eeprom_blob;
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struct ath_dynack dynack;
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bool tpc_enabled;
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u8 tx_power[Ar5416RateSize];
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u8 tx_power_stbc[Ar5416RateSize];
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};
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struct ath_bus_ops {
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@ -1080,6 +1084,8 @@ int ar9003_paprd_init_table(struct ath_hw *ah);
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bool ar9003_paprd_is_done(struct ath_hw *ah);
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bool ar9003_is_paprd_enabled(struct ath_hw *ah);
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void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
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void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
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struct ath9k_channel *chan);
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/* Hardware family op attach helpers */
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int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
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@ -1724,6 +1724,8 @@ enum {
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#define AR_TPC_CTS_S 8
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#define AR_TPC_CHIRP 0x003f0000
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#define AR_TPC_CHIRP_S 16
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#define AR_TPC_RPT 0x3f000000
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#define AR_TPC_RPT_S 24
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#define AR_QUIET1 0x80fc
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#define AR_QUIET1_NEXT_QUIET_S 0
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