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net: aquantia: add rx-flow filter definitions
Add missing register definitions and the functions accessing them related to rx-flow filters. Signed-off-by: Dmitry Bogdanov <dmitry.bogdanov@aquantia.com> Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Dmitry Bogdanov
David S. Miller
parent
4fd3e2ac18
commit
23e7a718a4
@ -898,6 +898,24 @@ void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
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vlan_id_flr);
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}
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void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq_en,
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u32 filter)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter),
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HW_ATL_RPF_VL_RXQ_EN_F_MSK,
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HW_ATL_RPF_VL_RXQ_EN_F_SHIFT,
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vlan_rxq_en);
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}
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void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq,
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u32 filter)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_VL_RXQ_F_ADR(filter),
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HW_ATL_RPF_VL_RXQ_F_MSK,
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HW_ATL_RPF_VL_RXQ_F_SHIFT,
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vlan_rxq);
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};
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void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
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u32 filter)
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{
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@ -965,6 +983,20 @@ void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter)
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HW_ATL_RPF_ET_VALF_SHIFT, etht_flr);
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}
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void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_SPD_ADR(filter),
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HW_ATL_RPF_L4_SPD_MSK,
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HW_ATL_RPF_L4_SPD_SHIFT, val);
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}
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void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter)
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{
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aq_hw_write_reg_bit(aq_hw, HW_ATL_RPF_L4_DPD_ADR(filter),
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HW_ATL_RPF_L4_DPD_MSK,
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HW_ATL_RPF_L4_DPD_SHIFT, val);
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}
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/* RPO: rx packet offload */
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void hw_atl_rpo_ipv4header_crc_offload_en_set(struct aq_hw_s *aq_hw,
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u32 ipv4header_crc_offload_en)
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@ -1476,3 +1508,80 @@ void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr)
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HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT,
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up_force_intr);
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}
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void hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
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{
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aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location), 0U);
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}
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void hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
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{
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aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_SRCA_ADR(location), 0U);
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}
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void hw_atl_rpfl3l4_cmd_clear(struct aq_hw_s *aq_hw, u8 location)
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{
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aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), 0U);
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}
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void hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location)
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{
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int i;
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for (i = 0; i < 4; ++i)
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aq_hw_write_reg(aq_hw,
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HW_ATL_RPF_L3_DSTA_ADR(location + i),
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0U);
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}
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void hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw_s *aq_hw, u8 location)
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{
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int i;
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for (i = 0; i < 4; ++i)
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aq_hw_write_reg(aq_hw,
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HW_ATL_RPF_L3_SRCA_ADR(location + i),
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0U);
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}
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void hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
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u32 ipv4_dest)
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{
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aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_DSTA_ADR(location),
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ipv4_dest);
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}
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void hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
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u32 ipv4_src)
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{
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aq_hw_write_reg(aq_hw,
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HW_ATL_RPF_L3_SRCA_ADR(location),
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ipv4_src);
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}
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void hw_atl_rpfl3l4_cmd_set(struct aq_hw_s *aq_hw, u8 location, u32 cmd)
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{
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aq_hw_write_reg(aq_hw, HW_ATL_RPF_L3_REG_CTRL_ADR(location), cmd);
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}
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void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
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u32 *ipv6_src)
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{
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int i;
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for (i = 0; i < 4; ++i)
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aq_hw_write_reg(aq_hw,
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HW_ATL_RPF_L3_SRCA_ADR(location + i),
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ipv6_src[i]);
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}
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void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
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u32 *ipv6_dest)
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{
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int i;
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for (i = 0; i < 4; ++i)
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aq_hw_write_reg(aq_hw,
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HW_ATL_RPF_L3_DSTA_ADR(location + i),
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ipv6_dest[i]);
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}
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@ -441,6 +441,14 @@ void hw_atl_rpf_vlan_flr_act_set(struct aq_hw_s *aq_hw, u32 vlan_filter_act,
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void hw_atl_rpf_vlan_id_flr_set(struct aq_hw_s *aq_hw, u32 vlan_id_flr,
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u32 filter);
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/* Set VLAN RX queue assignment enable */
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void hw_atl_rpf_vlan_rxq_en_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq_en,
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u32 filter);
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/* Set VLAN RX queue */
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void hw_atl_rpf_vlan_rxq_flr_set(struct aq_hw_s *aq_hw, u32 vlan_rxq,
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u32 filter);
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/* set ethertype filter enable */
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void hw_atl_rpf_etht_flr_en_set(struct aq_hw_s *aq_hw, u32 etht_flr_en,
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u32 filter);
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@ -475,6 +483,12 @@ void hw_atl_rpf_etht_flr_act_set(struct aq_hw_s *aq_hw, u32 etht_flr_act,
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/* set ethertype filter */
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void hw_atl_rpf_etht_flr_set(struct aq_hw_s *aq_hw, u32 etht_flr, u32 filter);
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/* set L4 source port */
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void hw_atl_rpf_l4_spd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter);
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/* set L4 destination port */
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void hw_atl_rpf_l4_dpd_set(struct aq_hw_s *aq_hw, u32 val, u32 filter);
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/* rpo */
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/* set ipv4 header checksum offload enable */
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@ -704,4 +718,38 @@ void hw_atl_pci_pci_reg_res_dis_set(struct aq_hw_s *aq_hw, u32 pci_reg_res_dis);
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/* set uP Force Interrupt */
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void hw_atl_mcp_up_force_intr_set(struct aq_hw_s *aq_hw, u32 up_force_intr);
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/* clear ipv4 filter destination address */
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void hw_atl_rpfl3l4_ipv4_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location);
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/* clear ipv4 filter source address */
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void hw_atl_rpfl3l4_ipv4_src_addr_clear(struct aq_hw_s *aq_hw, u8 location);
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/* clear command for filter l3-l4 */
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void hw_atl_rpfl3l4_cmd_clear(struct aq_hw_s *aq_hw, u8 location);
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/* clear ipv6 filter destination address */
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void hw_atl_rpfl3l4_ipv6_dest_addr_clear(struct aq_hw_s *aq_hw, u8 location);
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/* clear ipv6 filter source address */
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void hw_atl_rpfl3l4_ipv6_src_addr_clear(struct aq_hw_s *aq_hw, u8 location);
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/* set ipv4 filter destination address */
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void hw_atl_rpfl3l4_ipv4_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
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u32 ipv4_dest);
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/* set ipv4 filter source address */
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void hw_atl_rpfl3l4_ipv4_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
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u32 ipv4_src);
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/* set command for filter l3-l4 */
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void hw_atl_rpfl3l4_cmd_set(struct aq_hw_s *aq_hw, u8 location, u32 cmd);
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/* set ipv6 filter source address */
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void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
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u32 *ipv6_src);
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/* set ipv6 filter destination address */
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void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
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u32 *ipv6_dest);
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#endif /* HW_ATL_LLH_H */
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@ -1092,24 +1092,43 @@
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/* Default value of bitfield vl_id{F}[B:0] */
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#define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0
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/* RX et_en{F} Bitfield Definitions
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* Preprocessor definitions for the bitfield "et_en{F}".
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/* RX vl_rxq_en{F} Bitfield Definitions
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* Preprocessor definitions for the bitfield "vl_rxq{F}".
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* Parameter: filter {F} | stride size 0x4 | range [0, 15]
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* PORT="pif_rpf_et_en_i[0]"
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* PORT="pif_rpf_vl_rxq_en_i"
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*/
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/* Register address for bitfield et_en{F} */
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#define HW_ATL_RPF_ET_EN_F_ADR(filter) (0x00005300 + (filter) * 0x4)
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/* Bitmask for bitfield et_en{F} */
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#define HW_ATL_RPF_ET_EN_F_MSK 0x80000000
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/* Inverted bitmask for bitfield et_en{F} */
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#define HW_ATL_RPF_ET_EN_F_MSKN 0x7FFFFFFF
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/* Lower bit position of bitfield et_en{F} */
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#define HW_ATL_RPF_ET_EN_F_SHIFT 31
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/* Width of bitfield et_en{F} */
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#define HW_ATL_RPF_ET_EN_F_WIDTH 1
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/* Default value of bitfield et_en{F} */
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#define HW_ATL_RPF_ET_EN_F_DEFAULT 0x0
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/* Register address for bitfield vl_rxq_en{F} */
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#define HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4)
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/* Bitmask for bitfield vl_rxq_en{F} */
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#define HW_ATL_RPF_VL_RXQ_EN_F_MSK 0x10000000
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/* Inverted bitmask for bitfield vl_rxq_en{F}[ */
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#define HW_ATL_RPF_VL_RXQ_EN_F_MSKN 0xEFFFFFFF
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/* Lower bit position of bitfield vl_rxq_en{F} */
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#define HW_ATL_RPF_VL_RXQ_EN_F_SHIFT 28
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/* Width of bitfield vl_rxq_en{F} */
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#define HW_ATL_RPF_VL_RXQ_EN_F_WIDTH 1
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/* Default value of bitfield vl_rxq_en{F} */
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#define HW_ATL_RPF_VL_RXQ_EN_F_DEFAULT 0x0
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/* RX vl_rxq{F}[4:0] Bitfield Definitions
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* Preprocessor definitions for the bitfield "vl_rxq{F}[4:0]".
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* Parameter: filter {F} | stride size 0x4 | range [0, 15]
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* PORT="pif_rpf_vl_rxq0_i[4:0]"
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*/
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/* Register address for bitfield vl_rxq{F}[4:0] */
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#define HW_ATL_RPF_VL_RXQ_F_ADR(filter) (0x00005290 + (filter) * 0x4)
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/* Bitmask for bitfield vl_rxq{F}[4:0] */
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#define HW_ATL_RPF_VL_RXQ_F_MSK 0x01F00000
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/* Inverted bitmask for bitfield vl_rxq{F}[4:0] */
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#define HW_ATL_RPF_VL_RXQ_F_MSKN 0xFE0FFFFF
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/* Lower bit position of bitfield vl_rxq{F}[4:0] */
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#define HW_ATL_RPF_VL_RXQ_F_SHIFT 20
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/* Width of bitfield vl_rxw{F}[4:0] */
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#define HW_ATL_RPF_VL_RXQ_F_WIDTH 5
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/* Default value of bitfield vl_rxq{F}[4:0] */
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#define HW_ATL_RPF_VL_RXQ_F_DEFAULT 0x0
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/* rx et_en{f} bitfield definitions
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* preprocessor definitions for the bitfield "et_en{f}".
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@ -1263,6 +1282,44 @@
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/* default value of bitfield et_val{f}[f:0] */
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#define HW_ATL_RPF_ET_VALF_DEFAULT 0x0
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/* RX l4_sp{D}[F:0] Bitfield Definitions
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* Preprocessor definitions for the bitfield "l4_sp{D}[F:0]".
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* Parameter: srcport {D} | stride size 0x4 | range [0, 7]
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* PORT="pif_rpf_l4_sp0_i[15:0]"
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*/
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/* Register address for bitfield l4_sp{D}[F:0] */
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#define HW_ATL_RPF_L4_SPD_ADR(srcport) (0x00005400u + (srcport) * 0x4)
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/* Bitmask for bitfield l4_sp{D}[F:0] */
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#define HW_ATL_RPF_L4_SPD_MSK 0x0000FFFFu
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/* Inverted bitmask for bitfield l4_sp{D}[F:0] */
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#define HW_ATL_RPF_L4_SPD_MSKN 0xFFFF0000u
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/* Lower bit position of bitfield l4_sp{D}[F:0] */
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#define HW_ATL_RPF_L4_SPD_SHIFT 0
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/* Width of bitfield l4_sp{D}[F:0] */
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#define HW_ATL_RPF_L4_SPD_WIDTH 16
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/* Default value of bitfield l4_sp{D}[F:0] */
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#define HW_ATL_RPF_L4_SPD_DEFAULT 0x0
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/* RX l4_dp{D}[F:0] Bitfield Definitions
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* Preprocessor definitions for the bitfield "l4_dp{D}[F:0]".
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* Parameter: destport {D} | stride size 0x4 | range [0, 7]
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* PORT="pif_rpf_l4_dp0_i[15:0]"
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*/
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/* Register address for bitfield l4_dp{D}[F:0] */
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#define HW_ATL_RPF_L4_DPD_ADR(destport) (0x00005420u + (destport) * 0x4)
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/* Bitmask for bitfield l4_dp{D}[F:0] */
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#define HW_ATL_RPF_L4_DPD_MSK 0x0000FFFFu
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/* Inverted bitmask for bitfield l4_dp{D}[F:0] */
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#define HW_ATL_RPF_L4_DPD_MSKN 0xFFFF0000u
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/* Lower bit position of bitfield l4_dp{D}[F:0] */
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#define HW_ATL_RPF_L4_DPD_SHIFT 0
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/* Width of bitfield l4_dp{D}[F:0] */
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#define HW_ATL_RPF_L4_DPD_WIDTH 16
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/* Default value of bitfield l4_dp{D}[F:0] */
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#define HW_ATL_RPF_L4_DPD_DEFAULT 0x0
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/* rx ipv4_chk_en bitfield definitions
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* preprocessor definitions for the bitfield "ipv4_chk_en".
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* port="pif_rpo_ipv4_chk_en_i"
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@ -2418,4 +2475,48 @@
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/* default value of bitfield uP Force Interrupt */
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#define HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT 0x0
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#define HW_ATL_RX_CTRL_ADDR_BEGIN_FL3L4 0x00005380
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#define HW_ATL_RX_SRCA_ADDR_BEGIN_FL3L4 0x000053B0
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#define HW_ATL_RX_DESTA_ADDR_BEGIN_FL3L4 0x000053D0
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#define HW_ATL_RPF_L3_REG_CTRL_ADR(location) (0x00005380 + (location) * 0x4)
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/* RX rpf_l3_sa{D}[1F:0] Bitfield Definitions
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* Preprocessor definitions for the bitfield "l3_sa{D}[1F:0]".
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* Parameter: location {D} | stride size 0x4 | range [0, 7]
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* PORT="pif_rpf_l3_sa0_i[31:0]"
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*/
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/* Register address for bitfield pif_rpf_l3_sa0_i[31:0] */
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#define HW_ATL_RPF_L3_SRCA_ADR(location) (0x000053B0 + (location) * 0x4)
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/* Bitmask for bitfield l3_sa0[1F:0] */
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#define HW_ATL_RPF_L3_SRCA_MSK 0xFFFFFFFFu
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/* Inverted bitmask for bitfield l3_sa0[1F:0] */
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#define HW_ATL_RPF_L3_SRCA_MSKN 0xFFFFFFFFu
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/* Lower bit position of bitfield l3_sa0[1F:0] */
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#define HW_ATL_RPF_L3_SRCA_SHIFT 0
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/* Width of bitfield l3_sa0[1F:0] */
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#define HW_ATL_RPF_L3_SRCA_WIDTH 32
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/* Default value of bitfield l3_sa0[1F:0] */
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#define HW_ATL_RPF_L3_SRCA_DEFAULT 0x0
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/* RX rpf_l3_da{D}[1F:0] Bitfield Definitions
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* Preprocessor definitions for the bitfield "l3_da{D}[1F:0]".
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* Parameter: location {D} | stride size 0x4 | range [0, 7]
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* PORT="pif_rpf_l3_da0_i[31:0]"
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*/
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/* Register address for bitfield pif_rpf_l3_da0_i[31:0] */
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#define HW_ATL_RPF_L3_DSTA_ADR(location) (0x000053B0 + (location) * 0x4)
|
||||
/* Bitmask for bitfield l3_da0[1F:0] */
|
||||
#define HW_ATL_RPF_L3_DSTA_MSK 0xFFFFFFFFu
|
||||
/* Inverted bitmask for bitfield l3_da0[1F:0] */
|
||||
#define HW_ATL_RPF_L3_DSTA_MSKN 0xFFFFFFFFu
|
||||
/* Lower bit position of bitfield l3_da0[1F:0] */
|
||||
#define HW_ATL_RPF_L3_DSTA_SHIFT 0
|
||||
/* Width of bitfield l3_da0[1F:0] */
|
||||
#define HW_ATL_RPF_L3_DSTA_WIDTH 32
|
||||
/* Default value of bitfield l3_da0[1F:0] */
|
||||
#define HW_ATL_RPF_L3_DSTA_DEFAULT 0x0
|
||||
|
||||
#endif /* HW_ATL_LLH_INTERNAL_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user