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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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clocksource/drivers/sp804: Support non-standard register offset
The ARM SP804 supports a maximum of 32-bit counter, but Hisilicon extends
it to 64-bit. That means, the registers: TimerXload, TimerXValue and
TimerXBGLoad are 64bits, all other registers are the same as those in the
SP804. The driver code can be completely reused except that the register
offset is different.
Currently, we get a timer register address by: add the constant register
offset to the timer base address. e.g. "base + TIMER_CTRL". It can not be
dynamically adjusted at run time.
So create a new structure "sp804_timer" to record the original registers
offset, and create a new structure "sp804_clkevt" to record the
calculated registers address. So the "base + TIMER_CTRL" is changed to
"clkevt->ctrl", this will faster than "base + timer->ctrl".
For example:
struct sp804_timer arm_sp804_timer = {
.ctrl = TIMER_CTRL,
};
struct sp804_clkevt clkevt;
clkevt.ctrl = base + arm_sp804_timer.ctrl.
- writel(0, base + TIMER_CTRL);
+ writel(0, clkevt->ctrl);
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200918132237.3552-7-thunder.leizhen@huawei.com
This commit is contained in:
Zhen Lei
Daniel Lezcano
parent
e69aae713b
commit
23c788cd48
@ -10,6 +10,7 @@
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*
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* Every SP804 contains two identical timers.
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*/
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#define NR_TIMERS 2
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#define TIMER_1_BASE 0x00
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#define TIMER_2_BASE 0x20
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@ -29,3 +30,28 @@
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#define TIMER_RIS 0x10 /* CVR ro */
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#define TIMER_MIS 0x14 /* CVR ro */
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#define TIMER_BGLOAD 0x18 /* CVR rw */
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struct sp804_timer {
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int load;
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int value;
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int ctrl;
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int intclr;
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int ris;
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int mis;
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int bgload;
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int timer_base[NR_TIMERS];
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int width;
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};
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struct sp804_clkevt {
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void __iomem *base;
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void __iomem *load;
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void __iomem *value;
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void __iomem *ctrl;
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void __iomem *intclr;
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void __iomem *ris;
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void __iomem *mis;
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void __iomem *bgload;
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unsigned long reload;
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int width;
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};
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@ -20,6 +20,17 @@
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#include "timer-sp.h"
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struct sp804_timer __initdata arm_sp804_timer = {
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.load = TIMER_LOAD,
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.value = TIMER_VALUE,
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.ctrl = TIMER_CTRL,
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.intclr = TIMER_INTCLR,
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.timer_base = {TIMER_1_BASE, TIMER_2_BASE},
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.width = 32,
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};
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static struct sp804_clkevt sp804_clkevt[NR_TIMERS];
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static long __init sp804_get_clock_rate(struct clk *clk, const char *name)
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{
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long rate;
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@ -58,11 +69,26 @@ static long __init sp804_get_clock_rate(struct clk *clk, const char *name)
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return rate;
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}
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static void __iomem *sched_clock_base;
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static struct sp804_clkevt * __init sp804_clkevt_get(void __iomem *base)
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{
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int i;
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for (i = 0; i < NR_TIMERS; i++) {
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if (sp804_clkevt[i].base == base)
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return &sp804_clkevt[i];
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}
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/* It's impossible to reach here */
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WARN_ON(1);
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return NULL;
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}
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static struct sp804_clkevt *sched_clkevt;
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static u64 notrace sp804_read(void)
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{
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return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
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return ~readl_relaxed(sched_clkevt->value);
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}
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int __init sp804_clocksource_and_sched_clock_init(void __iomem *base,
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@ -71,22 +97,25 @@ int __init sp804_clocksource_and_sched_clock_init(void __iomem *base,
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int use_sched_clock)
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{
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long rate;
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struct sp804_clkevt *clkevt;
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rate = sp804_get_clock_rate(clk, name);
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if (rate < 0)
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return -EINVAL;
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writel(0, base + TIMER_CTRL);
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writel(0xffffffff, base + TIMER_LOAD);
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writel(0xffffffff, base + TIMER_VALUE);
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writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
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base + TIMER_CTRL);
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clkevt = sp804_clkevt_get(base);
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clocksource_mmio_init(base + TIMER_VALUE, name,
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writel(0, clkevt->ctrl);
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writel(0xffffffff, clkevt->load);
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writel(0xffffffff, clkevt->value);
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writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
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clkevt->ctrl);
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clocksource_mmio_init(clkevt->value, name,
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rate, 200, 32, clocksource_mmio_readl_down);
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if (use_sched_clock) {
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sched_clock_base = base;
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sched_clkevt = clkevt;
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sched_clock_register(sp804_read, 32, rate);
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}
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@ -94,8 +123,7 @@ int __init sp804_clocksource_and_sched_clock_init(void __iomem *base,
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}
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static void __iomem *clkevt_base;
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static unsigned long clkevt_reload;
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static struct sp804_clkevt *common_clkevt;
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/*
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* IRQ handler for the timer
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@ -105,7 +133,7 @@ static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
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struct clock_event_device *evt = dev_id;
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/* clear the interrupt */
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writel(1, clkevt_base + TIMER_INTCLR);
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writel(1, common_clkevt->intclr);
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evt->event_handler(evt);
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@ -114,7 +142,7 @@ static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
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static inline void timer_shutdown(struct clock_event_device *evt)
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{
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writel(0, clkevt_base + TIMER_CTRL);
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writel(0, common_clkevt->ctrl);
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}
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static int sp804_shutdown(struct clock_event_device *evt)
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@ -129,8 +157,8 @@ static int sp804_set_periodic(struct clock_event_device *evt)
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TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
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timer_shutdown(evt);
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writel(clkevt_reload, clkevt_base + TIMER_LOAD);
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writel(ctrl, clkevt_base + TIMER_CTRL);
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writel(common_clkevt->reload, common_clkevt->load);
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writel(ctrl, common_clkevt->ctrl);
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return 0;
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}
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@ -140,8 +168,8 @@ static int sp804_set_next_event(unsigned long next,
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unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
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TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE;
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writel(next, clkevt_base + TIMER_LOAD);
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writel(ctrl, clkevt_base + TIMER_CTRL);
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writel(next, common_clkevt->load);
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writel(ctrl, common_clkevt->ctrl);
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return 0;
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}
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@ -168,13 +196,13 @@ int __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
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if (rate < 0)
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return -EINVAL;
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clkevt_base = base;
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clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
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common_clkevt = sp804_clkevt_get(base);
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common_clkevt->reload = DIV_ROUND_CLOSEST(rate, HZ);
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evt->name = name;
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evt->irq = irq;
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evt->cpumask = cpu_possible_mask;
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writel(0, base + TIMER_CTRL);
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writel(0, common_clkevt->ctrl);
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if (request_irq(irq, sp804_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
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"timer", &sp804_clockevent))
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@ -184,7 +212,26 @@ int __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
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return 0;
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}
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static int __init sp804_of_init(struct device_node *np)
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static void __init sp804_clkevt_init(struct sp804_timer *timer, void __iomem *base)
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{
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int i;
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for (i = 0; i < NR_TIMERS; i++) {
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void __iomem *timer_base;
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struct sp804_clkevt *clkevt;
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timer_base = base + timer->timer_base[i];
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clkevt = &sp804_clkevt[i];
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clkevt->base = timer_base;
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clkevt->load = timer_base + timer->load;
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clkevt->value = timer_base + timer->value;
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clkevt->ctrl = timer_base + timer->ctrl;
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clkevt->intclr = timer_base + timer->intclr;
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clkevt->width = timer->width;
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}
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}
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static int __init sp804_of_init(struct device_node *np, struct sp804_timer *timer)
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{
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static bool initialized = false;
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void __iomem *base;
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@ -199,12 +246,12 @@ static int __init sp804_of_init(struct device_node *np)
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if (!base)
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return -ENXIO;
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timer1_base = base;
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timer2_base = base + TIMER_2_BASE;
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timer1_base = base + timer->timer_base[0];
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timer2_base = base + timer->timer_base[1];
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/* Ensure timers are disabled */
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writel(0, timer1_base + TIMER_CTRL);
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writel(0, timer2_base + TIMER_CTRL);
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writel(0, timer1_base + timer->ctrl);
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writel(0, timer2_base + timer->ctrl);
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if (initialized || !of_device_is_available(np)) {
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ret = -EINVAL;
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@ -230,6 +277,8 @@ static int __init sp804_of_init(struct device_node *np)
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if (irq <= 0)
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goto err;
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sp804_clkevt_init(timer, base);
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of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
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if (irq_num == 2) {
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@ -259,7 +308,12 @@ static int __init sp804_of_init(struct device_node *np)
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iounmap(base);
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return ret;
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}
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TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
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static int __init arm_sp804_of_init(struct device_node *np)
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{
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return sp804_of_init(np, &arm_sp804_timer);
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}
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TIMER_OF_DECLARE(sp804, "arm,sp804", arm_sp804_of_init);
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static int __init integrator_cp_of_init(struct device_node *np)
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{
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@ -282,11 +336,13 @@ static int __init integrator_cp_of_init(struct device_node *np)
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}
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/* Ensure timer is disabled */
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writel(0, base + TIMER_CTRL);
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writel(0, base + arm_sp804_timer.ctrl);
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if (init_count == 2 || !of_device_is_available(np))
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goto err;
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sp804_clkevt_init(&arm_sp804_timer, base);
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if (!init_count) {
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ret = sp804_clocksource_and_sched_clock_init(base,
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name, clk, 0);
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