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ARM: 5995/1: ARM: Add L2x0 outer_sync() support (3/4)

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The L2x0 cache controllers need to explicitly drain their write buffer
even for Normal Noncacheable memory accesses.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Catalin Marinas 2010-03-24 16:48:53 +01:00 committed by Russell King
parent 319f551a0a
commit 23107c5420
2 changed files with 11 additions and 0 deletions
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1
arch/arm/mm/Kconfig
View File

@ -763,6 +763,7 @@ config CACHE_L2X0
REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
default y default y
select OUTER_CACHE select OUTER_CACHE
select OUTER_CACHE_SYNC
help help
This option enables the L2x0 PrimeCell. This option enables the L2x0 PrimeCell.

10
arch/arm/mm/cache-l2x0.c
View File

@ -93,6 +93,15 @@ static inline void l2x0_flush_line(unsigned long addr)
} }
#endif #endif
static void l2x0_cache_sync(void)
{
unsigned long flags;
spin_lock_irqsave(&l2x0_lock, flags);
cache_sync();
spin_unlock_irqrestore(&l2x0_lock, flags);
}
static inline void l2x0_inv_all(void) static inline void l2x0_inv_all(void)
{ {
unsigned long flags; unsigned long flags;
@ -225,6 +234,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
outer_cache.inv_range = l2x0_inv_range; outer_cache.inv_range = l2x0_inv_range;
outer_cache.clean_range = l2x0_clean_range; outer_cache.clean_range = l2x0_clean_range;
outer_cache.flush_range = l2x0_flush_range; outer_cache.flush_range = l2x0_flush_range;
outer_cache.sync = l2x0_cache_sync;
printk(KERN_INFO "L2X0 cache controller enabled\n"); printk(KERN_INFO "L2X0 cache controller enabled\n");
} }