mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 01:46:40 +07:00
bnx2x: new Multi-function mode - BD
This adds support to a new multi-function mode, enabling driver to initialize such devices and correctly interacting with management FW for fully utilizing their features. Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: Ariel Elior <Ariel.Elior@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yuval Mintz
David S. Miller
parent
924c6216f8
commit
230d00eb4b
@ -1424,6 +1424,7 @@ enum {
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SUB_MF_MODE_UNKNOWN = 0,
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SUB_MF_MODE_UFP,
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SUB_MF_MODE_NPAR1_DOT_5,
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SUB_MF_MODE_BD,
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};
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struct bnx2x {
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@ -1638,6 +1639,8 @@ struct bnx2x {
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u8 mf_sub_mode;
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#define IS_MF_UFP(bp) (IS_MF_SD(bp) && \
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bp->mf_sub_mode == SUB_MF_MODE_UFP)
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#define IS_MF_BD(bp) (IS_MF_SD(bp) && \
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bp->mf_sub_mode == SUB_MF_MODE_BD)
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u8 wol;
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@ -2517,6 +2517,20 @@ static void bnx2x_bz_fp(struct bnx2x *bp, int index)
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fp->mode = TPA_MODE_DISABLED;
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}
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void bnx2x_set_os_driver_state(struct bnx2x *bp, u32 state)
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{
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u32 cur;
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if (!IS_MF_BD(bp) || !SHMEM2_HAS(bp, os_driver_state) || IS_VF(bp))
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return;
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cur = SHMEM2_RD(bp, os_driver_state[BP_FW_MB_IDX(bp)]);
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DP(NETIF_MSG_IFUP, "Driver state %08x-->%08x\n",
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cur, state);
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SHMEM2_WR(bp, os_driver_state[BP_FW_MB_IDX(bp)], state);
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}
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int bnx2x_load_cnic(struct bnx2x *bp)
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{
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int i, rc, port = BP_PORT(bp);
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@ -2880,6 +2894,8 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
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/* mark driver is loaded in shmem2 */
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u32 val;
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val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
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val &= ~DRV_FLAGS_MTU_MASK;
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val |= (bp->dev->mtu << DRV_FLAGS_MTU_SHIFT);
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SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
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val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
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DRV_FLAGS_CAPABILITIES_LOADED_L2);
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@ -2896,6 +2912,9 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
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if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG))
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bnx2x_dcbx_init(bp, false);
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if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
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bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_ACTIVE);
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DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n");
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return 0;
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@ -2963,6 +2982,9 @@ int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
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DP(NETIF_MSG_IFUP, "Starting NIC unload\n");
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if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
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bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
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/* mark driver is unloaded in shmem2 */
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if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
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u32 val;
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@ -4191,6 +4213,41 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
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return NETDEV_TX_OK;
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}
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void bnx2x_get_c2s_mapping(struct bnx2x *bp, u8 *c2s_map, u8 *c2s_default)
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{
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int mfw_vn = BP_FW_MB_IDX(bp);
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u32 tmp;
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/* If the shmem shouldn't affect configuration, reflect */
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if (!IS_MF_BD(bp)) {
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int i;
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for (i = 0; i < BNX2X_MAX_PRIORITY; i++)
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c2s_map[i] = i;
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*c2s_default = 0;
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return;
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}
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tmp = SHMEM2_RD(bp, c2s_pcp_map_lower[mfw_vn]);
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tmp = (__force u32)be32_to_cpu((__force __be32)tmp);
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c2s_map[0] = tmp & 0xff;
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c2s_map[1] = (tmp >> 8) & 0xff;
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c2s_map[2] = (tmp >> 16) & 0xff;
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c2s_map[3] = (tmp >> 24) & 0xff;
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tmp = SHMEM2_RD(bp, c2s_pcp_map_upper[mfw_vn]);
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tmp = (__force u32)be32_to_cpu((__force __be32)tmp);
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c2s_map[4] = tmp & 0xff;
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c2s_map[5] = (tmp >> 8) & 0xff;
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c2s_map[6] = (tmp >> 16) & 0xff;
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c2s_map[7] = (tmp >> 24) & 0xff;
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tmp = SHMEM2_RD(bp, c2s_pcp_map_default[mfw_vn]);
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tmp = (__force u32)be32_to_cpu((__force __be32)tmp);
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*c2s_default = (tmp >> (8 * mfw_vn)) & 0xff;
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}
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/**
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* bnx2x_setup_tc - routine to configure net_device for multi tc
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*
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@ -4201,8 +4258,9 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
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*/
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int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)
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{
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int cos, prio, count, offset;
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struct bnx2x *bp = netdev_priv(dev);
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u8 c2s_map[BNX2X_MAX_PRIORITY], c2s_def;
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int cos, prio, count, offset;
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/* setup tc must be called under rtnl lock */
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ASSERT_RTNL();
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@ -4226,12 +4284,16 @@ int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)
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return -EINVAL;
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}
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bnx2x_get_c2s_mapping(bp, c2s_map, &c2s_def);
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/* configure priority to traffic class mapping */
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for (prio = 0; prio < BNX2X_MAX_PRIORITY; prio++) {
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netdev_set_prio_tc_map(dev, prio, bp->prio_to_cos[prio]);
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int outer_prio = c2s_map[prio];
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netdev_set_prio_tc_map(dev, prio, bp->prio_to_cos[outer_prio]);
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DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
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"mapping priority %d to tc %d\n",
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prio, bp->prio_to_cos[prio]);
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outer_prio, bp->prio_to_cos[outer_prio]);
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}
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/* Use this configuration to differentiate tc0 from other COSes
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@ -4285,6 +4347,9 @@ int bnx2x_change_mac_addr(struct net_device *dev, void *p)
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if (netif_running(dev))
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rc = bnx2x_set_eth_mac(bp, true);
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if (IS_PF(bp) && SHMEM2_HAS(bp, curr_cfg))
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SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
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return rc;
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}
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@ -4838,6 +4903,9 @@ int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
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*/
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dev->mtu = new_mtu;
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if (IS_PF(bp) && SHMEM2_HAS(bp, curr_cfg))
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SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
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return bnx2x_reload_if_running(dev);
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}
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@ -622,6 +622,14 @@ int bnx2x_set_features(struct net_device *dev, netdev_features_t features);
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*/
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void bnx2x_tx_timeout(struct net_device *dev);
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/** bnx2x_get_c2s_mapping - read inner-to-outer vlan configuration
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* c2s_map should have BNX2X_MAX_PRIORITY entries.
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* @bp: driver handle
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* @c2s_map: should have BNX2X_MAX_PRIORITY entries for mapping
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* @c2s_default: entry for non-tagged configuration
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*/
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void bnx2x_get_c2s_mapping(struct bnx2x *bp, u8 *c2s_map, u8 *c2s_default);
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/*********************** Inlines **********************************/
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/*********************** Fast path ********************************/
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static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
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@ -933,6 +941,27 @@ static inline int bnx2x_func_start(struct bnx2x *bp)
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start_params->mf_mode = bp->mf_mode;
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start_params->sd_vlan_tag = bp->mf_ov;
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/* Configure Ethertype for BD mode */
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if (IS_MF_BD(bp)) {
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DP(NETIF_MSG_IFUP, "Configuring ethertype 0x88a8 for BD\n");
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start_params->sd_vlan_eth_type = ETH_P_8021AD;
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REG_WR(bp, PRS_REG_VLAN_TYPE_0, ETH_P_8021AD);
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REG_WR(bp, PBF_REG_VLAN_TYPE_0, ETH_P_8021AD);
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REG_WR(bp, NIG_REG_LLH_E1HOV_TYPE_1, ETH_P_8021AD);
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bnx2x_get_c2s_mapping(bp, start_params->c2s_pri,
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&start_params->c2s_pri_default);
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start_params->c2s_pri_valid = 1;
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DP(NETIF_MSG_IFUP,
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"Inner-to-Outer priority: %02x %02x %02x %02x %02x %02x %02x %02x [Default %02x]\n",
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start_params->c2s_pri[0], start_params->c2s_pri[1],
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start_params->c2s_pri[2], start_params->c2s_pri[3],
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start_params->c2s_pri[4], start_params->c2s_pri[5],
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start_params->c2s_pri[6], start_params->c2s_pri[7],
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start_params->c2s_pri_default);
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}
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if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
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start_params->network_cos_mode = STATIC_COS;
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else /* CHIP_IS_E1X */
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@ -1339,4 +1368,11 @@ void bnx2x_squeeze_objects(struct bnx2x *bp);
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void bnx2x_schedule_sp_rtnl(struct bnx2x*, enum sp_rtnl_flag,
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u32 verbose);
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/**
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* bnx2x_set_os_driver_state - write driver state for management FW usage
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*
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* @bp: driver handle
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* @state: OS_DRIVER_STATE_* value reflecting current driver state
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*/
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void bnx2x_set_os_driver_state(struct bnx2x *bp, u32 state);
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#endif /* BNX2X_CMN_H */
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@ -1131,6 +1131,9 @@ static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
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} else
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bp->wol = 0;
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if (SHMEM2_HAS(bp, curr_cfg))
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SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
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return 0;
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}
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@ -868,6 +868,7 @@ struct shared_feat_cfg { /* NVRAM Offset */
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#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
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#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
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#define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
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#define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500
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#define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600
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#define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700
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@ -2068,6 +2069,12 @@ struct ncsi_oem_fcoe_features {
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#define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
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};
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enum curr_cfg_method_e {
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CURR_CFG_MET_NONE = 0, /* default config */
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CURR_CFG_MET_OS = 1,
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CURR_CFG_MET_VENDOR_SPEC = 2,/* e.g. Option ROM, NPAR, O/S Cfg Utils */
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};
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struct ncsi_oem_data {
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u32 driver_version[4];
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struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
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@ -2191,6 +2198,8 @@ struct shmem2_region {
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#define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
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#define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
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#define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
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#define DRV_FLAGS_MTU_MASK 0xffff0000
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#define DRV_FLAGS_MTU_SHIFT 16
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u32 extended_dev_info_shared_cfg_size;
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@ -2273,6 +2282,71 @@ struct shmem2_region {
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/* We use indication for each PF (0..3) */
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#define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << (_pf_))
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union { /* For various OEMs */ /* Offset 0x1a0 */
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u8 storage_boot_prog[E2_FUNC_MAX];
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#define STORAGE_BOOT_PROG_MASK 0x000000FF
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#define STORAGE_BOOT_PROG_NONE 0x00000000
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#define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002
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#define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002
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#define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004
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#define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008
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#define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008
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#define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010
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#define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020
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#define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040
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#define STORAGE_BOOT_PROG_COMPLETED 0x00000080
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u32 oem_i2c_data_addr;
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};
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/* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
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/* For PCP values 0-3 use the map lower */
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/* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
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* 0x0000FF00 - PCP 2, 0x000000FF PCP 3
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*/
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u32 c2s_pcp_map_lower[E2_FUNC_MAX]; /* 0x1a4 */
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/* For PCP values 4-7 use the map upper */
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/* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
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* 0x0000FF00 - PCP 6, 0x000000FF PCP 7
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*/
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u32 c2s_pcp_map_upper[E2_FUNC_MAX]; /* 0x1b4 */
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/* For PCP default value get the MSB byte of the map default */
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u32 c2s_pcp_map_default[E2_FUNC_MAX]; /* 0x1c4 */
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/* FC_NPIV table offset in NVRAM */
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u32 fc_npiv_nvram_tbl_addr[PORT_MAX]; /* 0x1d4 */
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/* Shows last method that changed configuration of this device */
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enum curr_cfg_method_e curr_cfg; /* 0x1dc */
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/* Storm FW version, shold be kept in the format 0xMMmmbbdd:
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* MM - Major, mm - Minor, bb - Build ,dd - Drop
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*/
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u32 netproc_fw_ver; /* 0x1e0 */
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/* Option ROM SMASH CLP version */
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u32 clp_ver; /* 0x1e4 */
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u32 pcie_bus_num; /* 0x1e8 */
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u32 sriov_switch_mode; /* 0x1ec */
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#define SRIOV_SWITCH_MODE_NONE 0x0
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#define SRIOV_SWITCH_MODE_VEB 0x1
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#define SRIOV_SWITCH_MODE_VEPA 0x2
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u8 rsrv2[E2_FUNC_MAX]; /* 0x1f0 */
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u32 img_inv_table_addr; /* Address to INV_TABLE_P */ /* 0x1f4 */
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u32 mtu_size[E2_FUNC_MAX]; /* 0x1f8 */
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u32 os_driver_state[E2_FUNC_MAX]; /* 0x208 */
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#define OS_DRIVER_STATE_NOT_LOADED 0 /* not installed */
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#define OS_DRIVER_STATE_LOADING 1 /* transition state */
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#define OS_DRIVER_STATE_DISABLED 2 /* installed but disabled */
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#define OS_DRIVER_STATE_ACTIVE 3 /* installed and active */
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};
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@ -2918,7 +2918,7 @@ static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
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func_params.f_obj = &bp->func_obj;
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func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
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if (IS_MF_UFP(bp)) {
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if (IS_MF_UFP(bp) || IS_MF_BD(bp)) {
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int func = BP_ABS_FUNC(bp);
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u32 val;
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@ -2945,16 +2945,16 @@ static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
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BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
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bp->mf_ov);
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goto fail;
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} else {
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DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n",
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bp->mf_ov);
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}
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DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov);
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bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
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return;
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} else {
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goto fail;
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}
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/* not supported by SW yet */
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bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
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return;
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fail:
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bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
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}
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@ -7433,6 +7433,9 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
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} else
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BNX2X_ERR("Bootcode is missing - can not initialize link\n");
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if (SHMEM2_HAS(bp, netproc_fw_ver))
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||||
SHMEM2_WR(bp, netproc_fw_ver, REG_RD(bp, XSEM_REG_PRAM));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -11682,7 +11685,7 @@ static void validate_set_si_mode(struct bnx2x *bp)
|
||||
static int bnx2x_get_hwinfo(struct bnx2x *bp)
|
||||
{
|
||||
int /*abs*/func = BP_ABS_FUNC(bp);
|
||||
int vn;
|
||||
int vn, mfw_vn;
|
||||
u32 val = 0, val2 = 0;
|
||||
int rc = 0;
|
||||
|
||||
@ -11772,6 +11775,7 @@ static int bnx2x_get_hwinfo(struct bnx2x *bp)
|
||||
bp->mf_mode = 0;
|
||||
bp->mf_sub_mode = 0;
|
||||
vn = BP_VN(bp);
|
||||
mfw_vn = BP_FW_MB_IDX(bp);
|
||||
|
||||
if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
|
||||
BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
|
||||
@ -11828,6 +11832,31 @@ static int bnx2x_get_hwinfo(struct bnx2x *bp)
|
||||
} else
|
||||
BNX2X_DEV_INFO("illegal OV for SD\n");
|
||||
break;
|
||||
case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE:
|
||||
bp->mf_mode = MULTI_FUNCTION_SD;
|
||||
bp->mf_sub_mode = SUB_MF_MODE_BD;
|
||||
bp->mf_config[vn] =
|
||||
MF_CFG_RD(bp,
|
||||
func_mf_config[func].config);
|
||||
|
||||
if (SHMEM2_HAS(bp, mtu_size)) {
|
||||
int mtu_idx = BP_FW_MB_IDX(bp);
|
||||
u16 mtu_size;
|
||||
u32 mtu;
|
||||
|
||||
mtu = SHMEM2_RD(bp, mtu_size[mtu_idx]);
|
||||
mtu_size = (u16)mtu;
|
||||
DP(NETIF_MSG_IFUP, "Read MTU size %04x [%08x]\n",
|
||||
mtu_size, mtu);
|
||||
|
||||
/* if valid: update device mtu */
|
||||
if (((mtu_size + ETH_HLEN) >=
|
||||
ETH_MIN_PACKET_SIZE) &&
|
||||
(mtu_size <=
|
||||
ETH_MAX_JUMBO_PACKET_SIZE))
|
||||
bp->dev->mtu = mtu_size;
|
||||
}
|
||||
break;
|
||||
case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
|
||||
bp->mf_mode = MULTI_FUNCTION_SD;
|
||||
bp->mf_sub_mode = SUB_MF_MODE_UFP;
|
||||
@ -11875,9 +11904,10 @@ static int bnx2x_get_hwinfo(struct bnx2x *bp)
|
||||
|
||||
BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
|
||||
func, bp->mf_ov, bp->mf_ov);
|
||||
} else if (bp->mf_sub_mode == SUB_MF_MODE_UFP) {
|
||||
} else if ((bp->mf_sub_mode == SUB_MF_MODE_UFP) ||
|
||||
(bp->mf_sub_mode == SUB_MF_MODE_BD)) {
|
||||
dev_err(&bp->pdev->dev,
|
||||
"Unexpected - no valid MF OV for func %d in UFP mode\n",
|
||||
"Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
|
||||
func);
|
||||
bp->path_has_ovlan = true;
|
||||
} else {
|
||||
@ -13565,6 +13595,9 @@ static int bnx2x_init_one(struct pci_dev *pdev,
|
||||
|
||||
bnx2x_register_phc(bp);
|
||||
|
||||
if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp))
|
||||
bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_DISABLED);
|
||||
|
||||
return 0;
|
||||
|
||||
init_one_exit:
|
||||
@ -13627,6 +13660,7 @@ static void __bnx2x_remove(struct pci_dev *pdev,
|
||||
/* Power on: we can't let PCI layer write to us while we are in D3 */
|
||||
if (IS_PF(bp)) {
|
||||
bnx2x_set_power_state(bp, PCI_D0);
|
||||
bnx2x_set_os_driver_state(bp, OS_DRIVER_STATE_NOT_LOADED);
|
||||
|
||||
/* Set endianity registers to reset values in case next driver
|
||||
* boots in different endianty environment.
|
||||
|
||||
@ -2139,6 +2139,10 @@
|
||||
/* [RW 1] When this bit is set; the LLH will expect all packets to be with
|
||||
e1hov */
|
||||
#define NIG_REG_LLH_E1HOV_MODE 0x160d8
|
||||
/* [RW 16] Outer VLAN type identifier for multi-function mode. In non
|
||||
* multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
|
||||
*/
|
||||
#define NIG_REG_LLH_E1HOV_TYPE_1 0x16028
|
||||
/* [RW 1] When this bit is set; the LLH will classify the packet before
|
||||
sending it to the BRB or calculating WoL on it. */
|
||||
#define NIG_REG_LLH_MF_MODE 0x16024
|
||||
@ -2955,7 +2959,12 @@
|
||||
#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
|
||||
/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
|
||||
#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
|
||||
#define PB_REG_CONTROL 0
|
||||
/* [RW 16] One of 8 values that should be compared to type in Ethernet
|
||||
* parsing. If there is a match; the field after Ethernet is the first VLAN.
|
||||
* Reset value is 0x8100 which is the standard VLAN type. Note that when
|
||||
* checking second VLAN; type is compared only to 0x8100.
|
||||
*/
|
||||
#define PBF_REG_VLAN_TYPE_0 0x15c06c
|
||||
/* [RW 2] Interrupt mask register #0 read/write */
|
||||
#define PB_REG_PB_INT_MASK 0x28
|
||||
/* [R 2] Interrupt register #0 read */
|
||||
@ -3374,6 +3383,12 @@
|
||||
#define PRS_REG_TCM_CURRENT_CREDIT 0x40160
|
||||
/* [R 8] debug only: TSDM current credit. Transaction based. */
|
||||
#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
|
||||
/* [RW 16] One of 8 values that should be compared to type in Ethernet
|
||||
* parsing. If there is a match; the field after Ethernet is the first VLAN.
|
||||
* Reset value is 0x8100 which is the standard VLAN type. Note that when
|
||||
* checking second VLAN; type is compared only to 0x8100.
|
||||
*/
|
||||
#define PRS_REG_VLAN_TYPE_0 0x401a8
|
||||
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
|
||||
#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
|
||||
#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
|
||||
|
||||
@ -1340,6 +1340,9 @@ int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param,
|
||||
|
||||
mutex_init(&bp->vfdb->bulletin_mutex);
|
||||
|
||||
if (SHMEM2_HAS(bp, sriov_switch_mode))
|
||||
SHMEM2_WR(bp, sriov_switch_mode, SRIOV_SWITCH_MODE_VEB);
|
||||
|
||||
return 0;
|
||||
failed:
|
||||
DP(BNX2X_MSG_IOV, "Failed err=%d\n", err);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user