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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/amdgpu: Add runtime VCN PG support
Enable support for dynamically powering up/down VCN on demand. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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61c8e90d96
commit
22cc6c5e19
drivers/gpu/drm/amd/amdgpu
@ -212,11 +212,11 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
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}
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if (fences == 0) {
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if (adev->pm.dpm_enabled) {
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/* might be used when with pg/cg
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if (adev->pm.dpm_enabled)
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amdgpu_dpm_enable_uvd(adev, false);
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*/
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}
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else
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amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
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AMD_PG_STATE_GATE);
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} else {
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schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
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}
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@ -228,9 +228,11 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
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bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
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if (set_clocks && adev->pm.dpm_enabled) {
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/* might be used when with pg/cg
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if (adev->pm.dpm_enabled)
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amdgpu_dpm_enable_uvd(adev, true);
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*/
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else
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amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
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AMD_PG_STATE_UNGATE);
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}
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}
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@ -35,7 +35,6 @@
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#include "mmhub/mmhub_9_1_offset.h"
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#include "mmhub/mmhub_9_1_sh_mask.h"
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static int vcn_v1_0_start(struct amdgpu_device *adev);
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static int vcn_v1_0_stop(struct amdgpu_device *adev);
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static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
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static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
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@ -146,10 +145,6 @@ static int vcn_v1_0_hw_init(void *handle)
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struct amdgpu_ring *ring = &adev->vcn.ring_dec;
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int i, r;
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r = vcn_v1_0_start(adev);
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if (r)
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goto done;
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ring->ready = true;
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r = amdgpu_ring_test_ring(ring);
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if (r) {
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@ -185,11 +180,9 @@ static int vcn_v1_0_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_ring *ring = &adev->vcn.ring_dec;
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int r;
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r = vcn_v1_0_stop(adev);
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if (r)
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return r;
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if (RREG32_SOC15(VCN, 0, mmUVD_STATUS))
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vcn_v1_0_stop(adev);
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ring->ready = false;
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@ -769,7 +762,7 @@ static int vcn_v1_0_stop(struct amdgpu_device *adev)
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
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~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
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/* enable clock gating */
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WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0);
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vcn_v1_0_enable_clock_gating(adev);
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vcn_1_0_enable_static_power_gating(adev);
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@ -1179,6 +1172,23 @@ static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t coun
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}
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}
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static int vcn_v1_0_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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/* This doesn't actually powergate the VCN block.
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* That's done in the dpm code via the SMC. This
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* just re-inits the block as necessary. The actual
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* gating still happens in the dpm code. We should
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* revisit this when there is a cleaner line between
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* the smc and the hw blocks
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*/
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (state == AMD_PG_STATE_GATE)
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return vcn_v1_0_stop(adev);
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else
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return vcn_v1_0_start(adev);
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}
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static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
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.name = "vcn_v1_0",
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@ -1197,7 +1207,7 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
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.soft_reset = NULL /* vcn_v1_0_soft_reset */,
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.post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
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.set_clockgating_state = vcn_v1_0_set_clockgating_state,
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.set_powergating_state = NULL /* vcn_v1_0_set_powergating_state */,
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.set_powergating_state = vcn_v1_0_set_powergating_state,
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};
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static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
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