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gpio: altera: make use of raw_spinlock variants

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The altera gpio driver currently implements an irq_chip for handling
interrupts; due to how irq_chip handling is done, it's necessary for the
irq_chip methods to be invoked from hardirq context, even on a a real-time
kernel.  Because the spinlock_t type becomes a "sleeping" spinlock w/ RT
kernels, it is not suitable to be used with irq_chips.

A quick audit of the operations under the lock reveal that they do only
minimal, bounded work, and are therefore safe to do under a raw spinlock.

Signed-off-by: Julia Cartwright <julia@ni.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Julia Cartwright 2017-03-09 10:21:49 -06:00 committed by Linus Walleij
parent 660549e05d
commit 21d01c9c08
1 changed files with 12 additions and 12 deletions
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24
drivers/gpio/gpio-altera.c
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@ -38,7 +38,7 @@
*/ */
struct altera_gpio_chip { struct altera_gpio_chip {
struct of_mm_gpio_chip mmchip; struct of_mm_gpio_chip mmchip;
spinlock_t gpio_lock; raw_spinlock_t gpio_lock;
int interrupt_trigger; int interrupt_trigger;
int mapped_irq; int mapped_irq;
}; };
@ -53,12 +53,12 @@ static void altera_gpio_irq_unmask(struct irq_data *d)
altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d)); altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
mm_gc = &altera_gc->mmchip; mm_gc = &altera_gc->mmchip;
spin_lock_irqsave(&altera_gc->gpio_lock, flags); raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK); intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
/* Set ALTERA_GPIO_IRQ_MASK bit to unmask */ /* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
intmask |= BIT(irqd_to_hwirq(d)); intmask |= BIT(irqd_to_hwirq(d));
writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK); writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
spin_unlock_irqrestore(&altera_gc->gpio_lock, flags); raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
} }
static void altera_gpio_irq_mask(struct irq_data *d) static void altera_gpio_irq_mask(struct irq_data *d)
@ -71,12 +71,12 @@ static void altera_gpio_irq_mask(struct irq_data *d)
altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d)); altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
mm_gc = &altera_gc->mmchip; mm_gc = &altera_gc->mmchip;
spin_lock_irqsave(&altera_gc->gpio_lock, flags); raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK); intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
/* Clear ALTERA_GPIO_IRQ_MASK bit to mask */ /* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
intmask &= ~BIT(irqd_to_hwirq(d)); intmask &= ~BIT(irqd_to_hwirq(d));
writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK); writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
spin_unlock_irqrestore(&altera_gc->gpio_lock, flags); raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
} }
/** /**
@ -143,14 +143,14 @@ static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
mm_gc = to_of_mm_gpio_chip(gc); mm_gc = to_of_mm_gpio_chip(gc);
chip = gpiochip_get_data(gc); chip = gpiochip_get_data(gc);
spin_lock_irqsave(&chip->gpio_lock, flags); raw_spin_lock_irqsave(&chip->gpio_lock, flags);
data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA); data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
if (value) if (value)
data_reg |= BIT(offset); data_reg |= BIT(offset);
else else
data_reg &= ~BIT(offset); data_reg &= ~BIT(offset);
writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA); writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
spin_unlock_irqrestore(&chip->gpio_lock, flags); raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
} }
static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset) static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
@ -163,12 +163,12 @@ static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
mm_gc = to_of_mm_gpio_chip(gc); mm_gc = to_of_mm_gpio_chip(gc);
chip = gpiochip_get_data(gc); chip = gpiochip_get_data(gc);
spin_lock_irqsave(&chip->gpio_lock, flags); raw_spin_lock_irqsave(&chip->gpio_lock, flags);
/* Set pin as input, assumes software controlled IP */ /* Set pin as input, assumes software controlled IP */
gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR); gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
gpio_ddr &= ~BIT(offset); gpio_ddr &= ~BIT(offset);
writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR); writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
spin_unlock_irqrestore(&chip->gpio_lock, flags); raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
return 0; return 0;
} }
@ -184,7 +184,7 @@ static int altera_gpio_direction_output(struct gpio_chip *gc,
mm_gc = to_of_mm_gpio_chip(gc); mm_gc = to_of_mm_gpio_chip(gc);
chip = gpiochip_get_data(gc); chip = gpiochip_get_data(gc);
spin_lock_irqsave(&chip->gpio_lock, flags); raw_spin_lock_irqsave(&chip->gpio_lock, flags);
/* Sets the GPIO value */ /* Sets the GPIO value */
data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA); data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
if (value) if (value)
@ -197,7 +197,7 @@ static int altera_gpio_direction_output(struct gpio_chip *gc,
gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR); gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
gpio_ddr |= BIT(offset); gpio_ddr |= BIT(offset);
writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR); writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
spin_unlock_irqrestore(&chip->gpio_lock, flags); raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
return 0; return 0;
} }
@ -266,7 +266,7 @@ static int altera_gpio_probe(struct platform_device *pdev)
if (!altera_gc) if (!altera_gc)
return -ENOMEM; return -ENOMEM;
spin_lock_init(&altera_gc->gpio_lock); raw_spin_lock_init(&altera_gc->gpio_lock);
if (of_property_read_u32(node, "altr,ngpio", &reg)) if (of_property_read_u32(node, "altr,ngpio", &reg))
/* By default assume maximum ngpio */ /* By default assume maximum ngpio */