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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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[SERIAL] Support Au1x00 8250 UARTs using the generic 8250 driver.
The offsets of the registers are in a different place, and some parts cannot handle a full set of modem control signals. Signed-off-by: Pantelis Antoniou <pantelis@embeddedalley.ocm> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -251,9 +251,53 @@ static const struct serial8250_config uart_config[] = {
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},
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};
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#ifdef CONFIG_SERIAL_8250_AU1X00
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/* Au1x00 UART hardware has a weird register layout */
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static const u8 au_io_in_map[] = {
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[UART_RX] = 0,
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[UART_IER] = 2,
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[UART_IIR] = 3,
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[UART_LCR] = 5,
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[UART_MCR] = 6,
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[UART_LSR] = 7,
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[UART_MSR] = 8,
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};
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static const u8 au_io_out_map[] = {
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[UART_TX] = 1,
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[UART_IER] = 2,
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[UART_FCR] = 4,
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[UART_LCR] = 5,
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[UART_MCR] = 6,
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};
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/* sane hardware needs no mapping */
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static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
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{
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if (up->port.iotype != UPIO_AU)
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return offset;
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return au_io_in_map[offset];
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}
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static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
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{
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if (up->port.iotype != UPIO_AU)
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return offset;
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return au_io_out_map[offset];
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}
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#else
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/* sane hardware needs no mapping */
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#define map_8250_in_reg(up, offset) (offset)
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#define map_8250_out_reg(up, offset) (offset)
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#endif
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static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
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{
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offset <<= up->port.regshift;
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offset = map_8250_in_reg(up, offset) << up->port.regshift;
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switch (up->port.iotype) {
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case UPIO_HUB6:
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@ -266,6 +310,11 @@ static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
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case UPIO_MEM32:
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return readl(up->port.membase + offset);
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#ifdef CONFIG_SERIAL_8250_AU1X00
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case UPIO_AU:
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return __raw_readl(up->port.membase + offset);
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#endif
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default:
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return inb(up->port.iobase + offset);
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}
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@ -274,7 +323,7 @@ static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
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static _INLINE_ void
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serial_out(struct uart_8250_port *up, int offset, int value)
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{
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offset <<= up->port.regshift;
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offset = map_8250_out_reg(up, offset) << up->port.regshift;
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switch (up->port.iotype) {
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case UPIO_HUB6:
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@ -290,6 +339,12 @@ serial_out(struct uart_8250_port *up, int offset, int value)
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writel(value, up->port.membase + offset);
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break;
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#ifdef CONFIG_SERIAL_8250_AU1X00
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case UPIO_AU:
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__raw_writel(value, up->port.membase + offset);
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break;
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#endif
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default:
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outb(value, up->port.iobase + offset);
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}
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@ -910,6 +965,13 @@ static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
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}
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}
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#endif
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#ifdef CONFIG_SERIAL_8250_AU1X00
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/* if access method is AU, it is a 16550 with a quirk */
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if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
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up->bugs |= UART_BUG_NOMSR;
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#endif
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serial_outp(up, UART_LCR, save_lcr);
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if (up->capabilities != uart_config[up->port.type].flags) {
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@ -1057,6 +1119,10 @@ static void serial8250_enable_ms(struct uart_port *port)
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{
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struct uart_8250_port *up = (struct uart_8250_port *)port;
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/* no MSR capabilities */
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if (up->bugs & UART_BUG_NOMSR)
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return;
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up->ier |= UART_IER_MSI;
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serial_out(up, UART_IER, up->ier);
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}
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@ -1774,7 +1840,8 @@ serial8250_set_termios(struct uart_port *port, struct termios *termios,
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* CTS flow control flag and modem status interrupts
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*/
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up->ier &= ~UART_IER_MSI;
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if (UART_ENABLE_MS(&up->port, termios->c_cflag))
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if (!(up->bugs & UART_BUG_NOMSR) &&
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UART_ENABLE_MS(&up->port, termios->c_cflag))
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up->ier |= UART_IER_MSI;
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if (up->capabilities & UART_CAP_UUE)
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up->ier |= UART_IER_UUE | UART_IER_RTOIE;
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@ -49,6 +49,7 @@ struct serial8250_config {
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#define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
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#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
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#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
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#if defined(__i386__) && (defined(CONFIG_M386) || defined(CONFIG_M486))
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#define _INLINE_ inline
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102
drivers/serial/8250_au1x00.c
Normal file
102
drivers/serial/8250_au1x00.c
Normal file
@ -0,0 +1,102 @@
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/*
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* Serial Device Initialisation for Au1x00
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*
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* (C) Copyright Embedded Alley Solutions, Inc 2005
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* Author: Pantelis Antoniou <pantelis@embeddedalley.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/serial_core.h>
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#include <linux/signal.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/serial_8250.h>
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#include <asm/mach-au1x00/au1000.h>
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#include "8250.h"
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#define PORT(_base, _irq) \
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{ \
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.iobase = _base, \
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.membase = (void __iomem *)_base,\
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.mapbase = _base, \
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.irq = _irq, \
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.uartclk = 0, /* filled */ \
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.regshift = 2, \
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.iotype = UPIO_AU, \
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.flags = UPF_SKIP_TEST | \
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UPF_IOREMAP, \
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}
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static struct plat_serial8250_port au1x00_data[] = {
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#if defined(CONFIG_SOC_AU1000)
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PORT(UART0_ADDR, AU1000_UART0_INT),
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PORT(UART1_ADDR, AU1000_UART1_INT),
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PORT(UART2_ADDR, AU1000_UART2_INT),
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PORT(UART3_ADDR, AU1000_UART3_INT),
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#elif defined(CONFIG_SOC_AU1500)
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PORT(UART0_ADDR, AU1500_UART0_INT),
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PORT(UART3_ADDR, AU1500_UART3_INT),
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#elif defined(CONFIG_SOC_AU1100)
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PORT(UART0_ADDR, AU1100_UART0_INT),
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PORT(UART1_ADDR, AU1100_UART1_INT),
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PORT(UART2_ADDR, AU1100_UART2_INT),
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PORT(UART3_ADDR, AU1100_UART3_INT),
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#elif defined(CONFIG_SOC_AU1550)
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PORT(UART0_ADDR, AU1550_UART0_INT),
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PORT(UART1_ADDR, AU1550_UART1_INT),
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PORT(UART2_ADDR, AU1550_UART2_INT),
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PORT(UART3_ADDR, AU1550_UART3_INT),
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#elif defined(CONFIG_SOC_AU1200)
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PORT(UART0_ADDR, AU1200_UART0_INT),
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PORT(UART1_ADDR, AU1200_UART1_INT),
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#endif
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{ },
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};
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static struct platform_device au1x00_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_AU1X00,
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.dev = {
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.platform_data = au1x00_data,
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},
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};
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static int __init au1x00_init(void)
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{
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int i;
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unsigned int uartclk;
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/* get uart clock */
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uartclk = get_au1x00_uart_baud_base() * 16;
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/* fill up uartclk */
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for (i = 0; au1x00_data[i].flags ; i++)
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au1x00_data[i].uartclk = uartclk;
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return platform_device_register(&au1x00_device);
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}
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/* XXX: Yes, I know this doesn't yet work. */
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static void __exit au1x00_exit(void)
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{
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platform_device_unregister(&au1x00_device);
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}
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module_init(au1x00_init);
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module_exit(au1x00_exit);
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MODULE_AUTHOR("Pantelis Antoniou <pantelis@embeddedalley.com>");
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MODULE_DESCRIPTION("8250 serial probe module for Au1x000 cards");
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MODULE_LICENSE("GPL");
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@ -207,6 +207,14 @@ config SERIAL_8250_ACORN
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system, say Y to this option. The driver can handle 1, 2, or 3 port
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cards. If unsure, say N.
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config SERIAL_8250_AU1X00
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bool "AU1X00 serial port support"
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depends on SERIAL_8250 != n && SOC_AU1X00
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help
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If you have an Au1x00 board and want to use the serial port, say Y
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to this option. The driver can handle 1 or 2 serial ports.
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If unsure, say N.
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comment "Non-8250 serial port support"
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config SERIAL_AMBA_PL010
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@ -22,6 +22,7 @@ obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o
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obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o
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obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o
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obj-$(CONFIG_SERIAL_8250_MCA) += 8250_mca.o
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obj-$(CONFIG_SERIAL_8250_AU1X00) += 8250_au1x00.o
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obj-$(CONFIG_SERIAL_AMBA_PL010) += amba-pl010.o
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obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o
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obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o
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@ -1959,6 +1959,7 @@ uart_report_port(struct uart_driver *drv, struct uart_port *port)
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break;
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case UPIO_MEM:
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case UPIO_MEM32:
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case UPIO_AU:
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snprintf(address, sizeof(address),
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"MMIO 0x%lx", port->mapbase);
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break;
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@ -42,6 +42,7 @@ enum {
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PLAT8250_DEV_BOCA,
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PLAT8250_DEV_HUB6,
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PLAT8250_DEV_MCA,
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PLAT8250_DEV_AU1X00,
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};
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/*
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@ -211,6 +211,7 @@ struct uart_port {
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#define UPIO_HUB6 (1)
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#define UPIO_MEM (2)
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#define UPIO_MEM32 (3)
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#define UPIO_AU (4) /* Au1x00 type IO */
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unsigned int read_status_mask; /* driver specific */
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unsigned int ignore_status_mask; /* driver specific */
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