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mmc: sdhci-msm: Don't enable PWRSAVE_DLL for certain sdhc hosts
SDHC core with new 14lpp and later tech DLL should not enable PWRSAVE_DLL since such controller's internal gating cannot meet following MCLK requirement: When MCLK is gated OFF, it is not gated for less than 0.5us and MCLK must be switched on for at-least 1us before DATA starts coming. Adding support for this requirement. Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Signed-off-by: Veerabhadrarao Badiganti <vbadigan@codeaurora.org> Reviewed-by: Can Guo <cang@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Link: https://lore.kernel.org/r/1581077075-26011-1-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -977,9 +977,21 @@ static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host *host)
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goto out;
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}
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config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec3);
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config |= CORE_PWRSAVE_DLL;
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writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec3);
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/*
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* Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
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* When MCLK is gated OFF, it is not gated for less than 0.5us
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* and MCLK must be switched on for at-least 1us before DATA
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* starts coming. Controllers with 14lpp and later tech DLL cannot
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* guarantee above requirement. So PWRSAVE_DLL should not be
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* turned on for host controllers using this DLL.
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*/
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if (!msm_host->use_14lpp_dll_reset) {
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config = readl_relaxed(host->ioaddr +
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msm_offset->core_vendor_spec3);
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config |= CORE_PWRSAVE_DLL;
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writel_relaxed(config, host->ioaddr +
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msm_offset->core_vendor_spec3);
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}
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/*
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* Drain writebuffer to ensure above DLL calibration
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