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arm64: dts: marvell: cp110: add GPIO interrupts
Add the GPIO interrupts for the CP110. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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@ -131,8 +131,12 @@ cpm_gpio1: gpio@100 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&cpm_pinctrl 0 0 32>;
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interrupt-controller;
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interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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cpm_gpio2: gpio@140 {
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@ -142,6 +146,11 @@ cpm_gpio2: gpio@140 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&cpm_pinctrl 0 32 31>;
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interrupt-controller;
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interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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@ -138,8 +138,12 @@ cps_gpio1: gpio@100 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&cps_pinctrl 0 0 32>;
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interrupt-controller;
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interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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cps_gpio2: gpio@140 {
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@ -149,6 +153,11 @@ cps_gpio2: gpio@140 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&cps_pinctrl 0 32 31>;
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interrupt-controller;
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interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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