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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 10:06:39 +07:00
drm/nva3: somewhat improve clock reporting
Definitely not 100% correct, but, for the configurations I've seen used it'll read back the correct clocks now. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -27,10 +27,10 @@
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#include "nouveau_bios.h"
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#include "nouveau_pm.h"
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/*XXX: boards using limits 0x40 need fixing, the register layout
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* is correct here, but, there's some other funny magic
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* that modifies things, so it's not likely we'll set/read
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* the correct timings yet.. working on it...
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/* This is actually a lot more complex than it appears here, but hopefully
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* this should be able to deal with what the VBIOS leaves for us..
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*
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* If not, well, I'll jump off that bridge when I come to it.
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*/
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struct nva3_pm_state {
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@ -38,21 +38,57 @@ struct nva3_pm_state {
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int N, M, P;
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};
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static int
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nva3_pm_pll_offset(u32 id)
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{
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static const u32 pll_map[] = {
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0x00, PLL_CORE,
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0x01, PLL_SHADER,
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0x02, PLL_MEMORY,
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0x00, 0x00
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};
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const u32 *map = pll_map;
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while (map[1]) {
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if (id == map[1])
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return map[0];
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map += 2;
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}
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return -ENOENT;
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}
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int
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nva3_pm_clock_get(struct drm_device *dev, u32 id)
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{
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u32 src0, src1, ctrl, coef;
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struct pll_lims pll;
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int P, N, M, ret;
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u32 reg;
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int ret, off;
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int P, N, M;
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ret = get_pll_limits(dev, id, &pll);
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if (ret)
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return ret;
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reg = nv_rd32(dev, pll.reg + 4);
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P = (reg & 0x003f0000) >> 16;
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N = (reg & 0x0000ff00) >> 8;
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M = (reg & 0x000000ff);
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off = nva3_pm_pll_offset(id);
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if (off < 0)
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return off;
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src0 = nv_rd32(dev, 0x4120 + (off * 4));
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src1 = nv_rd32(dev, 0x4160 + (off * 4));
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ctrl = nv_rd32(dev, pll.reg + 0);
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coef = nv_rd32(dev, pll.reg + 4);
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NV_DEBUG(dev, "PLL %02x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
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id, src0, src1, ctrl, coef);
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if (ctrl & 0x00000008) {
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u32 div = ((src1 & 0x003c0000) >> 18) + 1;
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return (pll.refclk * 2) / div;
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}
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P = (coef & 0x003f0000) >> 16;
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N = (coef & 0x0000ff00) >> 8;
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M = (coef & 0x000000ff);
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return pll.refclk * N / M / P;
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}
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