mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 05:46:42 +07:00
powerpc/sstep: Check instruction validity against ISA version before emulation
commit 8813ff49607eab3caaf40fe8929b0ce7dc68e85f upstream.
We currently unconditionally try to emulate newer instructions on older
Power versions that could cause issues. Gate it.
Fixes: 350779a29f ("powerpc: Handle most loads and stores in instruction emulation code")
Signed-off-by: Ananth N Mavinakayanahalli <ananth@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/161157995977.64773.13794501093457185080.stgit@thinktux.local
[Dropped a few missing hunks for the backport to v5.10]
Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ananth N Mavinakayanahalli
Greg Kroah-Hartman
parent
04b049ac9c
commit
20d323c8cf
@ -1241,9 +1241,11 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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if ((word & 0xfe2) == 2)
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op->type = SYSCALL;
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else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
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(word & 0xfe3) == 1)
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(word & 0xfe3) == 1) { /* scv */
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op->type = SYSCALL_VECTORED_0;
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else
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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} else
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op->type = UNKNOWN;
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return 0;
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#endif
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@ -1347,7 +1349,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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#ifdef __powerpc64__
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case 1:
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if (!cpu_has_feature(CPU_FTR_ARCH_31))
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return -1;
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goto unknown_opcode;
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prefix_r = GET_PREFIX_R(word);
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ra = GET_PREFIX_RA(suffix);
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@ -1381,7 +1383,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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#ifdef __powerpc64__
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case 4:
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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return -1;
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goto unknown_opcode;
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switch (word & 0x3f) {
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case 48: /* maddhd */
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@ -1467,6 +1469,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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case 19:
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if (((word >> 1) & 0x1f) == 2) {
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/* addpcis */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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imm = (short) (word & 0xffc1); /* d0 + d2 fields */
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imm |= (word >> 15) & 0x3e; /* d1 field */
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op->val = regs->nip + (imm << 16) + 4;
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@ -1779,7 +1783,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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#ifdef __powerpc64__
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case 265: /* modud */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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return -1;
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goto unknown_opcode;
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op->val = regs->gpr[ra] % regs->gpr[rb];
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goto compute_done;
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#endif
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@ -1789,7 +1793,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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case 267: /* moduw */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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return -1;
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goto unknown_opcode;
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op->val = (unsigned int) regs->gpr[ra] %
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(unsigned int) regs->gpr[rb];
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goto compute_done;
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@ -1826,7 +1830,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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#endif
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case 755: /* darn */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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return -1;
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goto unknown_opcode;
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switch (ra & 0x3) {
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case 0:
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/* 32-bit conditioned */
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@ -1848,14 +1852,14 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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#ifdef __powerpc64__
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case 777: /* modsd */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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return -1;
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goto unknown_opcode;
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op->val = (long int) regs->gpr[ra] %
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(long int) regs->gpr[rb];
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goto compute_done;
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#endif
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case 779: /* modsw */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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return -1;
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goto unknown_opcode;
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op->val = (int) regs->gpr[ra] %
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(int) regs->gpr[rb];
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goto compute_done;
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@ -1932,14 +1936,14 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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#endif
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case 538: /* cnttzw */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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return -1;
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goto unknown_opcode;
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val = (unsigned int) regs->gpr[rd];
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op->val = (val ? __builtin_ctz(val) : 32);
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goto logical_done;
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#ifdef __powerpc64__
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case 570: /* cnttzd */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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return -1;
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goto unknown_opcode;
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val = regs->gpr[rd];
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op->val = (val ? __builtin_ctzl(val) : 64);
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goto logical_done;
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@ -2049,7 +2053,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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case 890: /* extswsli with sh_5 = 0 */
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case 891: /* extswsli with sh_5 = 1 */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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return -1;
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goto unknown_opcode;
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op->type = COMPUTE + SETREG;
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sh = rb | ((word & 2) << 4);
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val = (signed int) regs->gpr[rd];
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@ -2376,6 +2380,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 268: /* lxvx */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd | ((word & 1) << 5);
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op->type = MKOP(LOAD_VSX, 0, 16);
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op->element_size = 16;
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@ -2385,6 +2391,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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case 269: /* lxvl */
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case 301: { /* lxvll */
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int nb;
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd | ((word & 1) << 5);
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op->ea = ra ? regs->gpr[ra] : 0;
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nb = regs->gpr[rb] & 0xff;
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@ -2404,6 +2412,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 364: /* lxvwsx */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd | ((word & 1) << 5);
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op->type = MKOP(LOAD_VSX, 0, 4);
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op->element_size = 4;
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@ -2411,6 +2421,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 396: /* stxvx */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd | ((word & 1) << 5);
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op->type = MKOP(STORE_VSX, 0, 16);
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op->element_size = 16;
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@ -2420,6 +2432,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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case 397: /* stxvl */
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case 429: { /* stxvll */
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int nb;
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd | ((word & 1) << 5);
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op->ea = ra ? regs->gpr[ra] : 0;
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nb = regs->gpr[rb] & 0xff;
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@ -2464,6 +2478,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 781: /* lxsibzx */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd | ((word & 1) << 5);
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op->type = MKOP(LOAD_VSX, 0, 1);
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op->element_size = 8;
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@ -2471,6 +2487,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 812: /* lxvh8x */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd | ((word & 1) << 5);
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op->type = MKOP(LOAD_VSX, 0, 16);
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op->element_size = 2;
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@ -2478,6 +2496,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 813: /* lxsihzx */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd | ((word & 1) << 5);
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op->type = MKOP(LOAD_VSX, 0, 2);
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op->element_size = 8;
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@ -2491,6 +2511,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 876: /* lxvb16x */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd | ((word & 1) << 5);
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op->type = MKOP(LOAD_VSX, 0, 16);
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op->element_size = 1;
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@ -2504,6 +2526,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 909: /* stxsibx */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd | ((word & 1) << 5);
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op->type = MKOP(STORE_VSX, 0, 1);
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op->element_size = 8;
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@ -2511,6 +2535,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 940: /* stxvh8x */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd | ((word & 1) << 5);
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op->type = MKOP(STORE_VSX, 0, 16);
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op->element_size = 2;
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@ -2518,6 +2544,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 941: /* stxsihx */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd | ((word & 1) << 5);
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op->type = MKOP(STORE_VSX, 0, 2);
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op->element_size = 8;
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@ -2531,6 +2559,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 1004: /* stxvb16x */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd | ((word & 1) << 5);
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op->type = MKOP(STORE_VSX, 0, 16);
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op->element_size = 1;
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@ -2639,12 +2669,16 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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op->type = MKOP(LOAD_FP, 0, 16);
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break;
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case 2: /* lxsd */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd + 32;
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op->type = MKOP(LOAD_VSX, 0, 8);
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op->element_size = 8;
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op->vsx_flags = VSX_CHECK_VEC;
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break;
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case 3: /* lxssp */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->reg = rd + 32;
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op->type = MKOP(LOAD_VSX, 0, 4);
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op->element_size = 8;
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@ -2681,6 +2715,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 1: /* lxv */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->ea = dqform_ea(word, regs);
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if (word & 8)
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op->reg = rd + 32;
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@ -2691,6 +2727,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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case 2: /* stxsd with LSB of DS field = 0 */
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case 6: /* stxsd with LSB of DS field = 1 */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->ea = dsform_ea(word, regs);
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op->reg = rd + 32;
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op->type = MKOP(STORE_VSX, 0, 8);
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@ -2700,6 +2738,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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case 3: /* stxssp with LSB of DS field = 0 */
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case 7: /* stxssp with LSB of DS field = 1 */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->ea = dsform_ea(word, regs);
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op->reg = rd + 32;
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op->type = MKOP(STORE_VSX, 0, 4);
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@ -2708,6 +2748,8 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 5: /* stxv */
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if (!cpu_has_feature(CPU_FTR_ARCH_300))
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goto unknown_opcode;
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op->ea = dqform_ea(word, regs);
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if (word & 8)
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op->reg = rd + 32;
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@ -2737,7 +2779,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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break;
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case 1: /* Prefixed instructions */
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if (!cpu_has_feature(CPU_FTR_ARCH_31))
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return -1;
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goto unknown_opcode;
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prefix_r = GET_PREFIX_R(word);
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ra = GET_PREFIX_RA(suffix);
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@ -2872,6 +2914,10 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
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return 0;
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unknown_opcode:
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op->type = UNKNOWN;
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return 0;
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logical_done:
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if (word & 1)
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set_cr0(regs, op);
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