mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-18 19:16:20 +07:00
drm/nouveau: create real execution engine for software object class
Just a cleanup more or less, and to remove the need for special handling of software objects. This removes a heap of documentation on dma/graph object formats. The info is very out of date with our current understanding, and is far better documented in rnndb in envytools git. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
2cda7f4c5e
commit
20abd1634a
@ -18,6 +18,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
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nv50_fb.o nvc0_fb.o \
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nv04_fifo.o nv10_fifo.o nv40_fifo.o nv50_fifo.o nvc0_fifo.o \
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nve0_fifo.o \
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nv04_software.o nv50_software.o nvc0_software.o \
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nv04_graph.o nv10_graph.o nv20_graph.o \
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nv40_graph.o nv50_graph.o nvc0_graph.o nve0_graph.o \
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nv40_grctx.o nv50_grctx.o nvc0_grctx.o nve0_grctx.o \
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@ -28,6 +28,7 @@
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#include "nouveau_drm.h"
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#include "nouveau_dma.h"
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#include "nouveau_ramht.h"
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#include "nouveau_software.h"
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static int
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nouveau_channel_pushbuf_init(struct nouveau_channel *chan)
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@ -155,8 +156,6 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
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}
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NV_DEBUG(dev, "initialising channel %d\n", chan->id);
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INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
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INIT_LIST_HEAD(&chan->nvsw.flip);
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INIT_LIST_HEAD(&chan->fence.pending);
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spin_lock_init(&chan->fence.lock);
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@ -213,6 +212,12 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
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OUT_RING (chan, 0x00000000);
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FIRE_RING(chan);
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ret = nouveau_gpuobj_gr_new(chan, NvSw, nouveau_software_class(dev));
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if (ret) {
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nouveau_channel_put(&chan);
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return ret;
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}
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ret = nouveau_fence_channel_init(chan);
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if (ret) {
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nouveau_channel_put(&chan);
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@ -33,6 +33,7 @@
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#include "nouveau_crtc.h"
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#include "nouveau_dma.h"
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#include "nouveau_connector.h"
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#include "nouveau_software.h"
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#include "nouveau_gpio.h"
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#include "nv50_display.h"
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@ -432,6 +433,7 @@ nouveau_page_flip_emit(struct nouveau_channel *chan,
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struct nouveau_page_flip_state *s,
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struct nouveau_fence **pfence)
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{
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struct nouveau_software_chan *swch = chan->engctx[NVOBJ_ENGINE_SW];
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struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
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struct drm_device *dev = chan->dev;
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unsigned long flags;
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@ -439,7 +441,7 @@ nouveau_page_flip_emit(struct nouveau_channel *chan,
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/* Queue it to the pending list */
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spin_lock_irqsave(&dev->event_lock, flags);
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list_add_tail(&s->head, &chan->nvsw.flip);
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list_add_tail(&s->head, &swch->flip);
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spin_unlock_irqrestore(&dev->event_lock, flags);
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/* Synchronize with the old framebuffer */
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@ -547,20 +549,20 @@ int
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nouveau_finish_page_flip(struct nouveau_channel *chan,
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struct nouveau_page_flip_state *ps)
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{
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struct nouveau_software_chan *swch = chan->engctx[NVOBJ_ENGINE_SW];
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struct drm_device *dev = chan->dev;
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struct nouveau_page_flip_state *s;
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unsigned long flags;
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spin_lock_irqsave(&dev->event_lock, flags);
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if (list_empty(&chan->nvsw.flip)) {
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if (list_empty(&swch->flip)) {
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NV_ERROR(dev, "Unexpected pageflip in channel %d.\n", chan->id);
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spin_unlock_irqrestore(&dev->event_lock, flags);
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return -EINVAL;
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}
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s = list_first_entry(&chan->nvsw.flip,
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struct nouveau_page_flip_state, head);
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s = list_first_entry(&swch->flip, struct nouveau_page_flip_state, head);
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if (s->event) {
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struct drm_pending_vblank_event *e = s->event;
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struct timeval now;
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@ -296,14 +296,6 @@ struct nouveau_channel {
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uint32_t sw_subchannel[8];
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struct nouveau_vma dispc_vma[4];
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struct {
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struct nouveau_gpuobj *vblsem;
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uint32_t vblsem_head;
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uint32_t vblsem_offset;
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uint32_t vblsem_rval;
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struct list_head vbl_wait;
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struct list_head flip;
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} nvsw;
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struct {
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bool active;
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@ -32,6 +32,7 @@
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#include "nouveau_drv.h"
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#include "nouveau_ramht.h"
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#include "nouveau_software.h"
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#include "nouveau_dma.h"
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#define USE_REFCNT(dev) (nouveau_private(dev)->chipset >= 0x10)
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@ -503,11 +504,6 @@ nouveau_fence_channel_init(struct nouveau_channel *chan)
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int ret;
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if (dev_priv->card_type < NV_C0) {
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/* Create an NV_SW object for various sync purposes */
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ret = nouveau_gpuobj_gr_new(chan, NvSw, NV_SW);
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if (ret)
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return ret;
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ret = RING_SPACE(chan, 2);
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if (ret)
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return ret;
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@ -35,6 +35,7 @@
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#include "nouveau_drv.h"
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#include "nouveau_drm.h"
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#include "nouveau_ramht.h"
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#include "nouveau_software.h"
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#include "nouveau_vm.h"
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#include "nv50_display.h"
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@ -133,37 +134,6 @@ nouveau_gpuobj_mthd_call2(struct drm_device *dev, int chid,
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return ret;
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}
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/* NVidia uses context objects to drive drawing operations.
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Context objects can be selected into 8 subchannels in the FIFO,
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and then used via DMA command buffers.
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A context object is referenced by a user defined handle (CARD32). The HW
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looks up graphics objects in a hash table in the instance RAM.
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An entry in the hash table consists of 2 CARD32. The first CARD32 contains
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the handle, the second one a bitfield, that contains the address of the
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object in instance RAM.
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The format of the second CARD32 seems to be:
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NV4 to NV30:
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15: 0 instance_addr >> 4
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17:16 engine (here uses 1 = graphics)
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28:24 channel id (here uses 0)
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31 valid (use 1)
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NV40:
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15: 0 instance_addr >> 4 (maybe 19-0)
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21:20 engine (here uses 1 = graphics)
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I'm unsure about the other bits, but using 0 seems to work.
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The key into the hash table depends on the object handle and channel id and
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is given as:
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*/
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int
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nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
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uint32_t size, int align, uint32_t flags,
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@ -361,34 +331,6 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, u32 pinst, u64 vinst,
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return 0;
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}
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/*
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DMA objects are used to reference a piece of memory in the
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framebuffer, PCI or AGP address space. Each object is 16 bytes big
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and looks as follows:
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entry[0]
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11:0 class (seems like I can always use 0 here)
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12 page table present?
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13 page entry linear?
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15:14 access: 0 rw, 1 ro, 2 wo
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17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP
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31:20 dma adjust (bits 0-11 of the address)
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entry[1]
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dma limit (size of transfer)
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entry[X]
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1 0 readonly, 1 readwrite
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31:12 dma frame address of the page (bits 12-31 of the address)
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entry[N]
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page table terminator, same value as the first pte, as does nvidia
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rivatv uses 0xffffffff
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Non linear page tables need a list of frame addresses afterwards,
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the rivatv project has some info on this.
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The method below creates a DMA object in instance RAM and returns a handle
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to it that can be used to set up context objects.
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*/
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void
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nv50_gpuobj_dma_init(struct nouveau_gpuobj *obj, u32 offset, int class,
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u64 base, u64 size, int target, int access,
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@ -540,82 +482,6 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base,
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return 0;
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}
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/* Context objects in the instance RAM have the following structure.
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* On NV40 they are 32 byte long, on NV30 and smaller 16 bytes.
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NV4 - NV30:
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entry[0]
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11:0 class
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12 chroma key enable
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13 user clip enable
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14 swizzle enable
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17:15 patch config:
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scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre
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18 synchronize enable
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19 endian: 1 big, 0 little
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21:20 dither mode
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23 single step enable
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24 patch status: 0 invalid, 1 valid
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25 context_surface 0: 1 valid
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26 context surface 1: 1 valid
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27 context pattern: 1 valid
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28 context rop: 1 valid
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29,30 context beta, beta4
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entry[1]
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7:0 mono format
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15:8 color format
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31:16 notify instance address
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entry[2]
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15:0 dma 0 instance address
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31:16 dma 1 instance address
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entry[3]
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dma method traps
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NV40:
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No idea what the exact format is. Here's what can be deducted:
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entry[0]:
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11:0 class (maybe uses more bits here?)
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17 user clip enable
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21:19 patch config
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25 patch status valid ?
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entry[1]:
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15:0 DMA notifier (maybe 20:0)
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entry[2]:
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15:0 DMA 0 instance (maybe 20:0)
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24 big endian
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entry[3]:
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15:0 DMA 1 instance (maybe 20:0)
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entry[4]:
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entry[5]:
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set to 0?
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*/
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static int
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nouveau_gpuobj_sw_new(struct nouveau_channel *chan, u32 handle, u16 class)
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{
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struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
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struct nouveau_gpuobj *gpuobj;
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int ret;
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gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
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if (!gpuobj)
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return -ENOMEM;
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gpuobj->dev = chan->dev;
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gpuobj->engine = NVOBJ_ENGINE_SW;
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gpuobj->class = class;
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kref_init(&gpuobj->refcount);
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gpuobj->cinst = 0x40;
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spin_lock(&dev_priv->ramin_lock);
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list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
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spin_unlock(&dev_priv->ramin_lock);
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ret = nouveau_ramht_insert(chan, handle, gpuobj);
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nouveau_gpuobj_ref(NULL, &gpuobj);
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return ret;
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}
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int
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nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
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{
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@ -632,9 +498,6 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
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if (oc->id != class)
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continue;
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if (oc->engine == NVOBJ_ENGINE_SW)
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return nouveau_gpuobj_sw_new(chan, handle, class);
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if (!chan->engctx[oc->engine]) {
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ret = eng->context_new(chan, oc->engine);
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if (ret)
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@ -956,6 +819,17 @@ int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data,
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if (init->handle == ~0)
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return -EINVAL;
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/* compatibility with userspace that assumes 506e for all chipsets */
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if (init->class == 0x506e) {
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init->class = nouveau_software_class(dev);
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if (init->class == 0x906e)
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return 0;
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} else
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if (init->class == 0x906e) {
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NV_ERROR(dev, "906e not supported yet\n");
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return -EINVAL;
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}
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chan = nouveau_channel_get(file_priv, init->channel);
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if (IS_ERR(chan))
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return PTR_ERR(chan);
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68
drivers/gpu/drm/nouveau/nouveau_software.h
Normal file
68
drivers/gpu/drm/nouveau/nouveau_software.h
Normal file
@ -0,0 +1,68 @@
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#ifndef __NOUVEAU_SOFTWARE_H__
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#define __NOUVEAU_SOFTWARE_H__
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struct nouveau_software_priv {
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struct nouveau_exec_engine base;
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struct list_head vblank;
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};
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struct nouveau_software_chan {
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struct list_head flip;
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struct {
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struct list_head list;
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struct nouveau_bo *bo;
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u32 offset;
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u32 value;
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u32 head;
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} vblank;
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};
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static inline void
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nouveau_software_vblank(struct drm_device *dev, int crtc)
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{
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struct nouveau_software_priv *psw = nv_engine(dev, NVOBJ_ENGINE_SW);
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struct nouveau_software_chan *pch, *tmp;
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list_for_each_entry_safe(pch, tmp, &psw->vblank, vblank.list) {
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if (pch->vblank.head != crtc)
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continue;
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nouveau_bo_wr32(pch->vblank.bo, pch->vblank.offset,
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pch->vblank.value);
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list_del(&pch->vblank.list);
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drm_vblank_put(dev, crtc);
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}
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}
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static inline void
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nouveau_software_context_new(struct nouveau_software_chan *pch)
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{
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INIT_LIST_HEAD(&pch->flip);
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}
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static inline void
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nouveau_software_create(struct nouveau_software_priv *psw)
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{
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INIT_LIST_HEAD(&psw->vblank);
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}
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static inline u16
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nouveau_software_class(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (dev_priv->card_type <= NV_04)
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return 0x006e;
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if (dev_priv->card_type <= NV_40)
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return 0x016e;
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if (dev_priv->card_type <= NV_50)
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return 0x506e;
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if (dev_priv->card_type <= NV_E0)
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return 0x906e;
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return 0x0000;
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}
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int nv04_software_create(struct drm_device *);
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int nv50_software_create(struct drm_device *);
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int nvc0_software_create(struct drm_device *);
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#endif
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@ -39,6 +39,7 @@
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#include "nouveau_gpio.h"
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#include "nouveau_pm.h"
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#include "nv50_display.h"
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#include "nouveau_software.h"
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static void nouveau_stub_takedown(struct drm_device *dev) {}
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static int nouveau_stub_init(struct drm_device *dev) { return 0; }
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@ -765,6 +766,26 @@ nouveau_card_init(struct drm_device *dev)
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goto out_ttmvram;
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if (!dev_priv->noaccel) {
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switch (dev_priv->card_type) {
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case NV_04:
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case NV_10:
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case NV_20:
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case NV_30:
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case NV_40:
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nv04_software_create(dev);
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break;
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case NV_50:
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nv50_software_create(dev);
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break;
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case NV_C0:
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case NV_D0:
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case NV_E0:
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nvc0_software_create(dev);
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break;
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default:
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break;
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}
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switch (dev_priv->card_type) {
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case NV_04:
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nv04_graph_create(dev);
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@ -550,28 +550,6 @@ nv04_graph_fini(struct drm_device *dev, int engine, bool suspend)
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return 0;
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}
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static int
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nv04_graph_mthd_set_ref(struct nouveau_channel *chan,
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u32 class, u32 mthd, u32 data)
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{
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atomic_set(&chan->fence.last_sequence_irq, data);
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return 0;
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}
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int
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nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
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u32 class, u32 mthd, u32 data)
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{
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struct drm_device *dev = chan->dev;
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struct nouveau_page_flip_state s;
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if (!nouveau_finish_page_flip(chan, &s))
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nv_set_crtc_base(dev, s.crtc,
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s.offset + s.y * s.pitch + s.x * s.bpp / 8);
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return 0;
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}
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/*
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* Software methods, why they are needed, and how they all work:
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*
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@ -1345,9 +1323,5 @@ nv04_graph_create(struct drm_device *dev)
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NVOBJ_MTHD (dev, 0x005e, 0x0198, nv04_graph_mthd_bind_surf2d);
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NVOBJ_MTHD (dev, 0x005e, 0x02fc, nv04_graph_mthd_set_operation);
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||||
/* nvsw */
|
||||
NVOBJ_CLASS(dev, 0x506e, SW);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0150, nv04_graph_mthd_set_ref);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
|
||||
return 0;
|
||||
}
|
||||
|
||||
153
drivers/gpu/drm/nouveau/nv04_software.c
Normal file
153
drivers/gpu/drm/nouveau/nv04_software.c
Normal file
@ -0,0 +1,153 @@
|
||||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
|
||||
#include "drmP.h"
|
||||
#include "nouveau_drv.h"
|
||||
#include "nouveau_ramht.h"
|
||||
#include "nouveau_software.h"
|
||||
#include "nouveau_hw.h"
|
||||
|
||||
struct nv04_software_priv {
|
||||
struct nouveau_software_priv base;
|
||||
};
|
||||
|
||||
struct nv04_software_chan {
|
||||
struct nouveau_software_chan base;
|
||||
};
|
||||
|
||||
static int
|
||||
mthd_fence(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
|
||||
{
|
||||
atomic_set(&chan->fence.last_sequence_irq, data);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mthd_flip(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
|
||||
{
|
||||
|
||||
struct nouveau_page_flip_state state;
|
||||
|
||||
if (!nouveau_finish_page_flip(chan, &state)) {
|
||||
nv_set_crtc_base(chan->dev, state.crtc, state.offset +
|
||||
state.y * state.pitch +
|
||||
state.x * state.bpp / 8);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv04_software_context_new(struct nouveau_channel *chan, int engine)
|
||||
{
|
||||
struct nv04_software_chan *pch;
|
||||
|
||||
pch = kzalloc(sizeof(*pch), GFP_KERNEL);
|
||||
if (!pch)
|
||||
return -ENOMEM;
|
||||
|
||||
nouveau_software_context_new(&pch->base);
|
||||
atomic_set(&chan->fence.last_sequence_irq, 0);
|
||||
chan->engctx[engine] = pch;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
nv04_software_context_del(struct nouveau_channel *chan, int engine)
|
||||
{
|
||||
struct nv04_software_chan *pch = chan->engctx[engine];
|
||||
chan->engctx[engine] = NULL;
|
||||
kfree(pch);
|
||||
}
|
||||
|
||||
static int
|
||||
nv04_software_object_new(struct nouveau_channel *chan, int engine,
|
||||
u32 handle, u16 class)
|
||||
{
|
||||
struct drm_device *dev = chan->dev;
|
||||
struct nouveau_gpuobj *obj = NULL;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_gpuobj_new(dev, chan, 16, 16, 0, &obj);
|
||||
if (ret)
|
||||
return ret;
|
||||
obj->engine = 0;
|
||||
obj->class = class;
|
||||
|
||||
ret = nouveau_ramht_insert(chan, handle, obj);
|
||||
nouveau_gpuobj_ref(NULL, &obj);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
nv04_software_init(struct drm_device *dev, int engine)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv04_software_fini(struct drm_device *dev, int engine, bool suspend)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
nv04_software_destroy(struct drm_device *dev, int engine)
|
||||
{
|
||||
struct nv04_software_priv *psw = nv_engine(dev, engine);
|
||||
|
||||
NVOBJ_ENGINE_DEL(dev, SW);
|
||||
kfree(psw);
|
||||
}
|
||||
|
||||
int
|
||||
nv04_software_create(struct drm_device *dev)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct nv04_software_priv *psw;
|
||||
|
||||
psw = kzalloc(sizeof(*psw), GFP_KERNEL);
|
||||
if (!psw)
|
||||
return -ENOMEM;
|
||||
|
||||
psw->base.base.destroy = nv04_software_destroy;
|
||||
psw->base.base.init = nv04_software_init;
|
||||
psw->base.base.fini = nv04_software_fini;
|
||||
psw->base.base.context_new = nv04_software_context_new;
|
||||
psw->base.base.context_del = nv04_software_context_del;
|
||||
psw->base.base.object_new = nv04_software_object_new;
|
||||
nouveau_software_create(&psw->base);
|
||||
|
||||
NVOBJ_ENGINE_ADD(dev, SW, &psw->base.base);
|
||||
if (dev_priv->card_type <= NV_04) {
|
||||
NVOBJ_CLASS(dev, 0x006e, SW);
|
||||
NVOBJ_MTHD (dev, 0x006e, 0x0150, mthd_fence);
|
||||
NVOBJ_MTHD (dev, 0x006e, 0x0500, mthd_flip);
|
||||
} else {
|
||||
NVOBJ_CLASS(dev, 0x016e, SW);
|
||||
NVOBJ_MTHD (dev, 0x016e, 0x0500, mthd_flip);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1153,10 +1153,6 @@ nv10_graph_create(struct drm_device *dev)
|
||||
NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
|
||||
nouveau_irq_register(dev, 12, nv10_graph_isr);
|
||||
|
||||
/* nvsw */
|
||||
NVOBJ_CLASS(dev, 0x506e, SW);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
|
||||
|
||||
NVOBJ_CLASS(dev, 0x0030, GR); /* null */
|
||||
NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
|
||||
NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
|
||||
|
||||
@ -796,10 +796,6 @@ nv20_graph_create(struct drm_device *dev)
|
||||
NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
|
||||
nouveau_irq_register(dev, 12, nv20_graph_isr);
|
||||
|
||||
/* nvsw */
|
||||
NVOBJ_CLASS(dev, 0x506e, SW);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
|
||||
|
||||
NVOBJ_CLASS(dev, 0x0030, GR); /* null */
|
||||
NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
|
||||
NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
|
||||
|
||||
@ -439,7 +439,6 @@ nv40_graph_create(struct drm_device *dev)
|
||||
NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
|
||||
nouveau_irq_register(dev, 12, nv40_graph_isr);
|
||||
|
||||
NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
|
||||
NVOBJ_CLASS(dev, 0x0030, GR); /* null */
|
||||
NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
|
||||
NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
|
||||
@ -462,8 +461,5 @@ nv40_graph_create(struct drm_device *dev)
|
||||
else
|
||||
NVOBJ_CLASS(dev, 0x4097, GR);
|
||||
|
||||
/* nvsw */
|
||||
NVOBJ_CLASS(dev, 0x506e, SW);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -645,20 +645,7 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
|
||||
static void
|
||||
nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct nouveau_channel *chan, *tmp;
|
||||
|
||||
list_for_each_entry_safe(chan, tmp, &dev_priv->vbl_waiting,
|
||||
nvsw.vbl_wait) {
|
||||
if (chan->nvsw.vblsem_head != crtc)
|
||||
continue;
|
||||
|
||||
nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
|
||||
chan->nvsw.vblsem_rval);
|
||||
list_del(&chan->nvsw.vbl_wait);
|
||||
drm_vblank_put(dev, crtc);
|
||||
}
|
||||
|
||||
nouveau_software_vblank(dev, crtc);
|
||||
drm_handle_vblank(dev, crtc);
|
||||
}
|
||||
|
||||
|
||||
@ -33,6 +33,7 @@
|
||||
#include "nouveau_dma.h"
|
||||
#include "nouveau_reg.h"
|
||||
#include "nouveau_crtc.h"
|
||||
#include "nouveau_software.h"
|
||||
#include "nv50_evo.h"
|
||||
|
||||
struct nv50_display_crtc {
|
||||
|
||||
@ -333,70 +333,6 @@ nv50_graph_context_switch(struct drm_device *dev)
|
||||
NV40_PGRAPH_INTR_EN) | NV_PGRAPH_INTR_CONTEXT_SWITCH);
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_graph_nvsw_dma_vblsem(struct nouveau_channel *chan,
|
||||
u32 class, u32 mthd, u32 data)
|
||||
{
|
||||
struct nouveau_gpuobj *gpuobj;
|
||||
|
||||
gpuobj = nouveau_ramht_find(chan, data);
|
||||
if (!gpuobj)
|
||||
return -ENOENT;
|
||||
|
||||
if (nouveau_notifier_offset(gpuobj, NULL))
|
||||
return -EINVAL;
|
||||
|
||||
chan->nvsw.vblsem = gpuobj;
|
||||
chan->nvsw.vblsem_offset = ~0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_graph_nvsw_vblsem_offset(struct nouveau_channel *chan,
|
||||
u32 class, u32 mthd, u32 data)
|
||||
{
|
||||
if (nouveau_notifier_offset(chan->nvsw.vblsem, &data))
|
||||
return -ERANGE;
|
||||
|
||||
chan->nvsw.vblsem_offset = data >> 2;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_graph_nvsw_vblsem_release_val(struct nouveau_channel *chan,
|
||||
u32 class, u32 mthd, u32 data)
|
||||
{
|
||||
chan->nvsw.vblsem_rval = data;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_graph_nvsw_vblsem_release(struct nouveau_channel *chan,
|
||||
u32 class, u32 mthd, u32 data)
|
||||
{
|
||||
struct drm_device *dev = chan->dev;
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (!chan->nvsw.vblsem || chan->nvsw.vblsem_offset == ~0 || data > 1)
|
||||
return -EINVAL;
|
||||
|
||||
drm_vblank_get(dev, data);
|
||||
|
||||
chan->nvsw.vblsem_head = data;
|
||||
list_add(&chan->nvsw.vbl_wait, &dev_priv->vbl_waiting);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_graph_nvsw_mthd_page_flip(struct nouveau_channel *chan,
|
||||
u32 class, u32 mthd, u32 data)
|
||||
{
|
||||
nouveau_finish_page_flip(chan, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
nv50_graph_tlb_flush(struct drm_device *dev, int engine)
|
||||
{
|
||||
@ -1018,14 +954,6 @@ nv50_graph_create(struct drm_device *dev)
|
||||
|
||||
nouveau_irq_register(dev, 12, nv50_graph_isr);
|
||||
|
||||
/* NVSW really doesn't live here... */
|
||||
NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0500, nv50_graph_nvsw_mthd_page_flip);
|
||||
|
||||
NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
|
||||
NVOBJ_CLASS(dev, 0x0030, GR); /* null */
|
||||
NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
|
||||
|
||||
190
drivers/gpu/drm/nouveau/nv50_software.c
Normal file
190
drivers/gpu/drm/nouveau/nv50_software.c
Normal file
@ -0,0 +1,190 @@
|
||||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
|
||||
#include "drmP.h"
|
||||
#include "nouveau_drv.h"
|
||||
#include "nouveau_ramht.h"
|
||||
#include "nouveau_software.h"
|
||||
|
||||
struct nv50_software_priv {
|
||||
struct nouveau_software_priv base;
|
||||
};
|
||||
|
||||
struct nv50_software_chan {
|
||||
struct nouveau_software_chan base;
|
||||
struct {
|
||||
struct nouveau_gpuobj *object;
|
||||
} vblank;
|
||||
};
|
||||
|
||||
static int
|
||||
mthd_dma_vblsem(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
|
||||
{
|
||||
struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
|
||||
struct nouveau_gpuobj *gpuobj;
|
||||
|
||||
gpuobj = nouveau_ramht_find(chan, data);
|
||||
if (!gpuobj)
|
||||
return -ENOENT;
|
||||
|
||||
if (nouveau_notifier_offset(gpuobj, NULL))
|
||||
return -EINVAL;
|
||||
|
||||
pch->vblank.object = gpuobj;
|
||||
pch->base.vblank.offset = ~0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mthd_vblsem_offset(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
|
||||
{
|
||||
struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
|
||||
|
||||
if (nouveau_notifier_offset(pch->vblank.object, &data))
|
||||
return -ERANGE;
|
||||
|
||||
pch->base.vblank.offset = data >> 2;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mthd_vblsem_value(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
|
||||
{
|
||||
struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
|
||||
pch->base.vblank.value = data;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mthd_vblsem_release(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
|
||||
{
|
||||
struct nv50_software_priv *psw = nv_engine(chan->dev, NVOBJ_ENGINE_SW);
|
||||
struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW];
|
||||
struct drm_device *dev = chan->dev;
|
||||
|
||||
if (!pch->vblank.object || pch->base.vblank.offset == ~0 || data > 1)
|
||||
return -EINVAL;
|
||||
|
||||
drm_vblank_get(dev, data);
|
||||
|
||||
pch->base.vblank.head = data;
|
||||
list_add(&pch->base.vblank.list, &psw->base.vblank);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mthd_flip(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
|
||||
{
|
||||
nouveau_finish_page_flip(chan, NULL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_software_context_new(struct nouveau_channel *chan, int engine)
|
||||
{
|
||||
struct nv50_software_chan *pch;
|
||||
|
||||
pch = kzalloc(sizeof(*pch), GFP_KERNEL);
|
||||
if (!pch)
|
||||
return -ENOMEM;
|
||||
|
||||
nouveau_software_context_new(&pch->base);
|
||||
pch->base.vblank.bo = chan->notifier_bo;
|
||||
|
||||
chan->engctx[engine] = pch;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_software_context_del(struct nouveau_channel *chan, int engine)
|
||||
{
|
||||
struct nv50_software_chan *pch = chan->engctx[engine];
|
||||
chan->engctx[engine] = NULL;
|
||||
kfree(pch);
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_software_object_new(struct nouveau_channel *chan, int engine,
|
||||
u32 handle, u16 class)
|
||||
{
|
||||
struct drm_device *dev = chan->dev;
|
||||
struct nouveau_gpuobj *obj = NULL;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_gpuobj_new(dev, chan, 16, 16, 0, &obj);
|
||||
if (ret)
|
||||
return ret;
|
||||
obj->engine = 0;
|
||||
obj->class = class;
|
||||
|
||||
ret = nouveau_ramht_insert(chan, handle, obj);
|
||||
nouveau_gpuobj_ref(NULL, &obj);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_software_init(struct drm_device *dev, int engine)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_software_fini(struct drm_device *dev, int engine, bool suspend)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_software_destroy(struct drm_device *dev, int engine)
|
||||
{
|
||||
struct nv50_software_priv *psw = nv_engine(dev, engine);
|
||||
|
||||
NVOBJ_ENGINE_DEL(dev, SW);
|
||||
kfree(psw);
|
||||
}
|
||||
|
||||
int
|
||||
nv50_software_create(struct drm_device *dev)
|
||||
{
|
||||
struct nv50_software_priv *psw = kzalloc(sizeof(*psw), GFP_KERNEL);
|
||||
if (!psw)
|
||||
return -ENOMEM;
|
||||
|
||||
psw->base.base.destroy = nv50_software_destroy;
|
||||
psw->base.base.init = nv50_software_init;
|
||||
psw->base.base.fini = nv50_software_fini;
|
||||
psw->base.base.context_new = nv50_software_context_new;
|
||||
psw->base.base.context_del = nv50_software_context_del;
|
||||
psw->base.base.object_new = nv50_software_object_new;
|
||||
nouveau_software_create(&psw->base);
|
||||
|
||||
NVOBJ_ENGINE_ADD(dev, SW, &psw->base.base);
|
||||
NVOBJ_CLASS(dev, 0x506e, SW);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x018c, mthd_dma_vblsem);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0400, mthd_vblsem_offset);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0404, mthd_vblsem_value);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0408, mthd_vblsem_release);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0500, mthd_flip);
|
||||
return 0;
|
||||
}
|
||||
@ -278,7 +278,6 @@ nvc0_fifo_create(struct drm_device *dev)
|
||||
goto error;
|
||||
|
||||
nouveau_irq_register(dev, 8, nvc0_fifo_isr);
|
||||
NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
|
||||
return 0;
|
||||
|
||||
error:
|
||||
|
||||
106
drivers/gpu/drm/nouveau/nvc0_software.c
Normal file
106
drivers/gpu/drm/nouveau/nvc0_software.c
Normal file
@ -0,0 +1,106 @@
|
||||
/*
|
||||
* Copyright 2012 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
|
||||
#include "drmP.h"
|
||||
#include "nouveau_drv.h"
|
||||
#include "nouveau_ramht.h"
|
||||
#include "nouveau_software.h"
|
||||
|
||||
struct nvc0_software_priv {
|
||||
struct nouveau_software_priv base;
|
||||
};
|
||||
|
||||
struct nvc0_software_chan {
|
||||
struct nouveau_software_chan base;
|
||||
};
|
||||
|
||||
static int
|
||||
nvc0_software_context_new(struct nouveau_channel *chan, int engine)
|
||||
{
|
||||
struct nvc0_software_chan *pch;
|
||||
|
||||
pch = kzalloc(sizeof(*pch), GFP_KERNEL);
|
||||
if (!pch)
|
||||
return -ENOMEM;
|
||||
|
||||
nouveau_software_context_new(&pch->base);
|
||||
chan->engctx[engine] = pch;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
nvc0_software_context_del(struct nouveau_channel *chan, int engine)
|
||||
{
|
||||
struct nvc0_software_chan *pch = chan->engctx[engine];
|
||||
chan->engctx[engine] = NULL;
|
||||
kfree(pch);
|
||||
}
|
||||
|
||||
static int
|
||||
nvc0_software_object_new(struct nouveau_channel *chan, int engine,
|
||||
u32 handle, u16 class)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nvc0_software_init(struct drm_device *dev, int engine)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nvc0_software_fini(struct drm_device *dev, int engine, bool suspend)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
nvc0_software_destroy(struct drm_device *dev, int engine)
|
||||
{
|
||||
struct nvc0_software_priv *psw = nv_engine(dev, engine);
|
||||
|
||||
NVOBJ_ENGINE_DEL(dev, SW);
|
||||
kfree(psw);
|
||||
}
|
||||
|
||||
int
|
||||
nvc0_software_create(struct drm_device *dev)
|
||||
{
|
||||
struct nvc0_software_priv *psw = kzalloc(sizeof(*psw), GFP_KERNEL);
|
||||
if (!psw)
|
||||
return -ENOMEM;
|
||||
|
||||
psw->base.base.destroy = nvc0_software_destroy;
|
||||
psw->base.base.init = nvc0_software_init;
|
||||
psw->base.base.fini = nvc0_software_fini;
|
||||
psw->base.base.context_new = nvc0_software_context_new;
|
||||
psw->base.base.context_del = nvc0_software_context_del;
|
||||
psw->base.base.object_new = nvc0_software_object_new;
|
||||
nouveau_software_create(&psw->base);
|
||||
|
||||
NVOBJ_ENGINE_ADD(dev, SW, &psw->base.base);
|
||||
NVOBJ_CLASS(dev, 0x906e, SW);
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user