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ARM: dts: socfpga: add timer resets for SoCFPGA platform
Add the resets property for all the timers on the Cyclone5/Arria5/Arria10 platforms. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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@ -849,6 +849,8 @@ timer0: timer0@ffc08000 {
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reg = <0xffc08000 0x1000>;
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clocks = <&l4_sp_clk>;
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clock-names = "timer";
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resets = <&rst SPTIMER0_RESET>;
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reset-names = "timer";
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};
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timer1: timer1@ffc09000 {
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@ -857,6 +859,8 @@ timer1: timer1@ffc09000 {
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reg = <0xffc09000 0x1000>;
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clocks = <&l4_sp_clk>;
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clock-names = "timer";
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resets = <&rst SPTIMER1_RESET>;
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reset-names = "timer";
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};
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timer2: timer2@ffd00000 {
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@ -865,6 +869,8 @@ timer2: timer2@ffd00000 {
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reg = <0xffd00000 0x1000>;
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clocks = <&osc1>;
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clock-names = "timer";
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resets = <&rst OSC1TIMER0_RESET>;
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reset-names = "timer";
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};
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timer3: timer3@ffd01000 {
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@ -873,6 +879,8 @@ timer3: timer3@ffd01000 {
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reg = <0xffd01000 0x1000>;
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clocks = <&osc1>;
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clock-names = "timer";
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resets = <&rst OSC1TIMER1_RESET>;
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reset-names = "timer";
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};
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uart0: serial0@ffc02000 {
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@ -786,6 +786,8 @@ timer0: timer0@ffc02700 {
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reg = <0xffc02700 0x100>;
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clocks = <&l4_sp_clk>;
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clock-names = "timer";
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resets = <&rst SPTIMER0_RESET>;
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reset-names = "timer";
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};
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timer1: timer1@ffc02800 {
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@ -794,6 +796,8 @@ timer1: timer1@ffc02800 {
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reg = <0xffc02800 0x100>;
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clocks = <&l4_sp_clk>;
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clock-names = "timer";
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resets = <&rst SPTIMER1_RESET>;
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reset-names = "timer";
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};
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timer2: timer2@ffd00000 {
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@ -802,6 +806,8 @@ timer2: timer2@ffd00000 {
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reg = <0xffd00000 0x100>;
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clocks = <&l4_sys_free_clk>;
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clock-names = "timer";
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resets = <&rst L4SYSTIMER0_RESET>;
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reset-names = "timer";
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};
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timer3: timer3@ffd00100 {
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@ -810,6 +816,8 @@ timer3: timer3@ffd00100 {
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reg = <0xffd01000 0x100>;
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clocks = <&l4_sys_free_clk>;
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clock-names = "timer";
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resets = <&rst L4SYSTIMER1_RESET>;
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reset-names = "timer";
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};
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uart0: serial0@ffc02000 {
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