mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 20:56:41 +07:00
Merge branch 'octeontx2-af-NPC-parser-and-NIX-blocks-initialization'
Sunil Goutham says: ==================== octeontx2-af: NPC parser and NIX blocks initialization This patchset is a continuation to earlier submitted two patch series to add a new driver for Marvell's OcteonTX2 SOC's Resource virtualization unit (RVU) admin function driver. 1. octeontx2-af: Add RVU Admin Function driver https://www.spinics.net/lists/netdev/msg528272.html 2. octeontx2-af: NPA and NIX blocks initialization https://www.spinics.net/lists/netdev/msg529163.html This patch series adds more NIX block configuration logic and additionally adds NPC block parser profile configuration. In brief below is what this series adds. NIX block: - Support for PF/VF to allocate/free transmit scheduler queues, maintenance and their configuration. - Adds support for packet replication lists, only broadcast packets is covered for now. - Defines few RSS flow algorithms for HW to distribute packets. This is not the hash algorithsm (i.e toeplitz or crc32), here SW defines what fields in packet should HW take and calculate the hash. - Support for PF/VF to configure VTAG strip and capture capabilities. - Reset NIXLF statastics. NPC block: This block has multiple parser engines which support packet parsing at multiple layers and generates a parse result which is further used to generate a key. Based on packet field offsets in the key, SW can install packet forwarding rules. This patch series adds - Initial parser profile to be programmed into parser engines. - Default forwarding rules to forward packets to different logical interfaces having a NIXLF attached. - Support for promiscuous and multicast modes. Changes from v1: 1 Fixed kernel build failure when compiled with BIG_ENDIAN enabled. - Reported by Kbuild test robot 2 Fixed a warning observed when kernel is built with -Wunused-but-set-variable ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
1fad1fe40e
@ -7,4 +7,5 @@ obj-$(CONFIG_OCTEONTX2_MBOX) += octeontx2_mbox.o
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obj-$(CONFIG_OCTEONTX2_AF) += octeontx2_af.o
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octeontx2_mbox-y := mbox.o
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octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o
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octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \
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rvu_reg.o rvu_npc.o
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@ -186,6 +186,18 @@ u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id)
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}
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EXPORT_SYMBOL(cgx_lmac_addr_get);
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int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind)
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{
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struct cgx *cgx = cgxd;
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if (!cgx || lmac_id >= cgx->lmac_count)
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return -ENODEV;
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cgx_write(cgx, lmac_id, CGXX_CMRX_RX_ID_MAP, (pkind & 0x3F));
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return 0;
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}
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EXPORT_SYMBOL(cgx_set_pkind);
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static inline u8 cgx_get_lmac_type(struct cgx *cgx, int lmac_id)
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{
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u64 cfg;
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@ -97,6 +97,7 @@ extern struct pci_driver cgx_driver;
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int cgx_get_cgx_cnt(void);
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int cgx_get_lmac_cnt(void *cgxd);
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void *cgx_get_pdata(int cgx_id);
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int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
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int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
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int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
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int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
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@ -143,6 +143,34 @@ enum nix_scheduler {
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NIX_TXSCH_LVL_CNT = 0x5,
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};
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/* NIX RX action operation*/
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#define NIX_RX_ACTIONOP_DROP (0x0ull)
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#define NIX_RX_ACTIONOP_UCAST (0x1ull)
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#define NIX_RX_ACTIONOP_UCAST_IPSEC (0x2ull)
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#define NIX_RX_ACTIONOP_MCAST (0x3ull)
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#define NIX_RX_ACTIONOP_RSS (0x4ull)
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/* NIX TX action operation*/
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#define NIX_TX_ACTIONOP_DROP (0x0ull)
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#define NIX_TX_ACTIONOP_UCAST_DEFAULT (0x1ull)
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#define NIX_TX_ACTIONOP_UCAST_CHAN (0x2ull)
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#define NIX_TX_ACTIONOP_MCAST (0x3ull)
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#define NIX_TX_ACTIONOP_DROP_VIOL (0x5ull)
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#define NPC_MCAM_KEY_X1 0
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#define NPC_MCAM_KEY_X2 1
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#define NPC_MCAM_KEY_X4 2
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#define NIX_INTF_RX 0
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#define NIX_INTF_TX 1
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#define NIX_INTF_TYPE_CGX 0
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#define NIX_INTF_TYPE_LBK 1
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#define MAX_LMAC_PKIND 12
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#define NIX_LINK_CGX_LMAC(a, b) (0 + 4 * (a) + (b))
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#define NIX_CHAN_CGX_LMAC_CHX(a, b, c) (0x800 + 0x100 * (a) + 0x10 * (b) + (c))
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/* NIX LSO format indices.
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* As of now TSO is the only one using, so statically assigning indices.
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*/
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@ -158,4 +186,26 @@ enum nix_scheduler {
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#define DEFAULT_RSS_CONTEXT_GROUP 0
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#define MAX_RSS_INDIR_TBL_SIZE 256 /* 1 << Max adder bits */
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/* NIX flow tag, key type flags */
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#define FLOW_KEY_TYPE_PORT BIT(0)
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#define FLOW_KEY_TYPE_IPV4 BIT(1)
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#define FLOW_KEY_TYPE_IPV6 BIT(2)
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#define FLOW_KEY_TYPE_TCP BIT(3)
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#define FLOW_KEY_TYPE_UDP BIT(4)
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#define FLOW_KEY_TYPE_SCTP BIT(5)
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/* NIX flow tag algorithm indices, max is 31 */
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enum {
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FLOW_KEY_ALG_PORT,
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FLOW_KEY_ALG_IP,
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FLOW_KEY_ALG_TCP,
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FLOW_KEY_ALG_UDP,
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FLOW_KEY_ALG_SCTP,
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FLOW_KEY_ALG_TCP_UDP,
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FLOW_KEY_ALG_TCP_SCTP,
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FLOW_KEY_ALG_UDP_SCTP,
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FLOW_KEY_ALG_TCP_UDP_SCTP,
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FLOW_KEY_ALG_MAX,
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};
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#endif /* COMMON_H */
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@ -15,6 +15,7 @@
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#include <linux/sizes.h>
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#include "rvu_struct.h"
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#include "common.h"
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#define MBOX_SIZE SZ_64K
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@ -151,7 +152,15 @@ M(NPA_HWCTX_DISABLE, 0x403, hwctx_disable_req, msg_rsp) \
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M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc_req, nix_lf_alloc_rsp) \
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M(NIX_LF_FREE, 0x8001, msg_req, msg_rsp) \
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M(NIX_AQ_ENQ, 0x8002, nix_aq_enq_req, nix_aq_enq_rsp) \
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M(NIX_HWCTX_DISABLE, 0x8003, hwctx_disable_req, msg_rsp)
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M(NIX_HWCTX_DISABLE, 0x8003, hwctx_disable_req, msg_rsp) \
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M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
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M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free_req, msg_rsp) \
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M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_config, msg_rsp) \
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M(NIX_STATS_RST, 0x8007, msg_req, msg_rsp) \
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M(NIX_VTAG_CFG, 0x8008, nix_vtag_config, msg_rsp) \
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M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, msg_rsp) \
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M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, msg_rsp) \
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M(NIX_SET_RX_MODE, 0x800b, nix_rx_mode, msg_rsp)
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/* Messages initiated by AF (range 0xC00 - 0xDFF) */
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#define MBOX_UP_CGX_MESSAGES \
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@ -376,6 +385,10 @@ struct nix_lf_alloc_req {
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struct nix_lf_alloc_rsp {
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struct mbox_msghdr hdr;
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u16 sqb_size;
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u16 rx_chan_base;
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u16 tx_chan_base;
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u8 rx_chan_cnt; /* total number of RX channels */
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u8 tx_chan_cnt; /* total number of TX channels */
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u8 lso_tsov4_idx;
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u8 lso_tsov6_idx;
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u8 mac_addr[ETH_ALEN];
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@ -414,4 +427,99 @@ struct nix_aq_enq_rsp {
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};
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};
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/* Tx scheduler/shaper mailbox messages */
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#define MAX_TXSCHQ_PER_FUNC 128
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struct nix_txsch_alloc_req {
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struct mbox_msghdr hdr;
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/* Scheduler queue count request at each level */
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u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
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u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
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};
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struct nix_txsch_alloc_rsp {
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struct mbox_msghdr hdr;
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/* Scheduler queue count allocated at each level */
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u16 schq_contig[NIX_TXSCH_LVL_CNT];
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u16 schq[NIX_TXSCH_LVL_CNT];
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/* Scheduler queue list allocated at each level */
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u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
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u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
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};
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struct nix_txsch_free_req {
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struct mbox_msghdr hdr;
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#define TXSCHQ_FREE_ALL BIT_ULL(0)
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u16 flags;
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/* Scheduler queue level to be freed */
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u16 schq_lvl;
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/* List of scheduler queues to be freed */
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u16 schq;
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};
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struct nix_txschq_config {
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struct mbox_msghdr hdr;
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u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
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#define TXSCHQ_IDX_SHIFT 16
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#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
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#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
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u8 num_regs;
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#define MAX_REGS_PER_MBOX_MSG 20
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u64 reg[MAX_REGS_PER_MBOX_MSG];
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u64 regval[MAX_REGS_PER_MBOX_MSG];
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};
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struct nix_vtag_config {
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struct mbox_msghdr hdr;
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u8 vtag_size;
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/* cfg_type is '0' for tx vlan cfg
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* cfg_type is '1' for rx vlan cfg
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*/
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u8 cfg_type;
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union {
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/* valid when cfg_type is '0' */
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struct {
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/* tx vlan0 tag(C-VLAN) */
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u64 vlan0;
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/* tx vlan1 tag(S-VLAN) */
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u64 vlan1;
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/* insert tx vlan tag */
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u8 insert_vlan :1;
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/* insert tx double vlan tag */
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u8 double_vlan :1;
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} tx;
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/* valid when cfg_type is '1' */
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struct {
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/* rx vtag type index */
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u8 vtag_type;
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/* rx vtag strip */
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u8 strip_vtag :1;
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/* rx vtag capture */
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u8 capture_vtag :1;
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} rx;
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};
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};
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struct nix_rss_flowkey_cfg {
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struct mbox_msghdr hdr;
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int mcam_index; /* MCAM entry index to modify */
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u32 flowkey_cfg; /* Flowkey types selected */
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u8 group; /* RSS context or group */
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};
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struct nix_set_mac_addr {
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struct mbox_msghdr hdr;
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u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
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};
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struct nix_rx_mode {
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struct mbox_msghdr hdr;
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#define NIX_RX_MODE_UCAST BIT(0)
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#define NIX_RX_MODE_PROMISC BIT(1)
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#define NIX_RX_MODE_ALLMULTI BIT(2)
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u16 mode;
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};
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#endif /* MBOX_H */
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262
drivers/net/ethernet/marvell/octeontx2/af/npc.h
Normal file
262
drivers/net/ethernet/marvell/octeontx2/af/npc.h
Normal file
@ -0,0 +1,262 @@
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/* SPDX-License-Identifier: GPL-2.0
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* Marvell OcteonTx2 RVU Admin Function driver
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef NPC_H
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#define NPC_H
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enum NPC_LID_E {
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NPC_LID_LA = 0,
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NPC_LID_LB,
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NPC_LID_LC,
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NPC_LID_LD,
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NPC_LID_LE,
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NPC_LID_LF,
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NPC_LID_LG,
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NPC_LID_LH,
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};
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#define NPC_LT_NA 0
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enum npc_kpu_la_ltype {
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NPC_LT_LA_8023 = 1,
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NPC_LT_LA_ETHER,
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};
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enum npc_kpu_lb_ltype {
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NPC_LT_LB_ETAG = 1,
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NPC_LT_LB_CTAG,
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NPC_LT_LB_STAG,
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NPC_LT_LB_BTAG,
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NPC_LT_LB_QINQ,
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NPC_LT_LB_ITAG,
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};
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enum npc_kpu_lc_ltype {
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NPC_LT_LC_IP = 1,
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NPC_LT_LC_IP6,
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NPC_LT_LC_ARP,
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NPC_LT_LC_RARP,
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NPC_LT_LC_MPLS,
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NPC_LT_LC_NSH,
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NPC_LT_LC_PTP,
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NPC_LT_LC_FCOE,
|
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};
|
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|
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/* Don't modify Ltypes upto SCTP, otherwise it will
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* effect flow tag calculation and thus RSS.
|
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*/
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enum npc_kpu_ld_ltype {
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NPC_LT_LD_TCP = 1,
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NPC_LT_LD_UDP,
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NPC_LT_LD_ICMP,
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NPC_LT_LD_SCTP,
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NPC_LT_LD_IGMP,
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NPC_LT_LD_ICMP6,
|
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NPC_LT_LD_ESP,
|
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NPC_LT_LD_AH,
|
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NPC_LT_LD_GRE,
|
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NPC_LT_LD_GRE_MPLS,
|
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NPC_LT_LD_GRE_NSH,
|
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NPC_LT_LD_TU_MPLS,
|
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};
|
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|
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enum npc_kpu_le_ltype {
|
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NPC_LT_LE_TU_ETHER = 1,
|
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NPC_LT_LE_TU_PPP,
|
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NPC_LT_LE_TU_MPLS_IN_NSH,
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NPC_LT_LE_TU_3RD_NSH,
|
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};
|
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|
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enum npc_kpu_lf_ltype {
|
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NPC_LT_LF_TU_IP = 1,
|
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NPC_LT_LF_TU_IP6,
|
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NPC_LT_LF_TU_ARP,
|
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NPC_LT_LF_TU_MPLS_IP,
|
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NPC_LT_LF_TU_MPLS_IP6,
|
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NPC_LT_LF_TU_MPLS_ETHER,
|
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};
|
||||
|
||||
enum npc_kpu_lg_ltype {
|
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NPC_LT_LG_TU_TCP = 1,
|
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NPC_LT_LG_TU_UDP,
|
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NPC_LT_LG_TU_SCTP,
|
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NPC_LT_LG_TU_ICMP,
|
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NPC_LT_LG_TU_IGMP,
|
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NPC_LT_LG_TU_ICMP6,
|
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NPC_LT_LG_TU_ESP,
|
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NPC_LT_LG_TU_AH,
|
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};
|
||||
|
||||
enum npc_kpu_lh_ltype {
|
||||
NPC_LT_LH_TCP_DATA = 1,
|
||||
NPC_LT_LH_HTTP_DATA,
|
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NPC_LT_LH_HTTPS_DATA,
|
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NPC_LT_LH_PPTP_DATA,
|
||||
NPC_LT_LH_UDP_DATA,
|
||||
};
|
||||
|
||||
struct npc_kpu_profile_cam {
|
||||
u8 state;
|
||||
u8 state_mask;
|
||||
u16 dp0;
|
||||
u16 dp0_mask;
|
||||
u16 dp1;
|
||||
u16 dp1_mask;
|
||||
u16 dp2;
|
||||
u16 dp2_mask;
|
||||
};
|
||||
|
||||
struct npc_kpu_profile_action {
|
||||
u8 errlev;
|
||||
u8 errcode;
|
||||
u8 dp0_offset;
|
||||
u8 dp1_offset;
|
||||
u8 dp2_offset;
|
||||
u8 bypass_count;
|
||||
u8 parse_done;
|
||||
u8 next_state;
|
||||
u8 ptr_advance;
|
||||
u8 cap_ena;
|
||||
u8 lid;
|
||||
u8 ltype;
|
||||
u8 flags;
|
||||
u8 offset;
|
||||
u8 mask;
|
||||
u8 right;
|
||||
u8 shift;
|
||||
};
|
||||
|
||||
struct npc_kpu_profile {
|
||||
int cam_entries;
|
||||
int action_entries;
|
||||
struct npc_kpu_profile_cam *cam;
|
||||
struct npc_kpu_profile_action *action;
|
||||
};
|
||||
|
||||
/* NPC KPU register formats */
|
||||
struct npc_kpu_cam {
|
||||
#if defined(__BIG_ENDIAN_BITFIELD)
|
||||
u64 rsvd_63_56 : 8;
|
||||
u64 state : 8;
|
||||
u64 dp2_data : 16;
|
||||
u64 dp1_data : 16;
|
||||
u64 dp0_data : 16;
|
||||
#else
|
||||
u64 dp0_data : 16;
|
||||
u64 dp1_data : 16;
|
||||
u64 dp2_data : 16;
|
||||
u64 state : 8;
|
||||
u64 rsvd_63_56 : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct npc_kpu_action0 {
|
||||
#if defined(__BIG_ENDIAN_BITFIELD)
|
||||
u64 rsvd_63_57 : 7;
|
||||
u64 byp_count : 3;
|
||||
u64 capture_ena : 1;
|
||||
u64 parse_done : 1;
|
||||
u64 next_state : 8;
|
||||
u64 rsvd_43 : 1;
|
||||
u64 capture_lid : 3;
|
||||
u64 capture_ltype : 4;
|
||||
u64 capture_flags : 8;
|
||||
u64 ptr_advance : 8;
|
||||
u64 var_len_offset : 8;
|
||||
u64 var_len_mask : 8;
|
||||
u64 var_len_right : 1;
|
||||
u64 var_len_shift : 3;
|
||||
#else
|
||||
u64 var_len_shift : 3;
|
||||
u64 var_len_right : 1;
|
||||
u64 var_len_mask : 8;
|
||||
u64 var_len_offset : 8;
|
||||
u64 ptr_advance : 8;
|
||||
u64 capture_flags : 8;
|
||||
u64 capture_ltype : 4;
|
||||
u64 capture_lid : 3;
|
||||
u64 rsvd_43 : 1;
|
||||
u64 next_state : 8;
|
||||
u64 parse_done : 1;
|
||||
u64 capture_ena : 1;
|
||||
u64 byp_count : 3;
|
||||
u64 rsvd_63_57 : 7;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct npc_kpu_action1 {
|
||||
#if defined(__BIG_ENDIAN_BITFIELD)
|
||||
u64 rsvd_63_36 : 28;
|
||||
u64 errlev : 4;
|
||||
u64 errcode : 8;
|
||||
u64 dp2_offset : 8;
|
||||
u64 dp1_offset : 8;
|
||||
u64 dp0_offset : 8;
|
||||
#else
|
||||
u64 dp0_offset : 8;
|
||||
u64 dp1_offset : 8;
|
||||
u64 dp2_offset : 8;
|
||||
u64 errcode : 8;
|
||||
u64 errlev : 4;
|
||||
u64 rsvd_63_36 : 28;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct npc_kpu_pkind_cpi_def {
|
||||
#if defined(__BIG_ENDIAN_BITFIELD)
|
||||
u64 ena : 1;
|
||||
u64 rsvd_62_59 : 4;
|
||||
u64 lid : 3;
|
||||
u64 ltype_match : 4;
|
||||
u64 ltype_mask : 4;
|
||||
u64 flags_match : 8;
|
||||
u64 flags_mask : 8;
|
||||
u64 add_offset : 8;
|
||||
u64 add_mask : 8;
|
||||
u64 rsvd_15 : 1;
|
||||
u64 add_shift : 3;
|
||||
u64 rsvd_11_10 : 2;
|
||||
u64 cpi_base : 10;
|
||||
#else
|
||||
u64 cpi_base : 10;
|
||||
u64 rsvd_11_10 : 2;
|
||||
u64 add_shift : 3;
|
||||
u64 rsvd_15 : 1;
|
||||
u64 add_mask : 8;
|
||||
u64 add_offset : 8;
|
||||
u64 flags_mask : 8;
|
||||
u64 flags_match : 8;
|
||||
u64 ltype_mask : 4;
|
||||
u64 ltype_match : 4;
|
||||
u64 lid : 3;
|
||||
u64 rsvd_62_59 : 4;
|
||||
u64 ena : 1;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct nix_rx_action {
|
||||
#if defined(__BIG_ENDIAN_BITFIELD)
|
||||
u64 rsvd_63_61 :3;
|
||||
u64 flow_key_alg :5;
|
||||
u64 match_id :16;
|
||||
u64 index :20;
|
||||
u64 pf_func :16;
|
||||
u64 op :4;
|
||||
#else
|
||||
u64 op :4;
|
||||
u64 pf_func :16;
|
||||
u64 index :20;
|
||||
u64 match_id :16;
|
||||
u64 flow_key_alg :5;
|
||||
u64 rsvd_63_61 :3;
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* NPC_H */
|
||||
5709
drivers/net/ethernet/marvell/octeontx2/af/npc_profile.h
Normal file
5709
drivers/net/ethernet/marvell/octeontx2/af/npc_profile.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -80,7 +80,7 @@ int rvu_alloc_rsrc(struct rsrc_bmap *rsrc)
|
||||
return id;
|
||||
}
|
||||
|
||||
static int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc)
|
||||
int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc)
|
||||
{
|
||||
int start;
|
||||
|
||||
@ -105,7 +105,7 @@ static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start)
|
||||
bitmap_clear(rsrc->bmap, start, nrsrc);
|
||||
}
|
||||
|
||||
static bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc)
|
||||
bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc)
|
||||
{
|
||||
int start;
|
||||
|
||||
@ -180,6 +180,9 @@ int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc)
|
||||
bool is_pf;
|
||||
|
||||
switch (blktype) {
|
||||
case BLKTYPE_NPC:
|
||||
blkaddr = BLKADDR_NPC;
|
||||
goto exit;
|
||||
case BLKTYPE_NPA:
|
||||
blkaddr = BLKADDR_NPA;
|
||||
goto exit;
|
||||
@ -566,6 +569,7 @@ static void rvu_free_hw_resources(struct rvu *rvu)
|
||||
u64 cfg;
|
||||
|
||||
rvu_npa_freemem(rvu);
|
||||
rvu_npc_freemem(rvu);
|
||||
rvu_nix_freemem(rvu);
|
||||
|
||||
/* Free block LF bitmaps */
|
||||
@ -771,6 +775,10 @@ static int rvu_setup_hw_resources(struct rvu *rvu)
|
||||
rvu_scan_block(rvu, block);
|
||||
}
|
||||
|
||||
err = rvu_npc_init(rvu);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
err = rvu_npa_init(rvu);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
@ -59,6 +59,32 @@ struct rvu_block {
|
||||
unsigned char name[NAME_SIZE];
|
||||
};
|
||||
|
||||
struct nix_mcast {
|
||||
struct qmem *mce_ctx;
|
||||
struct qmem *mcast_buf;
|
||||
int replay_pkind;
|
||||
int next_free_mce;
|
||||
spinlock_t mce_lock; /* Serialize MCE updates */
|
||||
};
|
||||
|
||||
struct nix_mce_list {
|
||||
struct hlist_head head;
|
||||
int count;
|
||||
int max;
|
||||
};
|
||||
|
||||
struct npc_mcam {
|
||||
spinlock_t lock; /* MCAM entries and counters update lock */
|
||||
u8 keysize; /* MCAM keysize 112/224/448 bits */
|
||||
u8 banks; /* Number of MCAM banks */
|
||||
u8 banks_per_entry;/* Number of keywords in key */
|
||||
u16 banksize; /* Number of MCAM entries in each bank */
|
||||
u16 total_entries; /* Total number of MCAM entries */
|
||||
u16 entries; /* Total minus reserved for NIX LFs */
|
||||
u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
|
||||
u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
|
||||
};
|
||||
|
||||
/* Structure for per RVU func info ie PF/VF */
|
||||
struct rvu_pfvf {
|
||||
bool npalf; /* Only one NPALF per RVU_FUNC */
|
||||
@ -67,6 +93,7 @@ struct rvu_pfvf {
|
||||
u16 ssow;
|
||||
u16 cptlfs;
|
||||
u16 timlfs;
|
||||
u8 cgx_lmac;
|
||||
|
||||
/* Block LF's MSIX vector info */
|
||||
struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
|
||||
@ -91,7 +118,16 @@ struct rvu_pfvf {
|
||||
unsigned long *rq_bmap;
|
||||
unsigned long *cq_bmap;
|
||||
|
||||
u16 rx_chan_base;
|
||||
u16 tx_chan_base;
|
||||
u8 rx_chan_cnt; /* total number of RX channels */
|
||||
u8 tx_chan_cnt; /* total number of TX channels */
|
||||
|
||||
u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
|
||||
|
||||
/* Broadcast pkt replication info */
|
||||
u16 bcast_mce_idx;
|
||||
struct nix_mce_list bcast_mce_list;
|
||||
};
|
||||
|
||||
struct nix_txsch {
|
||||
@ -100,8 +136,14 @@ struct nix_txsch {
|
||||
u16 *pfvf_map;
|
||||
};
|
||||
|
||||
struct npc_pkind {
|
||||
struct rsrc_bmap rsrc;
|
||||
u32 *pfchan_map;
|
||||
};
|
||||
|
||||
struct nix_hw {
|
||||
struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
|
||||
struct nix_mcast mcast;
|
||||
};
|
||||
|
||||
struct rvu_hwinfo {
|
||||
@ -113,9 +155,13 @@ struct rvu_hwinfo {
|
||||
u8 cgx_links;
|
||||
u8 lbk_links;
|
||||
u8 sdp_links;
|
||||
u8 npc_kpus; /* No of parser units */
|
||||
|
||||
|
||||
struct rvu_block block[BLK_COUNT]; /* Block info */
|
||||
struct nix_hw *nix0;
|
||||
struct npc_pkind pkind;
|
||||
struct npc_mcam mcam;
|
||||
};
|
||||
|
||||
struct rvu {
|
||||
@ -180,11 +226,12 @@ static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
|
||||
/* Function Prototypes
|
||||
* RVU
|
||||
*/
|
||||
|
||||
int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
|
||||
int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
|
||||
void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
|
||||
int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
|
||||
int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
|
||||
bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
|
||||
int rvu_get_pf(u16 pcifunc);
|
||||
struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
|
||||
void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
|
||||
@ -194,6 +241,14 @@ int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
|
||||
int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
|
||||
int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
|
||||
|
||||
/* RVU HW reg validation */
|
||||
enum regmap_block {
|
||||
TXSCHQ_HWREGMAP = 0,
|
||||
MAX_HWREGMAP,
|
||||
};
|
||||
|
||||
bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
|
||||
|
||||
/* NPA/NIX AQ APIs */
|
||||
int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
|
||||
int qsize, int inst_size, int res_size);
|
||||
@ -213,6 +268,7 @@ static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
|
||||
|
||||
int rvu_cgx_probe(struct rvu *rvu);
|
||||
void rvu_cgx_wq_destroy(struct rvu *rvu);
|
||||
void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
|
||||
int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
|
||||
int rvu_mbox_handler_CGX_START_RXTX(struct rvu *rvu, struct msg_req *req,
|
||||
struct msg_rsp *rsp);
|
||||
@ -259,6 +315,7 @@ int rvu_mbox_handler_NPA_LF_FREE(struct rvu *rvu, struct msg_req *req,
|
||||
/* NIX APIs */
|
||||
int rvu_nix_init(struct rvu *rvu);
|
||||
void rvu_nix_freemem(struct rvu *rvu);
|
||||
int rvu_get_nixlf_count(struct rvu *rvu);
|
||||
int rvu_mbox_handler_NIX_LF_ALLOC(struct rvu *rvu,
|
||||
struct nix_lf_alloc_req *req,
|
||||
struct nix_lf_alloc_rsp *rsp);
|
||||
@ -270,4 +327,42 @@ int rvu_mbox_handler_NIX_AQ_ENQ(struct rvu *rvu,
|
||||
int rvu_mbox_handler_NIX_HWCTX_DISABLE(struct rvu *rvu,
|
||||
struct hwctx_disable_req *req,
|
||||
struct msg_rsp *rsp);
|
||||
int rvu_mbox_handler_NIX_TXSCH_ALLOC(struct rvu *rvu,
|
||||
struct nix_txsch_alloc_req *req,
|
||||
struct nix_txsch_alloc_rsp *rsp);
|
||||
int rvu_mbox_handler_NIX_TXSCH_FREE(struct rvu *rvu,
|
||||
struct nix_txsch_free_req *req,
|
||||
struct msg_rsp *rsp);
|
||||
int rvu_mbox_handler_NIX_TXSCHQ_CFG(struct rvu *rvu,
|
||||
struct nix_txschq_config *req,
|
||||
struct msg_rsp *rsp);
|
||||
int rvu_mbox_handler_NIX_STATS_RST(struct rvu *rvu, struct msg_req *req,
|
||||
struct msg_rsp *rsp);
|
||||
int rvu_mbox_handler_NIX_VTAG_CFG(struct rvu *rvu,
|
||||
struct nix_vtag_config *req,
|
||||
struct msg_rsp *rsp);
|
||||
int rvu_mbox_handler_NIX_RSS_FLOWKEY_CFG(struct rvu *rvu,
|
||||
struct nix_rss_flowkey_cfg *req,
|
||||
struct msg_rsp *rsp);
|
||||
int rvu_mbox_handler_NIX_SET_MAC_ADDR(struct rvu *rvu,
|
||||
struct nix_set_mac_addr *req,
|
||||
struct msg_rsp *rsp);
|
||||
int rvu_mbox_handler_NIX_SET_RX_MODE(struct rvu *rvu, struct nix_rx_mode *req,
|
||||
struct msg_rsp *rsp);
|
||||
|
||||
/* NPC APIs */
|
||||
int rvu_npc_init(struct rvu *rvu);
|
||||
void rvu_npc_freemem(struct rvu *rvu);
|
||||
int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
|
||||
void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
|
||||
void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
|
||||
int nixlf, u64 chan, u8 *mac_addr);
|
||||
void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
|
||||
int nixlf, u64 chan, bool allmulti);
|
||||
void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf);
|
||||
void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
|
||||
int nixlf, u64 chan);
|
||||
void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
|
||||
void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
|
||||
int group, int alg_idx, int mcam_index);
|
||||
#endif /* RVU_H */
|
||||
|
||||
@ -50,7 +50,7 @@ static inline u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id)
|
||||
return ((cgx_id & 0xF) << 4) | (lmac_id & 0xF);
|
||||
}
|
||||
|
||||
static void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
|
||||
void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
|
||||
{
|
||||
if (cgx_id >= rvu->cgx_cnt)
|
||||
return NULL;
|
||||
@ -60,10 +60,11 @@ static void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
|
||||
|
||||
static int rvu_map_cgx_lmac_pf(struct rvu *rvu)
|
||||
{
|
||||
struct npc_pkind *pkind = &rvu->hw->pkind;
|
||||
int cgx_cnt = rvu->cgx_cnt;
|
||||
int cgx, lmac_cnt, lmac;
|
||||
int pf = PF_CGXMAP_BASE;
|
||||
int size;
|
||||
int size, free_pkind;
|
||||
|
||||
if (!cgx_cnt)
|
||||
return 0;
|
||||
@ -96,6 +97,8 @@ static int rvu_map_cgx_lmac_pf(struct rvu *rvu)
|
||||
for (lmac = 0; lmac < lmac_cnt; lmac++, pf++) {
|
||||
rvu->pf2cgxlmac_map[pf] = cgxlmac_id_to_bmap(cgx, lmac);
|
||||
rvu->cgxlmac2pf_map[CGX_OFFSET(cgx) + lmac] = 1 << pf;
|
||||
free_pkind = rvu_alloc_rsrc(&pkind->rsrc);
|
||||
pkind->pfchan_map[free_pkind] = ((pf) & 0x3F) << 16;
|
||||
rvu->cgx_mapped_pfs++;
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
816
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
Normal file
816
drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
Normal file
@ -0,0 +1,816 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Marvell OcteonTx2 RVU Admin Function driver
|
||||
*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include "rvu_struct.h"
|
||||
#include "rvu_reg.h"
|
||||
#include "rvu.h"
|
||||
#include "npc.h"
|
||||
#include "npc_profile.h"
|
||||
|
||||
#define RSVD_MCAM_ENTRIES_PER_PF 2 /* Bcast & Promisc */
|
||||
#define RSVD_MCAM_ENTRIES_PER_NIXLF 1 /* Ucast for LFs */
|
||||
|
||||
#define NIXLF_UCAST_ENTRY 0
|
||||
#define NIXLF_BCAST_ENTRY 1
|
||||
#define NIXLF_PROMISC_ENTRY 2
|
||||
|
||||
#define NPC_PARSE_RESULT_DMAC_OFFSET 8
|
||||
|
||||
struct mcam_entry {
|
||||
#define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
|
||||
u64 kw[NPC_MAX_KWS_IN_KEY];
|
||||
u64 kw_mask[NPC_MAX_KWS_IN_KEY];
|
||||
u64 action;
|
||||
u64 vtag_action;
|
||||
};
|
||||
|
||||
void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf)
|
||||
{
|
||||
int blkaddr;
|
||||
u64 val = 0;
|
||||
|
||||
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
|
||||
if (blkaddr < 0)
|
||||
return;
|
||||
|
||||
/* Config CPI base for the PKIND */
|
||||
val = pkind | 1ULL << 62;
|
||||
rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val);
|
||||
}
|
||||
|
||||
int rvu_npc_get_pkind(struct rvu *rvu, u16 pf)
|
||||
{
|
||||
struct npc_pkind *pkind = &rvu->hw->pkind;
|
||||
u32 map;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < pkind->rsrc.max; i++) {
|
||||
map = pkind->pfchan_map[i];
|
||||
if (((map >> 16) & 0x3F) == pf)
|
||||
return i;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int npc_get_nixlf_mcam_index(struct npc_mcam *mcam,
|
||||
u16 pcifunc, int nixlf, int type)
|
||||
{
|
||||
int pf = rvu_get_pf(pcifunc);
|
||||
int index;
|
||||
|
||||
/* Check if this is for a PF */
|
||||
if (pf && !(pcifunc & RVU_PFVF_FUNC_MASK)) {
|
||||
/* Reserved entries exclude PF0 */
|
||||
pf--;
|
||||
index = mcam->pf_offset + (pf * RSVD_MCAM_ENTRIES_PER_PF);
|
||||
/* Broadcast address matching entry should be first so
|
||||
* that the packet can be replicated to all VFs.
|
||||
*/
|
||||
if (type == NIXLF_BCAST_ENTRY)
|
||||
return index;
|
||||
else if (type == NIXLF_PROMISC_ENTRY)
|
||||
return index + 1;
|
||||
}
|
||||
|
||||
return (mcam->nixlf_offset + (nixlf * RSVD_MCAM_ENTRIES_PER_NIXLF));
|
||||
}
|
||||
|
||||
static int npc_get_bank(struct npc_mcam *mcam, int index)
|
||||
{
|
||||
int bank = index / mcam->banksize;
|
||||
|
||||
/* 0,1 & 2,3 banks are combined for this keysize */
|
||||
if (mcam->keysize == NPC_MCAM_KEY_X2)
|
||||
return bank ? 2 : 0;
|
||||
|
||||
return bank;
|
||||
}
|
||||
|
||||
static bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam,
|
||||
int blkaddr, int index)
|
||||
{
|
||||
int bank = npc_get_bank(mcam, index);
|
||||
u64 cfg;
|
||||
|
||||
index &= (mcam->banksize - 1);
|
||||
cfg = rvu_read64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_CFG(index, bank));
|
||||
return (cfg & 1);
|
||||
}
|
||||
|
||||
static void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
|
||||
int blkaddr, int index, bool enable)
|
||||
{
|
||||
int bank = npc_get_bank(mcam, index);
|
||||
int actbank = bank;
|
||||
|
||||
index &= (mcam->banksize - 1);
|
||||
for (; bank < (actbank + mcam->banks_per_entry); bank++) {
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_MCAMEX_BANKX_CFG(index, bank),
|
||||
enable ? 1 : 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void npc_get_keyword(struct mcam_entry *entry, int idx,
|
||||
u64 *cam0, u64 *cam1)
|
||||
{
|
||||
u64 kw_mask = 0x00;
|
||||
|
||||
#define CAM_MASK(n) (BIT_ULL(n) - 1)
|
||||
|
||||
/* 0, 2, 4, 6 indices refer to BANKX_CAMX_W0 and
|
||||
* 1, 3, 5, 7 indices refer to BANKX_CAMX_W1.
|
||||
*
|
||||
* Also, only 48 bits of BANKX_CAMX_W1 are valid.
|
||||
*/
|
||||
switch (idx) {
|
||||
case 0:
|
||||
/* BANK(X)_CAM_W0<63:0> = MCAM_KEY[KW0]<63:0> */
|
||||
*cam1 = entry->kw[0];
|
||||
kw_mask = entry->kw_mask[0];
|
||||
break;
|
||||
case 1:
|
||||
/* BANK(X)_CAM_W1<47:0> = MCAM_KEY[KW1]<47:0> */
|
||||
*cam1 = entry->kw[1] & CAM_MASK(48);
|
||||
kw_mask = entry->kw_mask[1] & CAM_MASK(48);
|
||||
break;
|
||||
case 2:
|
||||
/* BANK(X + 1)_CAM_W0<15:0> = MCAM_KEY[KW1]<63:48>
|
||||
* BANK(X + 1)_CAM_W0<63:16> = MCAM_KEY[KW2]<47:0>
|
||||
*/
|
||||
*cam1 = (entry->kw[1] >> 48) & CAM_MASK(16);
|
||||
*cam1 |= ((entry->kw[2] & CAM_MASK(48)) << 16);
|
||||
kw_mask = (entry->kw_mask[1] >> 48) & CAM_MASK(16);
|
||||
kw_mask |= ((entry->kw_mask[2] & CAM_MASK(48)) << 16);
|
||||
break;
|
||||
case 3:
|
||||
/* BANK(X + 1)_CAM_W1<15:0> = MCAM_KEY[KW2]<63:48>
|
||||
* BANK(X + 1)_CAM_W1<47:16> = MCAM_KEY[KW3]<31:0>
|
||||
*/
|
||||
*cam1 = (entry->kw[2] >> 48) & CAM_MASK(16);
|
||||
*cam1 |= ((entry->kw[3] & CAM_MASK(32)) << 16);
|
||||
kw_mask = (entry->kw_mask[2] >> 48) & CAM_MASK(16);
|
||||
kw_mask |= ((entry->kw_mask[3] & CAM_MASK(32)) << 16);
|
||||
break;
|
||||
case 4:
|
||||
/* BANK(X + 2)_CAM_W0<31:0> = MCAM_KEY[KW3]<63:32>
|
||||
* BANK(X + 2)_CAM_W0<63:32> = MCAM_KEY[KW4]<31:0>
|
||||
*/
|
||||
*cam1 = (entry->kw[3] >> 32) & CAM_MASK(32);
|
||||
*cam1 |= ((entry->kw[4] & CAM_MASK(32)) << 32);
|
||||
kw_mask = (entry->kw_mask[3] >> 32) & CAM_MASK(32);
|
||||
kw_mask |= ((entry->kw_mask[4] & CAM_MASK(32)) << 32);
|
||||
break;
|
||||
case 5:
|
||||
/* BANK(X + 2)_CAM_W1<31:0> = MCAM_KEY[KW4]<63:32>
|
||||
* BANK(X + 2)_CAM_W1<47:32> = MCAM_KEY[KW5]<15:0>
|
||||
*/
|
||||
*cam1 = (entry->kw[4] >> 32) & CAM_MASK(32);
|
||||
*cam1 |= ((entry->kw[5] & CAM_MASK(16)) << 32);
|
||||
kw_mask = (entry->kw_mask[4] >> 32) & CAM_MASK(32);
|
||||
kw_mask |= ((entry->kw_mask[5] & CAM_MASK(16)) << 32);
|
||||
break;
|
||||
case 6:
|
||||
/* BANK(X + 3)_CAM_W0<47:0> = MCAM_KEY[KW5]<63:16>
|
||||
* BANK(X + 3)_CAM_W0<63:48> = MCAM_KEY[KW6]<15:0>
|
||||
*/
|
||||
*cam1 = (entry->kw[5] >> 16) & CAM_MASK(48);
|
||||
*cam1 |= ((entry->kw[6] & CAM_MASK(16)) << 48);
|
||||
kw_mask = (entry->kw_mask[5] >> 16) & CAM_MASK(48);
|
||||
kw_mask |= ((entry->kw_mask[6] & CAM_MASK(16)) << 48);
|
||||
break;
|
||||
case 7:
|
||||
/* BANK(X + 3)_CAM_W1<47:0> = MCAM_KEY[KW6]<63:16> */
|
||||
*cam1 = (entry->kw[6] >> 16) & CAM_MASK(48);
|
||||
kw_mask = (entry->kw_mask[6] >> 16) & CAM_MASK(48);
|
||||
break;
|
||||
}
|
||||
|
||||
*cam1 &= kw_mask;
|
||||
*cam0 = ~*cam1 & kw_mask;
|
||||
}
|
||||
|
||||
static void npc_config_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
|
||||
int blkaddr, int index, u8 intf,
|
||||
struct mcam_entry *entry, bool enable)
|
||||
{
|
||||
int bank = npc_get_bank(mcam, index);
|
||||
int kw = 0, actbank, actindex;
|
||||
u64 cam0, cam1;
|
||||
|
||||
actbank = bank; /* Save bank id, to set action later on */
|
||||
actindex = index;
|
||||
index &= (mcam->banksize - 1);
|
||||
|
||||
/* CAM1 takes the comparison value and
|
||||
* CAM0 specifies match for a bit in key being '0' or '1' or 'dontcare'.
|
||||
* CAM1<n> = 0 & CAM0<n> = 1 => match if key<n> = 0
|
||||
* CAM1<n> = 1 & CAM0<n> = 0 => match if key<n> = 1
|
||||
* CAM1<n> = 0 & CAM0<n> = 0 => always match i.e dontcare.
|
||||
*/
|
||||
for (; bank < (actbank + mcam->banks_per_entry); bank++, kw = kw + 2) {
|
||||
/* Interface should be set in all banks */
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 1),
|
||||
intf);
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_MCAMEX_BANKX_CAMX_INTF(index, bank, 0),
|
||||
~intf & 0x3);
|
||||
|
||||
/* Set the match key */
|
||||
npc_get_keyword(entry, kw, &cam0, &cam1);
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 1), cam1);
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_MCAMEX_BANKX_CAMX_W0(index, bank, 0), cam0);
|
||||
|
||||
npc_get_keyword(entry, kw + 1, &cam0, &cam1);
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 1), cam1);
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_MCAMEX_BANKX_CAMX_W1(index, bank, 0), cam0);
|
||||
}
|
||||
|
||||
/* Set 'action' */
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_MCAMEX_BANKX_ACTION(index, actbank), entry->action);
|
||||
|
||||
/* Set TAG 'action' */
|
||||
rvu_write64(rvu, blkaddr, NPC_AF_MCAMEX_BANKX_TAG_ACT(index, actbank),
|
||||
entry->vtag_action);
|
||||
|
||||
/* Enable the entry */
|
||||
if (enable)
|
||||
npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, true);
|
||||
else
|
||||
npc_enable_mcam_entry(rvu, mcam, blkaddr, actindex, false);
|
||||
}
|
||||
|
||||
static u64 npc_get_mcam_action(struct rvu *rvu, struct npc_mcam *mcam,
|
||||
int blkaddr, int index)
|
||||
{
|
||||
int bank = npc_get_bank(mcam, index);
|
||||
|
||||
index &= (mcam->banksize - 1);
|
||||
return rvu_read64(rvu, blkaddr,
|
||||
NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
|
||||
}
|
||||
|
||||
void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
|
||||
int nixlf, u64 chan, u8 *mac_addr)
|
||||
{
|
||||
struct npc_mcam *mcam = &rvu->hw->mcam;
|
||||
struct mcam_entry entry = { {0} };
|
||||
struct nix_rx_action action;
|
||||
int blkaddr, index, kwi;
|
||||
u64 mac = 0;
|
||||
|
||||
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
|
||||
if (blkaddr < 0)
|
||||
return;
|
||||
|
||||
for (index = ETH_ALEN - 1; index >= 0; index--)
|
||||
mac |= ((u64)*mac_addr++) << (8 * index);
|
||||
|
||||
index = npc_get_nixlf_mcam_index(mcam, pcifunc,
|
||||
nixlf, NIXLF_UCAST_ENTRY);
|
||||
|
||||
/* Match ingress channel and DMAC */
|
||||
entry.kw[0] = chan;
|
||||
entry.kw_mask[0] = 0xFFFULL;
|
||||
|
||||
kwi = NPC_PARSE_RESULT_DMAC_OFFSET / sizeof(u64);
|
||||
entry.kw[kwi] = mac;
|
||||
entry.kw_mask[kwi] = BIT_ULL(48) - 1;
|
||||
|
||||
/* Don't change the action if entry is already enabled
|
||||
* Otherwise RSS action may get overwritten.
|
||||
*/
|
||||
if (is_mcam_entry_enabled(rvu, mcam, blkaddr, index)) {
|
||||
*(u64 *)&action = npc_get_mcam_action(rvu, mcam,
|
||||
blkaddr, index);
|
||||
} else {
|
||||
*(u64 *)&action = 0x00;
|
||||
action.op = NIX_RX_ACTIONOP_UCAST;
|
||||
action.pf_func = pcifunc;
|
||||
}
|
||||
|
||||
entry.action = *(u64 *)&action;
|
||||
npc_config_mcam_entry(rvu, mcam, blkaddr, index,
|
||||
NIX_INTF_RX, &entry, true);
|
||||
}
|
||||
|
||||
void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
|
||||
int nixlf, u64 chan, bool allmulti)
|
||||
{
|
||||
struct npc_mcam *mcam = &rvu->hw->mcam;
|
||||
struct mcam_entry entry = { {0} };
|
||||
struct nix_rx_action action;
|
||||
int blkaddr, index, kwi;
|
||||
|
||||
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
|
||||
if (blkaddr < 0)
|
||||
return;
|
||||
|
||||
/* Only PF or AF VF can add a promiscuous entry */
|
||||
if (pcifunc & RVU_PFVF_FUNC_MASK)
|
||||
return;
|
||||
|
||||
index = npc_get_nixlf_mcam_index(mcam, pcifunc,
|
||||
nixlf, NIXLF_PROMISC_ENTRY);
|
||||
|
||||
entry.kw[0] = chan;
|
||||
entry.kw_mask[0] = 0xFFFULL;
|
||||
|
||||
if (allmulti) {
|
||||
kwi = NPC_PARSE_RESULT_DMAC_OFFSET / sizeof(u64);
|
||||
entry.kw[kwi] = BIT_ULL(40); /* LSB bit of 1st byte in DMAC */
|
||||
entry.kw_mask[kwi] = BIT_ULL(40);
|
||||
}
|
||||
|
||||
*(u64 *)&action = 0x00;
|
||||
action.op = NIX_RX_ACTIONOP_UCAST;
|
||||
action.pf_func = pcifunc;
|
||||
|
||||
entry.action = *(u64 *)&action;
|
||||
npc_config_mcam_entry(rvu, mcam, blkaddr, index,
|
||||
NIX_INTF_RX, &entry, true);
|
||||
}
|
||||
|
||||
void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf)
|
||||
{
|
||||
struct npc_mcam *mcam = &rvu->hw->mcam;
|
||||
int blkaddr, index;
|
||||
|
||||
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
|
||||
if (blkaddr < 0)
|
||||
return;
|
||||
|
||||
/* Only PF's have a promiscuous entry */
|
||||
if (pcifunc & RVU_PFVF_FUNC_MASK)
|
||||
return;
|
||||
|
||||
index = npc_get_nixlf_mcam_index(mcam, pcifunc,
|
||||
nixlf, NIXLF_PROMISC_ENTRY);
|
||||
npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false);
|
||||
}
|
||||
|
||||
void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
|
||||
int nixlf, u64 chan)
|
||||
{
|
||||
struct npc_mcam *mcam = &rvu->hw->mcam;
|
||||
struct mcam_entry entry = { {0} };
|
||||
struct nix_rx_action action;
|
||||
#ifdef MCAST_MCE
|
||||
struct rvu_pfvf *pfvf;
|
||||
#endif
|
||||
int blkaddr, index;
|
||||
|
||||
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
|
||||
if (blkaddr < 0)
|
||||
return;
|
||||
|
||||
/* Only PF can add a bcast match entry */
|
||||
if (pcifunc & RVU_PFVF_FUNC_MASK)
|
||||
return;
|
||||
#ifdef MCAST_MCE
|
||||
pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
|
||||
#endif
|
||||
|
||||
index = npc_get_nixlf_mcam_index(mcam, pcifunc,
|
||||
nixlf, NIXLF_BCAST_ENTRY);
|
||||
|
||||
/* Check for L2B bit and LMAC channel */
|
||||
entry.kw[0] = BIT_ULL(25) | chan;
|
||||
entry.kw_mask[0] = BIT_ULL(25) | 0xFFFULL;
|
||||
|
||||
*(u64 *)&action = 0x00;
|
||||
#ifdef MCAST_MCE
|
||||
/* Early silicon doesn't support pkt replication,
|
||||
* so install entry with UCAST action, so that PF
|
||||
* receives all broadcast packets.
|
||||
*/
|
||||
action.op = NIX_RX_ACTIONOP_MCAST;
|
||||
action.pf_func = pcifunc;
|
||||
action.index = pfvf->bcast_mce_idx;
|
||||
#else
|
||||
action.op = NIX_RX_ACTIONOP_UCAST;
|
||||
action.pf_func = pcifunc;
|
||||
#endif
|
||||
|
||||
entry.action = *(u64 *)&action;
|
||||
npc_config_mcam_entry(rvu, mcam, blkaddr, index,
|
||||
NIX_INTF_RX, &entry, true);
|
||||
}
|
||||
|
||||
void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
|
||||
int group, int alg_idx, int mcam_index)
|
||||
{
|
||||
struct npc_mcam *mcam = &rvu->hw->mcam;
|
||||
struct nix_rx_action action;
|
||||
int blkaddr, index, bank;
|
||||
|
||||
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
|
||||
if (blkaddr < 0)
|
||||
return;
|
||||
|
||||
/* Check if this is for reserved default entry */
|
||||
if (mcam_index < 0) {
|
||||
if (group != DEFAULT_RSS_CONTEXT_GROUP)
|
||||
return;
|
||||
index = npc_get_nixlf_mcam_index(mcam, pcifunc,
|
||||
nixlf, NIXLF_UCAST_ENTRY);
|
||||
} else {
|
||||
/* TODO: validate this mcam index */
|
||||
index = mcam_index;
|
||||
}
|
||||
|
||||
if (index >= mcam->total_entries)
|
||||
return;
|
||||
|
||||
bank = npc_get_bank(mcam, index);
|
||||
index &= (mcam->banksize - 1);
|
||||
|
||||
*(u64 *)&action = rvu_read64(rvu, blkaddr,
|
||||
NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
|
||||
/* Ignore if no action was set earlier */
|
||||
if (!*(u64 *)&action)
|
||||
return;
|
||||
|
||||
action.op = NIX_RX_ACTIONOP_RSS;
|
||||
action.pf_func = pcifunc;
|
||||
action.index = group;
|
||||
action.flow_key_alg = alg_idx;
|
||||
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_MCAMEX_BANKX_ACTION(index, bank), *(u64 *)&action);
|
||||
}
|
||||
|
||||
void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf)
|
||||
{
|
||||
struct npc_mcam *mcam = &rvu->hw->mcam;
|
||||
struct nix_rx_action action;
|
||||
int blkaddr, index, bank;
|
||||
|
||||
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
|
||||
if (blkaddr < 0)
|
||||
return;
|
||||
|
||||
/* Disable ucast MCAM match entry of this PF/VF */
|
||||
index = npc_get_nixlf_mcam_index(mcam, pcifunc,
|
||||
nixlf, NIXLF_UCAST_ENTRY);
|
||||
npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false);
|
||||
|
||||
/* For PF, disable promisc and bcast MCAM match entries */
|
||||
if (!(pcifunc & RVU_PFVF_FUNC_MASK)) {
|
||||
index = npc_get_nixlf_mcam_index(mcam, pcifunc,
|
||||
nixlf, NIXLF_BCAST_ENTRY);
|
||||
/* For bcast, disable only if it's action is not
|
||||
* packet replication, incase if action is replication
|
||||
* then this PF's nixlf is removed from bcast replication
|
||||
* list.
|
||||
*/
|
||||
bank = npc_get_bank(mcam, index);
|
||||
index &= (mcam->banksize - 1);
|
||||
*(u64 *)&action = rvu_read64(rvu, blkaddr,
|
||||
NPC_AF_MCAMEX_BANKX_ACTION(index, bank));
|
||||
if (action.op != NIX_RX_ACTIONOP_MCAST)
|
||||
npc_enable_mcam_entry(rvu, mcam, blkaddr, index, false);
|
||||
|
||||
rvu_npc_disable_promisc_entry(rvu, pcifunc, nixlf);
|
||||
}
|
||||
}
|
||||
|
||||
#define LDATA_EXTRACT_CONFIG(intf, lid, ltype, ld, cfg) \
|
||||
rvu_write64(rvu, blkaddr, \
|
||||
NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)
|
||||
|
||||
#define LDATA_FLAGS_CONFIG(intf, ld, flags, cfg) \
|
||||
rvu_write64(rvu, blkaddr, \
|
||||
NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg)
|
||||
|
||||
static void npc_config_ldata_extract(struct rvu *rvu, int blkaddr)
|
||||
{
|
||||
struct npc_mcam *mcam = &rvu->hw->mcam;
|
||||
int lid, ltype;
|
||||
int lid_count;
|
||||
u64 cfg;
|
||||
|
||||
cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST);
|
||||
lid_count = (cfg >> 4) & 0xF;
|
||||
|
||||
/* First clear any existing config i.e
|
||||
* disable LDATA and FLAGS extraction.
|
||||
*/
|
||||
for (lid = 0; lid < lid_count; lid++) {
|
||||
for (ltype = 0; ltype < 16; ltype++) {
|
||||
LDATA_EXTRACT_CONFIG(NIX_INTF_RX, lid, ltype, 0, 0ULL);
|
||||
LDATA_EXTRACT_CONFIG(NIX_INTF_RX, lid, ltype, 1, 0ULL);
|
||||
LDATA_EXTRACT_CONFIG(NIX_INTF_TX, lid, ltype, 0, 0ULL);
|
||||
LDATA_EXTRACT_CONFIG(NIX_INTF_TX, lid, ltype, 1, 0ULL);
|
||||
|
||||
LDATA_FLAGS_CONFIG(NIX_INTF_RX, 0, ltype, 0ULL);
|
||||
LDATA_FLAGS_CONFIG(NIX_INTF_RX, 1, ltype, 0ULL);
|
||||
LDATA_FLAGS_CONFIG(NIX_INTF_TX, 0, ltype, 0ULL);
|
||||
LDATA_FLAGS_CONFIG(NIX_INTF_TX, 1, ltype, 0ULL);
|
||||
}
|
||||
}
|
||||
|
||||
/* If we plan to extract Outer IPv4 tuple for TCP/UDP pkts
|
||||
* then 112bit key is not sufficient
|
||||
*/
|
||||
if (mcam->keysize != NPC_MCAM_KEY_X2)
|
||||
return;
|
||||
|
||||
/* Start placing extracted data/flags from 64bit onwards, for now */
|
||||
/* Extract DMAC from the packet */
|
||||
cfg = (0x05 << 16) | BIT_ULL(7) | NPC_PARSE_RESULT_DMAC_OFFSET;
|
||||
LDATA_EXTRACT_CONFIG(NIX_INTF_RX, NPC_LID_LA, NPC_LT_LA_ETHER, 0, cfg);
|
||||
}
|
||||
|
||||
static void npc_config_kpuaction(struct rvu *rvu, int blkaddr,
|
||||
struct npc_kpu_profile_action *kpuaction,
|
||||
int kpu, int entry, bool pkind)
|
||||
{
|
||||
struct npc_kpu_action0 action0 = {0};
|
||||
struct npc_kpu_action1 action1 = {0};
|
||||
u64 reg;
|
||||
|
||||
action1.errlev = kpuaction->errlev;
|
||||
action1.errcode = kpuaction->errcode;
|
||||
action1.dp0_offset = kpuaction->dp0_offset;
|
||||
action1.dp1_offset = kpuaction->dp1_offset;
|
||||
action1.dp2_offset = kpuaction->dp2_offset;
|
||||
|
||||
if (pkind)
|
||||
reg = NPC_AF_PKINDX_ACTION1(entry);
|
||||
else
|
||||
reg = NPC_AF_KPUX_ENTRYX_ACTION1(kpu, entry);
|
||||
|
||||
rvu_write64(rvu, blkaddr, reg, *(u64 *)&action1);
|
||||
|
||||
action0.byp_count = kpuaction->bypass_count;
|
||||
action0.capture_ena = kpuaction->cap_ena;
|
||||
action0.parse_done = kpuaction->parse_done;
|
||||
action0.next_state = kpuaction->next_state;
|
||||
action0.capture_lid = kpuaction->lid;
|
||||
action0.capture_ltype = kpuaction->ltype;
|
||||
action0.capture_flags = kpuaction->flags;
|
||||
action0.ptr_advance = kpuaction->ptr_advance;
|
||||
action0.var_len_offset = kpuaction->offset;
|
||||
action0.var_len_mask = kpuaction->mask;
|
||||
action0.var_len_right = kpuaction->right;
|
||||
action0.var_len_shift = kpuaction->shift;
|
||||
|
||||
if (pkind)
|
||||
reg = NPC_AF_PKINDX_ACTION0(entry);
|
||||
else
|
||||
reg = NPC_AF_KPUX_ENTRYX_ACTION0(kpu, entry);
|
||||
|
||||
rvu_write64(rvu, blkaddr, reg, *(u64 *)&action0);
|
||||
}
|
||||
|
||||
static void npc_config_kpucam(struct rvu *rvu, int blkaddr,
|
||||
struct npc_kpu_profile_cam *kpucam,
|
||||
int kpu, int entry)
|
||||
{
|
||||
struct npc_kpu_cam cam0 = {0};
|
||||
struct npc_kpu_cam cam1 = {0};
|
||||
|
||||
cam1.state = kpucam->state & kpucam->state_mask;
|
||||
cam1.dp0_data = kpucam->dp0 & kpucam->dp0_mask;
|
||||
cam1.dp1_data = kpucam->dp1 & kpucam->dp1_mask;
|
||||
cam1.dp2_data = kpucam->dp2 & kpucam->dp2_mask;
|
||||
|
||||
cam0.state = ~kpucam->state & kpucam->state_mask;
|
||||
cam0.dp0_data = ~kpucam->dp0 & kpucam->dp0_mask;
|
||||
cam0.dp1_data = ~kpucam->dp1 & kpucam->dp1_mask;
|
||||
cam0.dp2_data = ~kpucam->dp2 & kpucam->dp2_mask;
|
||||
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 0), *(u64 *)&cam0);
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_KPUX_ENTRYX_CAMX(kpu, entry, 1), *(u64 *)&cam1);
|
||||
}
|
||||
|
||||
static inline u64 enable_mask(int count)
|
||||
{
|
||||
return (((count) < 64) ? ~(BIT_ULL(count) - 1) : (0x00ULL));
|
||||
}
|
||||
|
||||
static void npc_program_kpu_profile(struct rvu *rvu, int blkaddr, int kpu,
|
||||
struct npc_kpu_profile *profile)
|
||||
{
|
||||
int entry, num_entries, max_entries;
|
||||
|
||||
if (profile->cam_entries != profile->action_entries) {
|
||||
dev_err(rvu->dev,
|
||||
"KPU%d: CAM and action entries [%d != %d] not equal\n",
|
||||
kpu, profile->cam_entries, profile->action_entries);
|
||||
}
|
||||
|
||||
max_entries = rvu_read64(rvu, blkaddr, NPC_AF_CONST1) & 0xFFF;
|
||||
|
||||
/* Program CAM match entries for previous KPU extracted data */
|
||||
num_entries = min_t(int, profile->cam_entries, max_entries);
|
||||
for (entry = 0; entry < num_entries; entry++)
|
||||
npc_config_kpucam(rvu, blkaddr,
|
||||
&profile->cam[entry], kpu, entry);
|
||||
|
||||
/* Program this KPU's actions */
|
||||
num_entries = min_t(int, profile->action_entries, max_entries);
|
||||
for (entry = 0; entry < num_entries; entry++)
|
||||
npc_config_kpuaction(rvu, blkaddr, &profile->action[entry],
|
||||
kpu, entry, false);
|
||||
|
||||
/* Enable all programmed entries */
|
||||
num_entries = min_t(int, profile->action_entries, profile->cam_entries);
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_KPUX_ENTRY_DISX(kpu, 0), enable_mask(num_entries));
|
||||
if (num_entries > 64) {
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_KPUX_ENTRY_DISX(kpu, 1),
|
||||
enable_mask(num_entries - 64));
|
||||
}
|
||||
|
||||
/* Enable this KPU */
|
||||
rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(kpu), 0x01);
|
||||
}
|
||||
|
||||
static void npc_parser_profile_init(struct rvu *rvu, int blkaddr)
|
||||
{
|
||||
struct rvu_hwinfo *hw = rvu->hw;
|
||||
int num_pkinds, num_kpus, idx;
|
||||
struct npc_pkind *pkind;
|
||||
|
||||
/* Get HW limits */
|
||||
hw->npc_kpus = (rvu_read64(rvu, blkaddr, NPC_AF_CONST) >> 8) & 0x1F;
|
||||
|
||||
/* Disable all KPUs and their entries */
|
||||
for (idx = 0; idx < hw->npc_kpus; idx++) {
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_KPUX_ENTRY_DISX(idx, 0), ~0ULL);
|
||||
rvu_write64(rvu, blkaddr,
|
||||
NPC_AF_KPUX_ENTRY_DISX(idx, 1), ~0ULL);
|
||||
rvu_write64(rvu, blkaddr, NPC_AF_KPUX_CFG(idx), 0x00);
|
||||
}
|
||||
|
||||
/* First program IKPU profile i.e PKIND configs.
|
||||
* Check HW max count to avoid configuring junk or
|
||||
* writing to unsupported CSR addresses.
|
||||
*/
|
||||
pkind = &hw->pkind;
|
||||
num_pkinds = ARRAY_SIZE(ikpu_action_entries);
|
||||
num_pkinds = min_t(int, pkind->rsrc.max, num_pkinds);
|
||||
|
||||
for (idx = 0; idx < num_pkinds; idx++)
|
||||
npc_config_kpuaction(rvu, blkaddr,
|
||||
&ikpu_action_entries[idx], 0, idx, true);
|
||||
|
||||
/* Program KPU CAM and Action profiles */
|
||||
num_kpus = ARRAY_SIZE(npc_kpu_profiles);
|
||||
num_kpus = min_t(int, hw->npc_kpus, num_kpus);
|
||||
|
||||
for (idx = 0; idx < num_kpus; idx++)
|
||||
npc_program_kpu_profile(rvu, blkaddr,
|
||||
idx, &npc_kpu_profiles[idx]);
|
||||
}
|
||||
|
||||
static int npc_mcam_rsrcs_init(struct rvu *rvu, int blkaddr)
|
||||
{
|
||||
int nixlf_count = rvu_get_nixlf_count(rvu);
|
||||
struct npc_mcam *mcam = &rvu->hw->mcam;
|
||||
int rsvd;
|
||||
u64 cfg;
|
||||
|
||||
/* Get HW limits */
|
||||
cfg = rvu_read64(rvu, blkaddr, NPC_AF_CONST);
|
||||
mcam->banks = (cfg >> 44) & 0xF;
|
||||
mcam->banksize = (cfg >> 28) & 0xFFFF;
|
||||
|
||||
/* Actual number of MCAM entries vary by entry size */
|
||||
cfg = (rvu_read64(rvu, blkaddr,
|
||||
NPC_AF_INTFX_KEX_CFG(0)) >> 32) & 0x07;
|
||||
mcam->total_entries = (mcam->banks / BIT_ULL(cfg)) * mcam->banksize;
|
||||
mcam->keysize = cfg;
|
||||
|
||||
/* Number of banks combined per MCAM entry */
|
||||
if (cfg == NPC_MCAM_KEY_X4)
|
||||
mcam->banks_per_entry = 4;
|
||||
else if (cfg == NPC_MCAM_KEY_X2)
|
||||
mcam->banks_per_entry = 2;
|
||||
else
|
||||
mcam->banks_per_entry = 1;
|
||||
|
||||
/* Reserve one MCAM entry for each of the NIX LF to
|
||||
* guarantee space to install default matching DMAC rule.
|
||||
* Also reserve 2 MCAM entries for each PF for default
|
||||
* channel based matching or 'bcast & promisc' matching to
|
||||
* support BCAST and PROMISC modes of operation for PFs.
|
||||
* PF0 is excluded.
|
||||
*/
|
||||
rsvd = (nixlf_count * RSVD_MCAM_ENTRIES_PER_NIXLF) +
|
||||
((rvu->hw->total_pfs - 1) * RSVD_MCAM_ENTRIES_PER_PF);
|
||||
if (mcam->total_entries <= rsvd) {
|
||||
dev_warn(rvu->dev,
|
||||
"Insufficient NPC MCAM size %d for pkt I/O, exiting\n",
|
||||
mcam->total_entries);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
mcam->entries = mcam->total_entries - rsvd;
|
||||
mcam->nixlf_offset = mcam->entries;
|
||||
mcam->pf_offset = mcam->nixlf_offset + nixlf_count;
|
||||
|
||||
spin_lock_init(&mcam->lock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rvu_npc_init(struct rvu *rvu)
|
||||
{
|
||||
struct npc_pkind *pkind = &rvu->hw->pkind;
|
||||
u64 keyz = NPC_MCAM_KEY_X2;
|
||||
int blkaddr, err;
|
||||
|
||||
blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0);
|
||||
if (blkaddr < 0) {
|
||||
dev_err(rvu->dev, "%s: NPC block not implemented\n", __func__);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Allocate resource bimap for pkind*/
|
||||
pkind->rsrc.max = (rvu_read64(rvu, blkaddr,
|
||||
NPC_AF_CONST1) >> 12) & 0xFF;
|
||||
err = rvu_alloc_bitmap(&pkind->rsrc);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* Allocate mem for pkind to PF and channel mapping info */
|
||||
pkind->pfchan_map = devm_kcalloc(rvu->dev, pkind->rsrc.max,
|
||||
sizeof(u32), GFP_KERNEL);
|
||||
if (!pkind->pfchan_map)
|
||||
return -ENOMEM;
|
||||
|
||||
/* Configure KPU profile */
|
||||
npc_parser_profile_init(rvu, blkaddr);
|
||||
|
||||
/* Config Outer L2, IPv4's NPC layer info */
|
||||
rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2,
|
||||
(NPC_LID_LA << 8) | (NPC_LT_LA_ETHER << 4) | 0x0F);
|
||||
rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4,
|
||||
(NPC_LID_LC << 8) | (NPC_LT_LC_IP << 4) | 0x0F);
|
||||
|
||||
/* Enable below for Rx pkts.
|
||||
* - Outer IPv4 header checksum validation.
|
||||
* - Detect outer L2 broadcast address and set NPC_RESULT_S[L2M].
|
||||
*/
|
||||
rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG,
|
||||
rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) |
|
||||
BIT_ULL(6) | BIT_ULL(2));
|
||||
|
||||
/* Set RX and TX side MCAM search key size.
|
||||
* Also enable parse key extract nibbles suchthat except
|
||||
* layer E to H, rest of the key is included for MCAM search.
|
||||
*/
|
||||
rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_RX),
|
||||
((keyz & 0x3) << 32) | ((1ULL << 20) - 1));
|
||||
rvu_write64(rvu, blkaddr, NPC_AF_INTFX_KEX_CFG(NIX_INTF_TX),
|
||||
((keyz & 0x3) << 32) | ((1ULL << 20) - 1));
|
||||
|
||||
err = npc_mcam_rsrcs_init(rvu, blkaddr);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* Config packet data and flags extraction into PARSE result */
|
||||
npc_config_ldata_extract(rvu, blkaddr);
|
||||
|
||||
/* Set TX miss action to UCAST_DEFAULT i.e
|
||||
* transmit the packet on NIX LF SQ's default channel.
|
||||
*/
|
||||
rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_ACT(NIX_INTF_TX),
|
||||
NIX_TX_ACTIONOP_UCAST_DEFAULT);
|
||||
|
||||
/* If MCAM lookup doesn't result in a match, drop the received packet */
|
||||
rvu_write64(rvu, blkaddr, NPC_AF_INTFX_MISS_ACT(NIX_INTF_RX),
|
||||
NIX_RX_ACTIONOP_DROP);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void rvu_npc_freemem(struct rvu *rvu)
|
||||
{
|
||||
struct npc_pkind *pkind = &rvu->hw->pkind;
|
||||
|
||||
kfree(pkind->rsrc.bmap);
|
||||
}
|
||||
71
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
Normal file
71
drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
Normal file
@ -0,0 +1,71 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Marvell OcteonTx2 RVU Admin Function driver
|
||||
*
|
||||
* Copyright (C) 2018 Marvell International Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/pci.h>
|
||||
|
||||
#include "rvu_struct.h"
|
||||
#include "common.h"
|
||||
#include "mbox.h"
|
||||
#include "rvu.h"
|
||||
|
||||
struct reg_range {
|
||||
u64 start;
|
||||
u64 end;
|
||||
};
|
||||
|
||||
struct hw_reg_map {
|
||||
u8 regblk;
|
||||
u8 num_ranges;
|
||||
u64 mask;
|
||||
#define MAX_REG_RANGES 8
|
||||
struct reg_range range[MAX_REG_RANGES];
|
||||
};
|
||||
|
||||
static struct hw_reg_map txsch_reg_map[NIX_TXSCH_LVL_CNT] = {
|
||||
{NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
|
||||
{NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
|
||||
{0x1200, 0x12E0} } },
|
||||
{NIX_TXSCH_LVL_TL3, 3, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
|
||||
{0x1610, 0x1618} } },
|
||||
{NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x1768} } },
|
||||
{NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
|
||||
};
|
||||
|
||||
bool rvu_check_valid_reg(int regmap, int regblk, u64 reg)
|
||||
{
|
||||
int idx;
|
||||
struct hw_reg_map *map;
|
||||
|
||||
/* Only 64bit offsets */
|
||||
if (reg & 0x07)
|
||||
return false;
|
||||
|
||||
if (regmap == TXSCHQ_HWREGMAP) {
|
||||
if (regblk >= NIX_TXSCH_LVL_CNT)
|
||||
return false;
|
||||
map = &txsch_reg_map[regblk];
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Should never happen */
|
||||
if (map->regblk != regblk)
|
||||
return false;
|
||||
|
||||
reg &= map->mask;
|
||||
|
||||
for (idx = 0; idx < map->num_ranges; idx++) {
|
||||
if (reg >= map->range[idx].start &&
|
||||
reg < map->range[idx].end)
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
@ -438,4 +438,65 @@
|
||||
#define NDC_AF_BLK_RST (0x002F0)
|
||||
#define NPC_AF_BLK_RST (0x00040)
|
||||
|
||||
/* NPC */
|
||||
#define NPC_AF_CFG (0x00000)
|
||||
#define NPC_AF_ACTIVE_PC (0x00010)
|
||||
#define NPC_AF_CONST (0x00020)
|
||||
#define NPC_AF_CONST1 (0x00030)
|
||||
#define NPC_AF_BLK_RST (0x00040)
|
||||
#define NPC_AF_MCAM_SCRUB_CTL (0x000a0)
|
||||
#define NPC_AF_KCAM_SCRUB_CTL (0x000b0)
|
||||
#define NPC_AF_KPUX_CFG(a) (0x00500 | (a) << 3)
|
||||
#define NPC_AF_PCK_CFG (0x00600)
|
||||
#define NPC_AF_PCK_DEF_OL2 (0x00610)
|
||||
#define NPC_AF_PCK_DEF_OIP4 (0x00620)
|
||||
#define NPC_AF_PCK_DEF_OIP6 (0x00630)
|
||||
#define NPC_AF_PCK_DEF_IIP4 (0x00640)
|
||||
#define NPC_AF_KEX_LDATAX_FLAGS_CFG(a) (0x00800 | (a) << 3)
|
||||
#define NPC_AF_INTFX_KEX_CFG(a) (0x01010 | (a) << 8)
|
||||
#define NPC_AF_PKINDX_ACTION0(a) (0x80000ull | (a) << 6)
|
||||
#define NPC_AF_PKINDX_ACTION1(a) (0x80008ull | (a) << 6)
|
||||
#define NPC_AF_PKINDX_CPI_DEFX(a, b) (0x80020ull | (a) << 6 | (b) << 3)
|
||||
#define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \
|
||||
(0x100000 | (a) << 14 | (b) << 6 | (c) << 3)
|
||||
#define NPC_AF_KPUX_ENTRYX_ACTION0(a, b) \
|
||||
(0x100020 | (a) << 14 | (b) << 6)
|
||||
#define NPC_AF_KPUX_ENTRYX_ACTION1(a, b) \
|
||||
(0x100028 | (a) << 14 | (b) << 6)
|
||||
#define NPC_AF_KPUX_ENTRY_DISX(a, b) (0x180000 | (a) << 6 | (b) << 3)
|
||||
#define NPC_AF_CPIX_CFG(a) (0x200000 | (a) << 3)
|
||||
#define NPC_AF_INTFX_LIDX_LTX_LDX_CFG(a, b, c, d) \
|
||||
(0x900000 | (a) << 16 | (b) << 12 | (c) << 5 | (d) << 3)
|
||||
#define NPC_AF_INTFX_LDATAX_FLAGSX_CFG(a, b, c) \
|
||||
(0x980000 | (a) << 16 | (b) << 12 | (c) << 3)
|
||||
#define NPC_AF_MCAMEX_BANKX_CAMX_INTF(a, b, c) \
|
||||
(0x1000000ull | (a) << 10 | (b) << 6 | (c) << 3)
|
||||
#define NPC_AF_MCAMEX_BANKX_CAMX_W0(a, b, c) \
|
||||
(0x1000010ull | (a) << 10 | (b) << 6 | (c) << 3)
|
||||
#define NPC_AF_MCAMEX_BANKX_CAMX_W1(a, b, c) \
|
||||
(0x1000020ull | (a) << 10 | (b) << 6 | (c) << 3)
|
||||
#define NPC_AF_MCAMEX_BANKX_CFG(a, b) (0x1800000ull | (a) << 8 | (b) << 4)
|
||||
#define NPC_AF_MCAMEX_BANKX_STAT_ACT(a, b) \
|
||||
(0x1880000 | (a) << 8 | (b) << 4)
|
||||
#define NPC_AF_MATCH_STATX(a) (0x1880008 | (a) << 8)
|
||||
#define NPC_AF_INTFX_MISS_STAT_ACT(a) (0x1880040 + (a) * 0x8)
|
||||
#define NPC_AF_MCAMEX_BANKX_ACTION(a, b) (0x1900000ull | (a) << 8 | (b) << 4)
|
||||
#define NPC_AF_MCAMEX_BANKX_TAG_ACT(a, b) \
|
||||
(0x1900008 | (a) << 8 | (b) << 4)
|
||||
#define NPC_AF_INTFX_MISS_ACT(a) (0x1a00000 | (a) << 4)
|
||||
#define NPC_AF_INTFX_MISS_TAG_ACT(a) (0x1b00008 | (a) << 4)
|
||||
#define NPC_AF_MCAM_BANKX_HITX(a, b) (0x1c80000 | (a) << 8 | (b) << 4)
|
||||
#define NPC_AF_LKUP_CTL (0x2000000)
|
||||
#define NPC_AF_LKUP_DATAX(a) (0x2000200 | (a) << 4)
|
||||
#define NPC_AF_LKUP_RESULTX(a) (0x2000400 | (a) << 4)
|
||||
#define NPC_AF_INTFX_STAT(a) (0x2000800 | (a) << 4)
|
||||
#define NPC_AF_DBG_CTL (0x3000000)
|
||||
#define NPC_AF_DBG_STATUS (0x3000010)
|
||||
#define NPC_AF_KPUX_DBG(a) (0x3000020 | (a) << 8)
|
||||
#define NPC_AF_IKPU_ERR_CTL (0x3000080)
|
||||
#define NPC_AF_KPUX_ERR_CTL(a) (0x30000a0 | (a) << 8)
|
||||
#define NPC_AF_MCAM_DBG (0x3001000)
|
||||
#define NPC_AF_DBG_DATAX(a) (0x3001400 | (a) << 4)
|
||||
#define NPC_AF_DBG_RESULTX(a) (0x3001800 | (a) << 4)
|
||||
|
||||
#endif /* RVU_REG_H */
|
||||
|
||||
@ -879,4 +879,39 @@ struct nix_lso_format {
|
||||
#endif
|
||||
};
|
||||
|
||||
struct nix_rx_flowkey_alg {
|
||||
#if defined(__BIG_ENDIAN_BITFIELD)
|
||||
u64 reserved_35_63 :29;
|
||||
u64 ltype_match :4;
|
||||
u64 ltype_mask :4;
|
||||
u64 sel_chan :1;
|
||||
u64 ena :1;
|
||||
u64 reserved_24_24 :1;
|
||||
u64 lid :3;
|
||||
u64 bytesm1 :5;
|
||||
u64 hdr_offset :8;
|
||||
u64 fn_mask :1;
|
||||
u64 ln_mask :1;
|
||||
u64 key_offset :6;
|
||||
#else
|
||||
u64 key_offset :6;
|
||||
u64 ln_mask :1;
|
||||
u64 fn_mask :1;
|
||||
u64 hdr_offset :8;
|
||||
u64 bytesm1 :5;
|
||||
u64 lid :3;
|
||||
u64 reserved_24_24 :1;
|
||||
u64 ena :1;
|
||||
u64 sel_chan :1;
|
||||
u64 ltype_mask :4;
|
||||
u64 ltype_match :4;
|
||||
u64 reserved_35_63 :29;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* NIX VTAG size */
|
||||
enum nix_vtag_size {
|
||||
VTAGSIZE_T4 = 0x0,
|
||||
VTAGSIZE_T8 = 0x1,
|
||||
};
|
||||
#endif /* RVU_STRUCT_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user