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drm/i915/cnl: Enable wrpll computation for CNL
Enable wrpll computation for Cannonlake platform to support
pll's required for HDMI output. The patch contains the following features
- compute Cannonlake port clock programming
dividers P, Q, and K.
- compute PLL parameters for Cannonlake. These parameters
set the values on DPLL registers.
- find the register values to program wrpll for Cannonlake.
The reference clock can be either 19.2MHz or 24MHz.
v2: rebase
v3: squash wrpll patches into one (Rodrigo)
v4: switch order of getting even dividers (Paulo)
update divider register values for PDiv and KDiv (Paulo)
update wrpll computation algorithm (Paulo)
v5: Remove ref clock division by 1000. (Rodrigo)
v6: Rodrigo rebasing on top of latest code.
Signed-off-by: Kahola, Mika <mika.kahola@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1497047175-27250-18-git-send-email-rodrigo.vivi@intel.com
This commit is contained in:
Kahola, Mika
Rodrigo Vivi
parent
ff15947e0f
commit
1fa62e1b76
@ -2126,17 +2126,153 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
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return ret;
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}
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static void cnl_wrpll_get_multipliers(unsigned int bestdiv,
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unsigned int *pdiv,
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unsigned int *qdiv,
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unsigned int *kdiv)
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{
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/* even dividers */
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if (bestdiv % 2 == 0) {
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if (bestdiv == 2) {
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*pdiv = 2;
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*qdiv = 1;
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*kdiv = 1;
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} else if (bestdiv % 4 == 0) {
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*pdiv = 2;
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*qdiv = bestdiv / 4;
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*kdiv = 2;
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} else if (bestdiv % 6 == 0) {
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*pdiv = 3;
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*qdiv = bestdiv / 6;
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*kdiv = 2;
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} else if (bestdiv % 5 == 0) {
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*pdiv = 5;
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*qdiv = bestdiv / 10;
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*kdiv = 2;
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} else if (bestdiv % 14 == 0) {
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*pdiv = 7;
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*qdiv = bestdiv / 14;
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*kdiv = 2;
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}
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} else {
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if (bestdiv == 3 || bestdiv == 5 || bestdiv == 7) {
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*pdiv = bestdiv;
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*qdiv = 1;
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*kdiv = 1;
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} else { /* 9, 15, 21 */
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*pdiv = bestdiv / 3;
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*qdiv = 1;
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*kdiv = 3;
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}
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}
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}
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static void cnl_wrpll_params_populate(struct skl_wrpll_params *params, uint32_t dco_freq,
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uint32_t ref_freq, uint32_t pdiv, uint32_t qdiv,
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uint32_t kdiv)
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{
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switch (kdiv) {
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case 1:
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params->kdiv = 1;
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break;
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case 2:
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params->kdiv = 2;
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break;
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case 3:
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params->kdiv = 4;
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break;
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default:
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WARN(1, "Incorrect KDiv\n");
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}
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switch (pdiv) {
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case 2:
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params->pdiv = 1;
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break;
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case 3:
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params->pdiv = 2;
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break;
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case 5:
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params->pdiv = 4;
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break;
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case 7:
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params->pdiv = 8;
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break;
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default:
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WARN(1, "Incorrect PDiv\n");
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}
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if (kdiv != 2)
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qdiv = 1;
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params->qdiv_ratio = qdiv;
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params->qdiv_mode = (qdiv == 1) ? 0 : 1;
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params->dco_integer = div_u64(dco_freq, ref_freq);
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params->dco_fraction = div_u64((div_u64((uint64_t)dco_freq<<15, (uint64_t)ref_freq) -
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((uint64_t)params->dco_integer<<15)) * 0x8000, 0x8000);
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}
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static bool
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cnl_ddi_calculate_wrpll(int clock /* in Hz */,
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struct drm_i915_private *dev_priv,
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struct skl_wrpll_params *wrpll_params)
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{
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uint64_t afe_clock = clock * 5 / KHz(1); /* clocks in kHz */
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unsigned int dco_min = 7998 * KHz(1);
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unsigned int dco_max = 10000 * KHz(1);
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unsigned int dco_mid = (dco_min + dco_max) / 2;
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static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16,
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18, 20, 24, 28, 30, 32, 36, 40,
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42, 44, 48, 50, 52, 54, 56, 60,
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64, 66, 68, 70, 72, 76, 78, 80,
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84, 88, 90, 92, 96, 98, 100, 102,
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3, 5, 7, 9, 15, 21 };
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unsigned int d, dco;
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unsigned int dco_centrality = 0;
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unsigned int best_dco_centrality = 999999;
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unsigned int best_div = 0;
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unsigned int best_dco = 0;
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unsigned int pdiv = 0, qdiv = 0, kdiv = 0;
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for (d = 0; d < ARRAY_SIZE(dividers); d++) {
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dco = afe_clock * dividers[d];
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if ((dco <= dco_max) && (dco >= dco_min)) {
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dco_centrality = abs(dco - dco_mid);
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if (dco_centrality < best_dco_centrality) {
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best_dco_centrality = dco_centrality;
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best_div = dividers[d];
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best_dco = dco;
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}
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}
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}
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if (best_div == 0)
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return false;
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cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
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cnl_wrpll_params_populate(wrpll_params, best_dco,
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dev_priv->cdclk.hw.ref, pdiv, qdiv, kdiv);
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return true;
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}
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static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc *crtc,
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struct intel_crtc_state *crtc_state,
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int clock)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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uint32_t cfgcr0, cfgcr1;
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struct skl_wrpll_params wrpll_params = { 0, };
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cfgcr0 = DPLL_CFGCR0_HDMI_MODE;
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/* FIXME: Proper wrpll calculation done in a following patch */
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return false;
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if (!cnl_ddi_calculate_wrpll(clock * 1000, dev_priv, &wrpll_params))
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return false;
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cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) |
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wrpll_params.dco_integer;
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