mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
drm/gm204/disp: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
e16cc45c7d
commit
1f89b4756f
@ -267,6 +267,7 @@ nouveau-y += core/engine/disp/nvd0.o
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nouveau-y += core/engine/disp/nve0.o
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nouveau-y += core/engine/disp/nvf0.o
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nouveau-y += core/engine/disp/gm107.o
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nouveau-y += core/engine/disp/gm204.o
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nouveau-y += core/engine/disp/dacnv50.o
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nouveau-y += core/engine/disp/dport.o
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nouveau-y += core/engine/disp/hdanva3.o
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@ -279,6 +280,7 @@ nouveau-y += core/engine/disp/piornv50.o
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nouveau-y += core/engine/disp/sornv50.o
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nouveau-y += core/engine/disp/sornv94.o
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nouveau-y += core/engine/disp/sornvd0.o
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nouveau-y += core/engine/disp/sorgm204.o
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nouveau-y += core/engine/disp/vga.o
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nouveau-y += core/engine/fifo/base.o
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nouveau-y += core/engine/fifo/nv04.o
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113
drivers/gpu/drm/nouveau/core/engine/disp/gm204.c
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113
drivers/gpu/drm/nouveau/core/engine/disp/gm204.c
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@ -0,0 +1,113 @@
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <engine/software.h>
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#include <engine/disp.h>
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#include <nvif/class.h>
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#include "nv50.h"
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/*******************************************************************************
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* Base display object
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******************************************************************************/
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static struct nouveau_oclass
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gm204_disp_sclass[] = {
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{ GM204_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
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{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
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{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
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{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
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{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
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{}
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};
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static struct nouveau_oclass
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gm204_disp_base_oclass[] = {
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{ GM204_DISP, &nvd0_disp_base_ofuncs },
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{}
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};
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/*******************************************************************************
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* Display engine implementation
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******************************************************************************/
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static int
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gm204_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nv50_disp_priv *priv;
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int heads = nv_rd32(parent, 0x022448);
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int ret;
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ret = nouveau_disp_create(parent, engine, oclass, heads,
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"PDISP", "display", &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
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if (ret)
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return ret;
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nv_engine(priv)->sclass = gm204_disp_base_oclass;
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nv_engine(priv)->cclass = &nv50_disp_cclass;
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nv_subdev(priv)->intr = nvd0_disp_intr;
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INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
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priv->sclass = gm204_disp_sclass;
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priv->head.nr = heads;
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priv->dac.nr = 3;
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priv->sor.nr = 4;
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priv->dac.power = nv50_dac_power;
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priv->dac.sense = nv50_dac_sense;
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priv->sor.power = nv50_sor_power;
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priv->sor.hda_eld = nvd0_hda_eld;
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priv->sor.hdmi = nvd0_hdmi_ctrl;
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return 0;
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}
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struct nouveau_oclass *
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gm204_disp_outp_sclass[] = {
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&gm204_sor_dp_impl.base.base,
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NULL
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};
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struct nouveau_oclass *
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gm204_disp_oclass = &(struct nv50_disp_impl) {
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.base.base.handle = NV_ENGINE(DISP, 0x07),
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.base.base.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = gm204_disp_ctor,
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.dtor = _nouveau_disp_dtor,
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.init = _nouveau_disp_init,
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.fini = _nouveau_disp_fini,
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},
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.base.vblank = &nvd0_disp_vblank_func,
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.base.outp = gm204_disp_outp_sclass,
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.mthd.core = &nve0_disp_mast_mthd_chan,
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.mthd.base = &nvd0_disp_sync_mthd_chan,
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.mthd.ovly = &nve0_disp_ovly_mthd_chan,
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.mthd.prev = -0x020000,
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.head.scanoutpos = nvd0_disp_base_scanoutpos,
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}.base.base;
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@ -242,6 +242,9 @@ int nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int);
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extern struct nouveau_oclass *nv94_disp_outp_sclass[];
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extern struct nvkm_output_dp_impl nvd0_sor_dp_impl;
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int nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool);
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extern struct nouveau_oclass *nvd0_disp_outp_sclass[];
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extern struct nvkm_output_dp_impl gm204_sor_dp_impl;
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#endif
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132
drivers/gpu/drm/nouveau/core/engine/disp/sorgm204.c
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132
drivers/gpu/drm/nouveau/core/engine/disp/sorgm204.c
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@ -0,0 +1,132 @@
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <core/os.h>
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#include <subdev/bios.h>
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#include <subdev/bios/dcb.h>
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#include <subdev/bios/dp.h>
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#include <subdev/bios/init.h>
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#include <subdev/timer.h>
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#include "nv50.h"
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static inline u32
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gm204_sor_soff(struct nvkm_output_dp *outp)
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{
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return (ffs(outp->base.info.or) - 1) * 0x800;
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}
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static inline u32
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gm204_sor_loff(struct nvkm_output_dp *outp)
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{
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return gm204_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
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}
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static inline u32
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gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
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{
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return lane * 0x08;
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}
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static int
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gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
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{
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struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
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const u32 soff = gm204_sor_soff(outp);
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const u32 data = 0x01010101 * pattern;
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if (outp->base.info.sorconf.link & 1)
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nv_mask(priv, 0x61c110 + soff, 0x0f0f0f0f, data);
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else
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nv_mask(priv, 0x61c12c + soff, 0x0f0f0f0f, data);
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return 0;
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}
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static int
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gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
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{
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struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
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const u32 soff = gm204_sor_soff(outp);
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const u32 loff = gm204_sor_loff(outp);
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u32 mask = 0, i;
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for (i = 0; i < nr; i++)
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mask |= 1 << (gm204_sor_dp_lane_map(priv, i) >> 3);
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nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask);
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nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000);
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nv_wait(priv, 0x61c034 + soff, 0x80000000, 0x00000000);
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return 0;
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}
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static int
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gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
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{
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struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
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struct nouveau_bios *bios = nouveau_bios(priv);
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const u32 shift = gm204_sor_dp_lane_map(priv, ln);
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const u32 loff = gm204_sor_loff(outp);
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u32 addr, data[4];
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u8 ver, hdr, cnt, len;
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struct nvbios_dpout info;
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struct nvbios_dpcfg ocfg;
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addr = nvbios_dpout_match(bios, outp->base.info.hasht,
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outp->base.info.hashm,
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&ver, &hdr, &cnt, &len, &info);
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if (!addr)
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return -ENODEV;
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addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe,
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&ver, &hdr, &cnt, &len, &ocfg);
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if (!addr)
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return -EINVAL;
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data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
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data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
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data[2] = nv_rd32(priv, 0x61c130 + loff);
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if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0)
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data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
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nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
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nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
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nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8));
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data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift);
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nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
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return 0;
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}
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struct nvkm_output_dp_impl
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gm204_sor_dp_impl = {
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.base.base.handle = DCB_OUTPUT_DP,
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.base.base.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = _nvkm_output_dp_ctor,
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.dtor = _nvkm_output_dp_dtor,
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.init = _nvkm_output_dp_init,
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.fini = _nvkm_output_dp_fini,
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},
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.pattern = gm204_sor_dp_pattern,
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.lnk_pwr = gm204_sor_dp_lnk_pwr,
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.lnk_ctl = nvd0_sor_dp_lnk_ctl,
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.drv_ctl = gm204_sor_dp_drv_ctl,
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};
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@ -60,7 +60,7 @@ nvd0_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
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return 0;
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}
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static int
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int
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nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
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{
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struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
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@ -51,6 +51,7 @@ nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
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case GK104_DISP_CORE_CHANNEL_DMA:
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case GK110_DISP_CORE_CHANNEL_DMA:
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case GM107_DISP_CORE_CHANNEL_DMA:
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case GM204_DISP_CORE_CHANNEL_DMA:
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case GF110_DISP_BASE_CHANNEL_DMA:
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case GK104_DISP_BASE_CHANNEL_DMA:
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case GK110_DISP_BASE_CHANNEL_DMA:
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@ -31,5 +31,6 @@ extern struct nouveau_oclass *nvd0_disp_oclass;
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extern struct nouveau_oclass *nve0_disp_oclass;
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extern struct nouveau_oclass *nvf0_disp_oclass;
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extern struct nouveau_oclass *gm107_disp_oclass;
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extern struct nouveau_oclass *gm204_disp_oclass;
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#endif
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@ -35,6 +35,7 @@
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#define GK104_DISP 0x00009170
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#define GK110_DISP 0x00009270
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#define GM107_DISP 0x00009470
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#define GM204_DISP 0x00009570
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#define NV50_DISP_CURSOR 0x0000507a
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#define G82_DISP_CURSOR 0x0000827a
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@ -65,6 +66,7 @@
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#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d
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#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d
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#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d
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#define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d
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#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e
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#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e
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