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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b43: HT-PHY: Implement band switching
It works pretty much the same way as in N-PHY. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -476,6 +476,11 @@ enum {
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#define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */
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#define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */
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/* B43_MMIO_PSM_PHY_HDR bits */
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#define B43_PSM_HDR_MAC_PHY_RESET 0x00000001
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#define B43_PSM_HDR_MAC_PHY_CLOCK_EN 0x00000002
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#define B43_PSM_HDR_MAC_PHY_FORCE_CLK 0x00000004
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/* See BCMA_CLKCTLST_EXTRESREQ and BCMA_CLKCTLST_EXTRESST */
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#define B43_BCMA_CLKCTLST_80211_PLL_REQ 0x00000100
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#define B43_BCMA_CLKCTLST_PHY_PLL_REQ 0x00000200
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@ -321,6 +321,26 @@ static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
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b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
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}
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static void b43_phy_ht_bphy_reset(struct b43_wldev *dev, bool reset)
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{
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u16 tmp;
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tmp = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
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b43_write16(dev, B43_MMIO_PSM_PHY_HDR,
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tmp | B43_PSM_HDR_MAC_PHY_FORCE_CLK);
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/* Put BPHY in or take it out of the reset */
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if (reset)
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b43_phy_set(dev, B43_PHY_B_BBCFG,
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B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX);
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else
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b43_phy_mask(dev, B43_PHY_B_BBCFG,
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(u16)~(B43_PHY_B_BBCFG_RSTCCA |
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B43_PHY_B_BBCFG_RSTRX));
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b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp);
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}
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/**************************************************
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* Samples
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**************************************************/
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@ -757,13 +777,19 @@ static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
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const struct b43_phy_ht_channeltab_e_phy *e,
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struct ieee80211_channel *new_channel)
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{
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bool old_band_5ghz;
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if (new_channel->band == IEEE80211_BAND_5GHZ) {
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/* Switch to 2 GHz for a moment to access B-PHY regs */
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b43_phy_mask(dev, B43_PHY_HT_BANDCTL, ~B43_PHY_HT_BANDCTL_5GHZ);
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old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
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if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
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/* TODO */
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} else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
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/* TODO */
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b43_phy_ht_bphy_reset(dev, true);
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/* Switch to 5 GHz */
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b43_phy_set(dev, B43_PHY_HT_BANDCTL, B43_PHY_HT_BANDCTL_5GHZ);
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} else {
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/* Switch to 2 GHz */
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b43_phy_mask(dev, B43_PHY_HT_BANDCTL, ~B43_PHY_HT_BANDCTL_5GHZ);
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b43_phy_ht_bphy_reset(dev, false);
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}
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b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
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@ -106,6 +106,9 @@
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#define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT 0
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#define B43_PHY_HT_TX_PCTL_STATUS_C3 B43_PHY_EXTG(0x169)
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#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001)
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#define B43_PHY_B_BBCFG_RSTCCA 0x4000 /* Reset CCA */
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#define B43_PHY_B_BBCFG_RSTRX 0x8000 /* Reset RX */
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#define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A)
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