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drm/amdgpu: Rename amdgpu_display_framebuffer_domains()
It returns supported domains for display, and domains actually used are to be decided later when pinned. Signed-off-by: Samuel Li <Samuel.Li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -189,7 +189,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
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goto cleanup;
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goto cleanup;
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}
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}
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r = amdgpu_bo_pin(new_abo, amdgpu_display_framebuffer_domains(adev), &base);
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r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev), &base);
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if (unlikely(r != 0)) {
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if (unlikely(r != 0)) {
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DRM_ERROR("failed to pin new abo buffer before flip\n");
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DRM_ERROR("failed to pin new abo buffer before flip\n");
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goto unreserve;
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goto unreserve;
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@ -484,7 +484,7 @@ static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
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.create_handle = drm_gem_fb_create_handle,
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.create_handle = drm_gem_fb_create_handle,
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};
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};
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uint32_t amdgpu_display_framebuffer_domains(struct amdgpu_device *adev)
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uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev)
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{
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{
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uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
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uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
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@ -23,7 +23,7 @@
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#ifndef __AMDGPU_DISPLAY_H__
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#ifndef __AMDGPU_DISPLAY_H__
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#define __AMDGPU_DISPLAY_H__
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#define __AMDGPU_DISPLAY_H__
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uint32_t amdgpu_display_framebuffer_domains(struct amdgpu_device *adev);
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uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev);
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struct drm_framebuffer *
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struct drm_framebuffer *
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amdgpu_display_user_framebuffer_create(struct drm_device *dev,
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amdgpu_display_user_framebuffer_create(struct drm_device *dev,
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struct drm_file *file_priv,
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struct drm_file *file_priv,
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@ -137,7 +137,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
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/* need to align pitch with crtc limits */
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/* need to align pitch with crtc limits */
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mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
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mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
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fb_tiled);
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fb_tiled);
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domain = amdgpu_display_framebuffer_domains(adev);
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domain = amdgpu_display_supported_domains(adev);
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height = ALIGN(mode_cmd->height, 8);
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height = ALIGN(mode_cmd->height, 8);
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size = mode_cmd->pitches[0] * height;
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size = mode_cmd->pitches[0] * height;
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@ -215,7 +215,7 @@ static int amdgpu_gem_begin_cpu_access(struct dma_buf *dma_buf,
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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struct ttm_operation_ctx ctx = { true, false };
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struct ttm_operation_ctx ctx = { true, false };
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u32 domain = amdgpu_display_framebuffer_domains(adev);
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u32 domain = amdgpu_display_supported_domains(adev);
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int ret;
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int ret;
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bool reads = (direction == DMA_BIDIRECTIONAL ||
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bool reads = (direction == DMA_BIDIRECTIONAL ||
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direction == DMA_FROM_DEVICE);
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direction == DMA_FROM_DEVICE);
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@ -3049,12 +3049,11 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
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return r;
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return r;
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if (plane->type != DRM_PLANE_TYPE_CURSOR)
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if (plane->type != DRM_PLANE_TYPE_CURSOR)
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domain = amdgpu_display_framebuffer_domains(adev);
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domain = amdgpu_display_supported_domains(adev);
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else
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else
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domain = AMDGPU_GEM_DOMAIN_VRAM;
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domain = AMDGPU_GEM_DOMAIN_VRAM;
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r = amdgpu_bo_pin(rbo, domain, &afb->address);
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r = amdgpu_bo_pin(rbo, domain, &afb->address);
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amdgpu_bo_unreserve(rbo);
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amdgpu_bo_unreserve(rbo);
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if (unlikely(r != 0)) {
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if (unlikely(r != 0)) {
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