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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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iommu/arm-smmu-v3: Clean up address masking
Before trying to add the SMMUv3.1 support for 52-bit addresses, make things bearable by cleaning up the various address mask definitions to use GENMASK_ULL() consistently. The fact that doing so reveals (and fixes) a latent off-by-one in Q_BASE_ADDR_MASK only goes to show what a jolly good idea it is... Tested-by: Nate Watterson <nwatters@codeaurora.org> Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Robin Murphy
Will Deacon
parent
940ded9c21
commit
1cf9e54e91
@ -22,6 +22,7 @@
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#include <linux/acpi.h>
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#include <linux/acpi_iort.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/dma-iommu.h>
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#include <linux/err.h>
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@ -158,8 +159,7 @@
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#define ARM_SMMU_STRTAB_BASE 0x80
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#define STRTAB_BASE_RA (1UL << 62)
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#define STRTAB_BASE_ADDR_SHIFT 6
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#define STRTAB_BASE_ADDR_MASK 0x3ffffffffffUL
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#define STRTAB_BASE_ADDR_MASK GENMASK_ULL(47, 6)
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#define ARM_SMMU_STRTAB_BASE_CFG 0x88
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#define STRTAB_BASE_CFG_LOG2SIZE_SHIFT 0
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@ -190,8 +190,7 @@
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#define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc
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/* Common MSI config fields */
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#define MSI_CFG0_ADDR_SHIFT 2
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#define MSI_CFG0_ADDR_MASK 0x3fffffffffffUL
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#define MSI_CFG0_ADDR_MASK GENMASK_ULL(47, 2)
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#define MSI_CFG2_SH_SHIFT 4
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#define MSI_CFG2_SH_NSH (0UL << MSI_CFG2_SH_SHIFT)
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#define MSI_CFG2_SH_OSH (2UL << MSI_CFG2_SH_SHIFT)
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@ -207,8 +206,7 @@
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Q_IDX(q, p) * (q)->ent_dwords)
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#define Q_BASE_RWA (1UL << 62)
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#define Q_BASE_ADDR_SHIFT 5
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#define Q_BASE_ADDR_MASK 0xfffffffffffUL
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#define Q_BASE_ADDR_MASK GENMASK_ULL(47, 5)
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#define Q_BASE_LOG2SIZE_SHIFT 0
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#define Q_BASE_LOG2SIZE_MASK 0x1fUL
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@ -225,8 +223,7 @@
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#define STRTAB_L1_DESC_DWORDS 1
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#define STRTAB_L1_DESC_SPAN_SHIFT 0
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#define STRTAB_L1_DESC_SPAN_MASK 0x1fUL
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#define STRTAB_L1_DESC_L2PTR_SHIFT 6
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#define STRTAB_L1_DESC_L2PTR_MASK 0x3ffffffffffUL
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#define STRTAB_L1_DESC_L2PTR_MASK GENMASK_ULL(47, 6)
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#define STRTAB_STE_DWORDS 8
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#define STRTAB_STE_0_V (1UL << 0)
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@ -239,8 +236,7 @@
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#define STRTAB_STE_0_S1FMT_SHIFT 4
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#define STRTAB_STE_0_S1FMT_LINEAR (0UL << STRTAB_STE_0_S1FMT_SHIFT)
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#define STRTAB_STE_0_S1CTXPTR_SHIFT 6
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#define STRTAB_STE_0_S1CTXPTR_MASK 0x3ffffffffffUL
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#define STRTAB_STE_0_S1CTXPTR_MASK GENMASK_ULL(47, 6)
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#define STRTAB_STE_0_S1CDMAX_SHIFT 59
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#define STRTAB_STE_0_S1CDMAX_MASK 0x1fUL
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@ -278,8 +274,7 @@
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#define STRTAB_STE_2_S2PTW (1UL << 54)
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#define STRTAB_STE_2_S2R (1UL << 58)
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#define STRTAB_STE_3_S2TTB_SHIFT 4
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#define STRTAB_STE_3_S2TTB_MASK 0xfffffffffffUL
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#define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(47, 4)
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/* Context descriptor (stage-1 only) */
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#define CTXDESC_CD_DWORDS 8
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@ -325,8 +320,7 @@
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#define CTXDESC_CD_0_ASID_SHIFT 48
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#define CTXDESC_CD_0_ASID_MASK 0xffffUL
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#define CTXDESC_CD_1_TTB0_SHIFT 4
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#define CTXDESC_CD_1_TTB0_MASK 0xfffffffffffUL
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#define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(47, 4)
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#define CTXDESC_CD_3_MAIR_SHIFT 0
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@ -351,7 +345,7 @@
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#define CMDQ_PREFETCH_0_SID_SHIFT 32
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#define CMDQ_PREFETCH_1_SIZE_SHIFT 0
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#define CMDQ_PREFETCH_1_ADDR_MASK ~0xfffUL
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#define CMDQ_PREFETCH_1_ADDR_MASK GENMASK_ULL(63, 12)
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#define CMDQ_CFGI_0_SID_SHIFT 32
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#define CMDQ_CFGI_0_SID_MASK 0xffffffffUL
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@ -362,8 +356,8 @@
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#define CMDQ_TLBI_0_VMID_SHIFT 32
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#define CMDQ_TLBI_0_ASID_SHIFT 48
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#define CMDQ_TLBI_1_LEAF (1UL << 0)
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#define CMDQ_TLBI_1_VA_MASK ~0xfffUL
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#define CMDQ_TLBI_1_IPA_MASK 0xfffffffff000UL
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#define CMDQ_TLBI_1_VA_MASK GENMASK_ULL(63, 12)
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#define CMDQ_TLBI_1_IPA_MASK GENMASK_ULL(47, 12)
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#define CMDQ_PRI_0_SSID_SHIFT 12
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#define CMDQ_PRI_0_SSID_MASK 0xfffffUL
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@ -386,8 +380,7 @@
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#define CMDQ_SYNC_0_MSIATTR_OIWB (0xfUL << CMDQ_SYNC_0_MSIATTR_SHIFT)
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#define CMDQ_SYNC_0_MSIDATA_SHIFT 32
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#define CMDQ_SYNC_0_MSIDATA_MASK 0xffffffffUL
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#define CMDQ_SYNC_1_MSIADDR_SHIFT 0
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#define CMDQ_SYNC_1_MSIADDR_MASK 0xffffffffffffcUL
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#define CMDQ_SYNC_1_MSIADDR_MASK GENMASK_ULL(47, 2)
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/* Event queue */
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#define EVTQ_ENT_DWORDS 4
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@ -413,8 +406,7 @@
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#define PRIQ_1_PRG_IDX_SHIFT 0
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#define PRIQ_1_PRG_IDX_MASK 0x1ffUL
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#define PRIQ_1_ADDR_SHIFT 12
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#define PRIQ_1_ADDR_MASK 0xfffffffffffffUL
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#define PRIQ_1_ADDR_MASK GENMASK_ULL(63, 12)
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/* High-level queue structures */
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#define ARM_SMMU_POLL_TIMEOUT_US 100
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@ -1093,7 +1085,7 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu,
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cfg->cdptr[0] = cpu_to_le64(val);
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val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK << CTXDESC_CD_1_TTB0_SHIFT;
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val = cfg->cd.ttbr & CTXDESC_CD_1_TTB0_MASK;
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cfg->cdptr[1] = cpu_to_le64(val);
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cfg->cdptr[3] = cpu_to_le64(cfg->cd.mair << CTXDESC_CD_3_MAIR_SHIFT);
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@ -1107,8 +1099,7 @@ arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc)
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val |= (desc->span & STRTAB_L1_DESC_SPAN_MASK)
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<< STRTAB_L1_DESC_SPAN_SHIFT;
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val |= desc->l2ptr_dma &
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STRTAB_L1_DESC_L2PTR_MASK << STRTAB_L1_DESC_L2PTR_SHIFT;
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val |= desc->l2ptr_dma & STRTAB_L1_DESC_L2PTR_MASK;
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*dst = cpu_to_le64(val);
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}
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@ -1214,8 +1205,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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!(smmu->features & ARM_SMMU_FEAT_STALL_FORCE))
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dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
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val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK
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<< STRTAB_STE_0_S1CTXPTR_SHIFT) |
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val |= (ste->s1_cfg->cdptr_dma & STRTAB_STE_0_S1CTXPTR_MASK) |
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STRTAB_STE_0_CFG_S1_TRANS;
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}
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@ -1232,7 +1222,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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STRTAB_STE_2_S2R);
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dst[3] = cpu_to_le64(ste->s2_cfg->vttbr &
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STRTAB_STE_3_S2TTB_MASK << STRTAB_STE_3_S2TTB_SHIFT);
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STRTAB_STE_3_S2TTB_MASK);
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val |= STRTAB_STE_0_CFG_S2_TRANS;
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}
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@ -1337,7 +1327,7 @@ static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt)
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evt[0] & PRIQ_0_PERM_READ ? "R" : "",
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evt[0] & PRIQ_0_PERM_WRITE ? "W" : "",
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evt[0] & PRIQ_0_PERM_EXEC ? "X" : "",
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evt[1] & PRIQ_1_ADDR_MASK << PRIQ_1_ADDR_SHIFT);
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evt[1] & PRIQ_1_ADDR_MASK);
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if (last) {
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struct arm_smmu_cmdq_ent cmd = {
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@ -2102,7 +2092,7 @@ static int arm_smmu_init_one_queue(struct arm_smmu_device *smmu,
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q->ent_dwords = dwords;
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q->q_base = Q_BASE_RWA;
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q->q_base |= q->base_dma & Q_BASE_ADDR_MASK << Q_BASE_ADDR_SHIFT;
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q->q_base |= q->base_dma & Q_BASE_ADDR_MASK;
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q->q_base |= (q->max_n_shift & Q_BASE_LOG2SIZE_MASK)
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<< Q_BASE_LOG2SIZE_SHIFT;
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@ -2239,8 +2229,7 @@ static int arm_smmu_init_strtab(struct arm_smmu_device *smmu)
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return ret;
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/* Set the strtab base address */
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reg = smmu->strtab_cfg.strtab_dma &
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STRTAB_BASE_ADDR_MASK << STRTAB_BASE_ADDR_SHIFT;
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reg = smmu->strtab_cfg.strtab_dma & STRTAB_BASE_ADDR_MASK;
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reg |= STRTAB_BASE_RA;
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smmu->strtab_cfg.strtab_base = reg;
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@ -2303,7 +2292,7 @@ static void arm_smmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
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phys_addr_t *cfg = arm_smmu_msi_cfg[desc->platform.msi_index];
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doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo;
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doorbell &= MSI_CFG0_ADDR_MASK << MSI_CFG0_ADDR_SHIFT;
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doorbell &= MSI_CFG0_ADDR_MASK;
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writeq_relaxed(doorbell, smmu->base + cfg[0]);
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writel_relaxed(msg->data, smmu->base + cfg[1]);
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