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drm/amd/display: do not reset lane count in EQ fallback

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[Description]
According to DP1.4 specs we should not reset lane count back
when falling back in failing EQ training.
This causes PHY test pattern compliance to fail as infinite LT
when LT fails EQ to 4 RBR and fails CR in a loop.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wenjing Liu 2017-08-23 17:02:34 -04:00 committed by Alex Deucher
parent 1565904542
commit 1cf49dea28
1 changed files with 0 additions and 2 deletions
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2
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
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@ -1302,8 +1302,6 @@ bool decide_fallback_link_setting(
current_link_setting->lane_count);
} else if (!reached_minimum_link_rate
(current_link_setting->link_rate)) {
current_link_setting->lane_count =
initial_link_settings.lane_count;
current_link_setting->link_rate =
reduce_link_rate(
current_link_setting->link_rate);