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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 10:05:18 +07:00
wil6210: fix eDMA RX chaining
HW requires Rx buffers to be 4 bytes aligned. Modify the driver to meet this requirement. Enable OFU rdy valid bug fix, to prevent hang in oful34_rx while there is back-pressure from host during RX. Signed-off-by: Maya Erez <merez@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -1614,6 +1614,13 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw)
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wil->txrx_ops.configure_interrupt_moderation(wil);
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/* Enable OFU rdy valid bug fix, to prevent hang in oful34_rx
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* while there is back-pressure from Host during RX
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*/
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if (wil->hw_version >= HW_VER_TALYN_MB)
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wil_s(wil, RGF_DMA_MISC_CTL,
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BIT_OFUL34_RDY_VALID_BUG_FIX_EN);
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rc = wil_restore_vifs(wil);
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if (rc) {
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wil_err(wil, "failed to restore vifs, rc %d\n", rc);
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@ -27,6 +27,8 @@
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#include "trace.h"
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#define WIL_EDMA_MAX_DATA_OFFSET (2)
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/* RX buffer size must be aligned to 4 bytes */
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#define WIL_EDMA_RX_BUF_LEN_DEFAULT (2048)
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static void wil_tx_desc_unmap_edma(struct device *dev,
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union wil_tx_desc *desc,
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@ -158,8 +160,7 @@ static int wil_ring_alloc_skb_edma(struct wil6210_priv *wil,
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struct wil_ring *ring, u32 i)
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{
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struct device *dev = wil_to_dev(wil);
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unsigned int sz = wil->rx_buf_len + ETH_HLEN +
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WIL_EDMA_MAX_DATA_OFFSET;
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unsigned int sz = ALIGN(wil->rx_buf_len, 4);
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dma_addr_t pa;
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u16 buff_id;
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struct list_head *active = &wil->rx_buff_mgmt.active;
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@ -600,7 +601,7 @@ static bool wil_is_rx_idle_edma(struct wil6210_priv *wil)
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static void wil_rx_buf_len_init_edma(struct wil6210_priv *wil)
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{
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wil->rx_buf_len = rx_large_buf ?
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WIL_MAX_ETH_MTU : TXRX_BUF_LEN_DEFAULT - WIL_MAX_MPDU_OVERHEAD;
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WIL_MAX_ETH_MTU : WIL_EDMA_RX_BUF_LEN_DEFAULT;
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}
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static int wil_rx_init_edma(struct wil6210_priv *wil, u16 desc_ring_size)
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@ -633,8 +634,7 @@ static int wil_rx_init_edma(struct wil6210_priv *wil, u16 desc_ring_size)
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wil_rx_buf_len_init_edma(wil);
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max_rx_pl_per_desc = wil->rx_buf_len + ETH_HLEN +
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WIL_EDMA_MAX_DATA_OFFSET;
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max_rx_pl_per_desc = ALIGN(wil->rx_buf_len, 4);
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/* Use debugfs dbg_num_rx_srings if set, reserve one sring for TX */
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if (wil->num_rx_status_rings > WIL6210_MAX_STATUS_RINGS - 1)
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@ -869,8 +869,7 @@ static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil,
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struct sk_buff *skb;
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dma_addr_t pa;
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struct wil_ring_rx_data *rxdata = &sring->rx_data;
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unsigned int sz = wil->rx_buf_len + ETH_HLEN +
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WIL_EDMA_MAX_DATA_OFFSET;
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unsigned int sz = ALIGN(wil->rx_buf_len, 4);
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struct wil_net_stats *stats = NULL;
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u16 dmalen;
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int cid;
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@ -302,6 +302,8 @@ struct RGF_ICR {
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#define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2)
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#define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3)
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#define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4)
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#define RGF_DMA_MISC_CTL (0x881d6c)
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#define BIT_OFUL34_RDY_VALID_BUG_FIX_EN BIT(7)
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#define RGF_DMA_PSEUDO_CAUSE (0x881c68)
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#define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c)
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