mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge branch 'pm-opp'
* pm-opp: PM / OPP: Add binding for 'opp-suspend' PM / OPP: Allow multiple OPP tables to be passed via DT PM / OPP: Add new bindings to address shortcomings of existing bindings
This commit is contained in:
Rafael J. Wysocki
commit
1af858fdd2
@ -1,8 +1,19 @@
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* Generic OPP Interface
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Generic OPP (Operating Performance Points) Bindings
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----------------------------------------------------
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SoCs have a standard set of tuples consisting of frequency and
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voltage pairs that the device will support per voltage domain. These
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are called Operating Performance Points or OPPs.
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Devices work at voltage-current-frequency combinations and some implementations
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have the liberty of choosing these. These combinations are called Operating
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Performance Points aka OPPs. This document defines bindings for these OPPs
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applicable across wide range of devices. For illustration purpose, this document
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uses CPU as a device.
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This document contain multiple versions of OPP binding and only one of them
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should be used per device.
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Binding 1: operating-points
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============================
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This binding only supports voltage-frequency pairs.
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Properties:
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- operating-points: An array of 2-tuples items, and each item consists
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@ -23,3 +34,432 @@ cpu@0 {
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198000 850000
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>;
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};
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Binding 2: operating-points-v2
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============================
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* Property: operating-points-v2
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Devices supporting OPPs must set their "operating-points-v2" property with
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phandle to a OPP table in their DT node. The OPP core will use this phandle to
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find the operating points for the device.
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Devices may want to choose OPP tables at runtime and so can provide a list of
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phandles here. But only *one* of them should be chosen at runtime. This must be
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accompanied by a corresponding "operating-points-names" property, to uniquely
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identify the OPP tables.
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If required, this can be extended for SoC vendor specfic bindings. Such bindings
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should be documented as Documentation/devicetree/bindings/power/<vendor>-opp.txt
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and should have a compatible description like: "operating-points-v2-<vendor>".
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Optional properties:
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- operating-points-names: Names of OPP tables (required if multiple OPP
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tables are present), to uniquely identify them. The same list must be present
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for all the CPUs which are sharing clock/voltage rails and hence the OPP
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tables.
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* OPP Table Node
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This describes the OPPs belonging to a device. This node can have following
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properties:
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Required properties:
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- compatible: Allow OPPs to express their compatibility. It should be:
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"operating-points-v2".
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- OPP nodes: One or more OPP nodes describing voltage-current-frequency
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combinations. Their name isn't significant but their phandle can be used to
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reference an OPP.
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Optional properties:
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- opp-shared: Indicates that device nodes using this OPP Table Node's phandle
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switch their DVFS state together, i.e. they share clock/voltage/current lines.
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Missing property means devices have independent clock/voltage/current lines,
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but they share OPP tables.
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- status: Marks the OPP table enabled/disabled.
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* OPP Node
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This defines voltage-current-frequency combinations along with other related
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properties.
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Required properties:
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- opp-hz: Frequency in Hz
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Optional properties:
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- opp-microvolt: voltage in micro Volts.
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A single regulator's voltage is specified with an array of size one or three.
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Single entry is for target voltage and three entries are for <target min max>
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voltages.
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Entries for multiple regulators must be present in the same order as
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regulators are specified in device's DT node.
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- opp-microamp: The maximum current drawn by the device in microamperes
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considering system specific parameters (such as transients, process, aging,
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maximum operating temperature range etc.) as necessary. This may be used to
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set the most efficient regulator operating mode.
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Should only be set if opp-microvolt is set for the OPP.
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Entries for multiple regulators must be present in the same order as
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regulators are specified in device's DT node. If this property isn't required
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for few regulators, then this should be marked as zero for them. If it isn't
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required for any regulator, then this property need not be present.
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- clock-latency-ns: Specifies the maximum possible transition latency (in
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nanoseconds) for switching to this OPP from any other OPP.
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- turbo-mode: Marks the OPP to be used only for turbo modes. Turbo mode is
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available on some platforms, where the device can run over its operating
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frequency for a short duration of time limited by the device's power, current
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and thermal limits.
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- opp-suspend: Marks the OPP to be used during device suspend. Only one OPP in
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the table should have this.
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- status: Marks the node enabled/disabled.
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Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together.
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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reg = <0>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 0>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply0>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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reg = <1>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 0>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply0>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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};
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cpu0_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = <1000000000>;
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opp-microvolt = <970000 975000 985000>;
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opp-microamp = <70000>;
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clock-latency-ns = <300000>;
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opp-suspend;
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};
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opp01 {
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opp-hz = <1100000000>;
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opp-microvolt = <980000 1000000 1010000>;
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opp-microamp = <80000>;
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clock-latency-ns = <310000>;
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};
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opp02 {
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opp-hz = <1200000000>;
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opp-microvolt = <1025000>;
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clock-latency-ns = <290000>;
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turbo-mode;
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};
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};
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};
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Example 2: Single cluster, Quad-core Qualcom-krait, switches DVFS states
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independently.
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "qcom,krait";
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reg = <0>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 0>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply0>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@1 {
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compatible = "qcom,krait";
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reg = <1>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 1>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply1>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@2 {
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compatible = "qcom,krait";
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reg = <2>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 2>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply2>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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cpu@3 {
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compatible = "qcom,krait";
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reg = <3>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 3>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply3>;
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operating-points-v2 = <&cpu_opp_table>;
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};
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};
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cpu_opp_table: opp_table {
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compatible = "operating-points-v2";
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/*
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* Missing opp-shared property means CPUs switch DVFS states
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* independently.
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*/
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opp00 {
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opp-hz = <1000000000>;
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opp-microvolt = <970000 975000 985000>;
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opp-microamp = <70000>;
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clock-latency-ns = <300000>;
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opp-suspend;
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};
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opp01 {
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opp-hz = <1100000000>;
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opp-microvolt = <980000 1000000 1010000>;
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opp-microamp = <80000>;
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clock-latency-ns = <310000>;
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};
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opp02 {
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opp-hz = <1200000000>;
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opp-microvolt = <1025000>;
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opp-microamp = <90000;
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lock-latency-ns = <290000>;
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turbo-mode;
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};
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};
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};
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Example 3: Dual-cluster, Dual-core per cluster. CPUs within a cluster switch
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DVFS state together.
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a7";
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reg = <0>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 0>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply0>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu@1 {
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compatible = "arm,cortex-a7";
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reg = <1>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 0>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply0>;
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operating-points-v2 = <&cluster0_opp>;
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};
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cpu@100 {
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compatible = "arm,cortex-a15";
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reg = <100>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 1>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply1>;
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operating-points-v2 = <&cluster1_opp>;
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};
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cpu@101 {
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compatible = "arm,cortex-a15";
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reg = <101>;
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next-level-cache = <&L2>;
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clocks = <&clk_controller 1>;
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clock-names = "cpu";
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cpu-supply = <&cpu_supply1>;
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operating-points-v2 = <&cluster1_opp>;
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};
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};
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = <1000000000>;
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opp-microvolt = <970000 975000 985000>;
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opp-microamp = <70000>;
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clock-latency-ns = <300000>;
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opp-suspend;
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};
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opp01 {
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opp-hz = <1100000000>;
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opp-microvolt = <980000 1000000 1010000>;
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opp-microamp = <80000>;
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clock-latency-ns = <310000>;
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};
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opp02 {
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opp-hz = <1200000000>;
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opp-microvolt = <1025000>;
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opp-microamp = <90000>;
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clock-latency-ns = <290000>;
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turbo-mode;
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};
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};
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cluster1_opp: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp10 {
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opp-hz = <1300000000>;
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opp-microvolt = <1045000 1050000 1055000>;
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opp-microamp = <95000>;
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clock-latency-ns = <400000>;
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opp-suspend;
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};
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opp11 {
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opp-hz = <1400000000>;
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opp-microvolt = <1075000>;
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opp-microamp = <100000>;
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clock-latency-ns = <400000>;
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};
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opp12 {
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opp-hz = <1500000000>;
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opp-microvolt = <1010000 1100000 1110000>;
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opp-microamp = <95000>;
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clock-latency-ns = <400000>;
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turbo-mode;
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};
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};
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};
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Example 4: Handling multiple regulators
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/ {
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cpus {
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cpu@0 {
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compatible = "arm,cortex-a7";
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...
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cpu-supply = <&cpu_supply0>, <&cpu_supply1>, <&cpu_supply2>;
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operating-points-v2 = <&cpu0_opp_table>;
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};
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};
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cpu0_opp_table: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = <1000000000>;
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opp-microvolt = <970000>, /* Supply 0 */
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<960000>, /* Supply 1 */
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<960000>; /* Supply 2 */
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opp-microamp = <70000>, /* Supply 0 */
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<70000>, /* Supply 1 */
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<70000>; /* Supply 2 */
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clock-latency-ns = <300000>;
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};
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/* OR */
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opp00 {
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opp-hz = <1000000000>;
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opp-microvolt = <970000 975000 985000>, /* Supply 0 */
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<960000 965000 975000>, /* Supply 1 */
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<960000 965000 975000>; /* Supply 2 */
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opp-microamp = <70000>, /* Supply 0 */
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<70000>, /* Supply 1 */
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<70000>; /* Supply 2 */
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clock-latency-ns = <300000>;
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};
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/* OR */
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opp00 {
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opp-hz = <1000000000>;
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opp-microvolt = <970000 975000 985000>, /* Supply 0 */
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<960000 965000 975000>, /* Supply 1 */
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<960000 965000 975000>; /* Supply 2 */
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opp-microamp = <70000>, /* Supply 0 */
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<0>, /* Supply 1 doesn't need this */
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<70000>; /* Supply 2 */
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clock-latency-ns = <300000>;
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};
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};
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};
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Example 5: Multiple OPP tables
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/ {
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cpus {
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cpu@0 {
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compatible = "arm,cortex-a7";
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...
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cpu-supply = <&cpu_supply>
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operating-points-v2 = <&cpu0_opp_table_slow>, <&cpu0_opp_table_fast>;
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operating-points-names = "slow", "fast";
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};
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};
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cpu0_opp_table_slow: opp_table_slow {
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compatible = "operating-points-v2";
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status = "okay";
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opp-shared;
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opp00 {
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opp-hz = <600000000>;
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...
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};
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opp01 {
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opp-hz = <800000000>;
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...
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};
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};
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cpu0_opp_table_fast: opp_table_fast {
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compatible = "operating-points-v2";
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status = "okay";
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opp-shared;
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opp10 {
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opp-hz = <1000000000>;
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...
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};
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opp11 {
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opp-hz = <1100000000>;
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...
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};
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};
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};
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Loading…
Reference in New Issue
Block a user