mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 14:36:46 +07:00
dmaengine: vdma: Add support for mulit-channel dma mode
This patch adds support for AXI DMA multi-channel dma mode Multichannel mode enables DMA to connect to multiple masters and slaves on the streaming side. In Multichannel mode AXI DMA supports 2D transfers. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Kedareswara rao Appana
Vinod Koul
parent
ba2c194e6c
commit
1a9e7a03c7
@ -114,7 +114,7 @@
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#define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n))
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/* HW specific definitions */
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#define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2
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#define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x20
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#define XILINX_DMA_DMAXR_ALL_IRQ_MASK \
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(XILINX_DMA_DMASR_FRM_CNT_IRQ | \
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@ -165,6 +165,18 @@
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#define XILINX_DMA_COALESCE_MAX 255
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#define XILINX_DMA_NUM_APP_WORDS 5
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/* Multi-Channel DMA Descriptor offsets*/
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#define XILINX_DMA_MCRX_CDESC(x) (0x40 + (x-1) * 0x20)
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#define XILINX_DMA_MCRX_TDESC(x) (0x48 + (x-1) * 0x20)
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/* Multi-Channel DMA Masks/Shifts */
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#define XILINX_DMA_BD_HSIZE_MASK GENMASK(15, 0)
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#define XILINX_DMA_BD_STRIDE_MASK GENMASK(15, 0)
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#define XILINX_DMA_BD_VSIZE_MASK GENMASK(31, 19)
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#define XILINX_DMA_BD_TDEST_MASK GENMASK(4, 0)
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#define XILINX_DMA_BD_STRIDE_SHIFT 0
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#define XILINX_DMA_BD_VSIZE_SHIFT 19
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/* AXI CDMA Specific Registers/Offsets */
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#define XILINX_CDMA_REG_SRCADDR 0x18
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#define XILINX_CDMA_REG_DSTADDR 0x20
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@ -210,8 +222,8 @@ struct xilinx_axidma_desc_hw {
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u32 next_desc_msb;
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u32 buf_addr;
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u32 buf_addr_msb;
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u32 pad1;
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u32 pad2;
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u32 mcdma_control;
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u32 vsize_stride;
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u32 control;
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u32 status;
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u32 app[XILINX_DMA_NUM_APP_WORDS];
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@ -349,6 +361,7 @@ struct xilinx_dma_chan {
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struct xilinx_axidma_tx_segment *seg_v;
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struct xilinx_axidma_tx_segment *cyclic_seg_v;
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void (*start_transfer)(struct xilinx_dma_chan *chan);
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u16 tdest;
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};
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struct xilinx_dma_config {
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@ -365,6 +378,7 @@ struct xilinx_dma_config {
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* @common: DMA device structure
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* @chan: Driver specific DMA channel
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* @has_sg: Specifies whether Scatter-Gather is present or not
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* @mcdma: Specifies whether Multi-Channel is present or not
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* @flush_on_fsync: Flush on frame sync
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* @ext_addr: Indicates 64 bit addressing is supported by dma device
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* @pdev: Platform device structure pointer
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@ -374,6 +388,8 @@ struct xilinx_dma_config {
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* @txs_clk: DMA mm2s stream clock
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* @rx_clk: DMA s2mm clock
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* @rxs_clk: DMA s2mm stream clock
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* @nr_channels: Number of channels DMA device supports
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* @chan_id: DMA channel identifier
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*/
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struct xilinx_dma_device {
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void __iomem *regs;
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@ -381,6 +397,7 @@ struct xilinx_dma_device {
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struct dma_device common;
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struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE];
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bool has_sg;
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bool mcdma;
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u32 flush_on_fsync;
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bool ext_addr;
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struct platform_device *pdev;
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@ -390,6 +407,8 @@ struct xilinx_dma_device {
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struct clk *txs_clk;
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struct clk *rx_clk;
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struct clk *rxs_clk;
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u32 nr_channels;
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u32 chan_id;
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};
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/* Macros */
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@ -1196,18 +1215,20 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
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tail_segment = list_last_entry(&tail_desc->segments,
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struct xilinx_axidma_tx_segment, node);
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old_head = list_first_entry(&head_desc->segments,
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struct xilinx_axidma_tx_segment, node);
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new_head = chan->seg_v;
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/* Copy Buffer Descriptor fields. */
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new_head->hw = old_head->hw;
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if (chan->has_sg && !chan->xdev->mcdma) {
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old_head = list_first_entry(&head_desc->segments,
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struct xilinx_axidma_tx_segment, node);
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new_head = chan->seg_v;
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/* Copy Buffer Descriptor fields. */
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new_head->hw = old_head->hw;
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/* Swap and save new reserve */
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list_replace_init(&old_head->node, &new_head->node);
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chan->seg_v = old_head;
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/* Swap and save new reserve */
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list_replace_init(&old_head->node, &new_head->node);
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chan->seg_v = old_head;
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tail_segment->hw.next_desc = chan->seg_v->phys;
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head_desc->async_tx.phys = new_head->phys;
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tail_segment->hw.next_desc = chan->seg_v->phys;
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head_desc->async_tx.phys = new_head->phys;
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}
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reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR);
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@ -1218,23 +1239,53 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
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dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
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}
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if (chan->has_sg)
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if (chan->has_sg && !chan->xdev->mcdma)
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xilinx_write(chan, XILINX_DMA_REG_CURDESC,
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head_desc->async_tx.phys);
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if (chan->has_sg && chan->xdev->mcdma) {
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if (chan->direction == DMA_MEM_TO_DEV) {
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dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
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head_desc->async_tx.phys);
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} else {
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if (!chan->tdest) {
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dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC,
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head_desc->async_tx.phys);
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} else {
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dma_ctrl_write(chan,
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XILINX_DMA_MCRX_CDESC(chan->tdest),
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head_desc->async_tx.phys);
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}
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}
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}
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xilinx_dma_start(chan);
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if (chan->err)
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return;
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/* Start the transfer */
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if (chan->has_sg) {
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if (chan->has_sg && !chan->xdev->mcdma) {
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if (chan->cyclic)
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xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
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chan->cyclic_seg_v->phys);
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else
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xilinx_write(chan, XILINX_DMA_REG_TAILDESC,
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tail_segment->phys);
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} else if (chan->has_sg && chan->xdev->mcdma) {
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if (chan->direction == DMA_MEM_TO_DEV) {
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dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
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tail_segment->phys);
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} else {
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if (!chan->tdest) {
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dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
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tail_segment->phys);
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} else {
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dma_ctrl_write(chan,
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XILINX_DMA_MCRX_TDESC(chan->tdest),
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tail_segment->phys);
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}
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}
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} else {
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struct xilinx_axidma_tx_segment *segment;
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struct xilinx_axidma_desc_hw *hw;
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@ -1861,6 +1912,90 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic(
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return NULL;
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}
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/**
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* xilinx_dma_prep_interleaved - prepare a descriptor for a
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* DMA_SLAVE transaction
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* @dchan: DMA channel
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* @xt: Interleaved template pointer
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* @flags: transfer ack flags
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*
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* Return: Async transaction descriptor on success and NULL on failure
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*/
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static struct dma_async_tx_descriptor *
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xilinx_dma_prep_interleaved(struct dma_chan *dchan,
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struct dma_interleaved_template *xt,
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unsigned long flags)
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{
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struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
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struct xilinx_dma_tx_descriptor *desc;
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struct xilinx_axidma_tx_segment *segment;
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struct xilinx_axidma_desc_hw *hw;
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if (!is_slave_direction(xt->dir))
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return NULL;
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if (!xt->numf || !xt->sgl[0].size)
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return NULL;
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if (xt->frame_size != 1)
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return NULL;
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/* Allocate a transaction descriptor. */
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desc = xilinx_dma_alloc_tx_descriptor(chan);
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if (!desc)
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return NULL;
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chan->direction = xt->dir;
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dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
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desc->async_tx.tx_submit = xilinx_dma_tx_submit;
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/* Get a free segment */
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segment = xilinx_axidma_alloc_tx_segment(chan);
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if (!segment)
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goto error;
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hw = &segment->hw;
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/* Fill in the descriptor */
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if (xt->dir != DMA_MEM_TO_DEV)
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hw->buf_addr = xt->dst_start;
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else
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hw->buf_addr = xt->src_start;
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hw->mcdma_control = chan->tdest & XILINX_DMA_BD_TDEST_MASK;
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hw->vsize_stride = (xt->numf << XILINX_DMA_BD_VSIZE_SHIFT) &
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XILINX_DMA_BD_VSIZE_MASK;
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hw->vsize_stride |= (xt->sgl[0].icg + xt->sgl[0].size) &
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XILINX_DMA_BD_STRIDE_MASK;
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hw->control = xt->sgl[0].size & XILINX_DMA_BD_HSIZE_MASK;
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/*
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* Insert the segment into the descriptor segments
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* list.
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*/
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list_add_tail(&segment->node, &desc->segments);
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segment = list_first_entry(&desc->segments,
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struct xilinx_axidma_tx_segment, node);
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desc->async_tx.phys = segment->phys;
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/* For the last DMA_MEM_TO_DEV transfer, set EOP */
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if (xt->dir == DMA_MEM_TO_DEV) {
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segment->hw.control |= XILINX_DMA_BD_SOP;
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segment = list_last_entry(&desc->segments,
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struct xilinx_axidma_tx_segment,
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node);
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segment->hw.control |= XILINX_DMA_BD_EOP;
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}
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return &desc->async_tx;
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error:
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xilinx_dma_free_tx_descriptor(chan, desc);
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return NULL;
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}
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/**
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* xilinx_dma_terminate_all - Halt the channel and free descriptors
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* @chan: Driver specific DMA Channel pointer
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@ -2176,7 +2311,7 @@ static void xdma_disable_allclks(struct xilinx_dma_device *xdev)
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* Return: '0' on success and failure value on error
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*/
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static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
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struct device_node *node)
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struct device_node *node, int chan_id)
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{
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struct xilinx_dma_chan *chan;
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bool has_dre = false;
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@ -2220,7 +2355,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
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if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel")) {
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chan->direction = DMA_MEM_TO_DEV;
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chan->id = 0;
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chan->id = chan_id;
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chan->tdest = chan_id;
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chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
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if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
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@ -2233,7 +2369,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
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} else if (of_device_is_compatible(node,
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"xlnx,axi-vdma-s2mm-channel")) {
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chan->direction = DMA_DEV_TO_MEM;
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chan->id = 1;
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chan->id = chan_id;
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chan->tdest = chan_id - xdev->nr_channels;
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chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
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if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
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@ -2287,6 +2424,32 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
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return 0;
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}
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/**
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* xilinx_dma_child_probe - Per child node probe
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* It get number of dma-channels per child node from
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* device-tree and initializes all the channels.
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*
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* @xdev: Driver specific device structure
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* @node: Device node
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*
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* Return: 0 always.
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*/
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static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev,
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struct device_node *node) {
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int ret, i, nr_channels = 1;
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ret = of_property_read_u32(node, "dma-channels", &nr_channels);
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if ((ret < 0) && xdev->mcdma)
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dev_warn(xdev->dev, "missing dma-channels property\n");
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for (i = 0; i < nr_channels; i++)
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xilinx_dma_chan_probe(xdev, node, xdev->chan_id++);
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xdev->nr_channels += nr_channels;
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return 0;
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}
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/**
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* of_dma_xilinx_xlate - Translation function
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* @dma_spec: Pointer to DMA specifier as found in the device tree
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@ -2300,7 +2463,7 @@ static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
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struct xilinx_dma_device *xdev = ofdma->of_dma_data;
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int chan_id = dma_spec->args[0];
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if (chan_id >= XILINX_DMA_MAX_CHANS_PER_DEVICE || !xdev->chan[chan_id])
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if (chan_id >= xdev->nr_channels || !xdev->chan[chan_id])
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return NULL;
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return dma_get_slave_channel(&xdev->chan[chan_id]->common);
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@ -2376,6 +2539,8 @@ static int xilinx_dma_probe(struct platform_device *pdev)
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/* Retrieve the DMA engine properties from the device tree */
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xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg");
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if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA)
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xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma");
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if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
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err = of_property_read_u32(node, "xlnx,num-fstores",
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@ -2426,6 +2591,8 @@ static int xilinx_dma_probe(struct platform_device *pdev)
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xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg;
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xdev->common.device_prep_dma_cyclic =
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xilinx_dma_prep_dma_cyclic;
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xdev->common.device_prep_interleaved_dma =
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xilinx_dma_prep_interleaved;
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/* Residue calculation is supported by only AXI DMA */
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xdev->common.residue_granularity =
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DMA_RESIDUE_GRANULARITY_SEGMENT;
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@ -2441,13 +2608,13 @@ static int xilinx_dma_probe(struct platform_device *pdev)
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/* Initialize the channels */
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for_each_child_of_node(node, child) {
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err = xilinx_dma_chan_probe(xdev, child);
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err = xilinx_dma_child_probe(xdev, child);
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if (err < 0)
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goto disable_clks;
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}
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if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
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for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++)
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for (i = 0; i < xdev->nr_channels; i++)
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if (xdev->chan[i])
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xdev->chan[i]->num_frms = num_frames;
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}
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@ -2470,7 +2637,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
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disable_clks:
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xdma_disable_allclks(xdev);
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error:
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for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++)
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for (i = 0; i < xdev->nr_channels; i++)
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if (xdev->chan[i])
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xilinx_dma_chan_remove(xdev->chan[i]);
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@ -2492,7 +2659,7 @@ static int xilinx_dma_remove(struct platform_device *pdev)
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dma_async_device_unregister(&xdev->common);
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for (i = 0; i < XILINX_DMA_MAX_CHANS_PER_DEVICE; i++)
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for (i = 0; i < xdev->nr_channels; i++)
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if (xdev->chan[i])
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xilinx_dma_chan_remove(xdev->chan[i]);
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