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crypto: caam - make CAAM_PTR_SZ dynamic
In order to be able to configure CAAM pointer size at run-time, which needed to support i.MX8MQ, which is 64-bit SoC with 32-bit pointer size, convert CAAM_PTR_SZ to refer to a global variable of the same name ("caam_ptr_sz") and adjust the rest of the code accordingly. No functional change intended. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Chris Spencer <christopher.spencer@sea.co.uk> Cc: Cory Tusar <cory.tusar@zii.aero> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Horia Geantă <horia.geanta@nxp.com> Cc: Aymen Sghaier <aymen.sghaier@nxp.com> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: linux-crypto@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -74,7 +74,7 @@
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#define CHACHAPOLY_DESC_JOB_IO_LEN (AEAD_DESC_JOB_IO_LEN + CAAM_CMD_SZ * 6)
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#define DESC_MAX_USED_BYTES (CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN)
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#define DESC_MAX_USED_BYTES (CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN_MIN)
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#define DESC_MAX_USED_LEN (DESC_MAX_USED_BYTES / CAAM_CMD_SZ)
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struct caam_alg_entry {
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@ -560,7 +560,7 @@ struct ahash_edesc {
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dma_addr_t sec4_sg_dma;
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int src_nents;
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int sec4_sg_bytes;
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u32 hw_desc[DESC_JOB_IO_LEN / sizeof(u32)] ____cacheline_aligned;
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u32 hw_desc[DESC_JOB_IO_LEN_MAX / sizeof(u32)] ____cacheline_aligned;
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struct sec4_sg_entry sec4_sg[0];
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};
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@ -53,7 +53,7 @@
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L1_CACHE_BYTES)
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/* length of descriptors */
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#define DESC_JOB_O_LEN (CAAM_CMD_SZ * 2 + CAAM_PTR_SZ * 2)
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#define DESC_JOB_O_LEN (CAAM_CMD_SZ * 2 + CAAM_PTR_SZ_MAX * 2)
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#define DESC_RNG_LEN (3 * CAAM_CMD_SZ)
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/* Buffer, its dma address and lock */
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@ -602,6 +602,7 @@ static int caam_probe(struct platform_device *pdev)
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caam_imx = (bool)imx_soc_match;
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comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
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caam_ptr_sz = sizeof(dma_addr_t);
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caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
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ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
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@ -14,9 +14,14 @@
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#define IMMEDIATE (1 << 23)
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#define CAAM_CMD_SZ sizeof(u32)
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#define CAAM_PTR_SZ sizeof(dma_addr_t)
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#define CAAM_PTR_SZ caam_ptr_sz
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#define CAAM_PTR_SZ_MAX sizeof(dma_addr_t)
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#define CAAM_PTR_SZ_MIN sizeof(u32)
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#define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE)
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#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3)
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#define __DESC_JOB_IO_LEN(n) (CAAM_CMD_SZ * 5 + (n) * 3)
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#define DESC_JOB_IO_LEN __DESC_JOB_IO_LEN(CAAM_PTR_SZ)
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#define DESC_JOB_IO_LEN_MAX __DESC_JOB_IO_LEN(CAAM_PTR_SZ_MAX)
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#define DESC_JOB_IO_LEN_MIN __DESC_JOB_IO_LEN(CAAM_PTR_SZ_MIN)
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/*
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* The CAAM QI hardware constructs a job descriptor which points
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@ -43,7 +48,7 @@
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* get loaded in deco buffer are '8' or '11'. The remaining words
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* in deco buffer can be used for storing shared descriptor.
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*/
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#define MAX_SDLEN ((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN) / CAAM_CMD_SZ)
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#define MAX_SDLEN ((CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN_MIN) / CAAM_CMD_SZ)
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#ifdef DEBUG
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#define PRINT_POS do { printk(KERN_DEBUG "%02d: %s\n", desc_len(desc),\
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@ -64,6 +69,7 @@
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(LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
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extern bool caam_little_end;
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extern size_t caam_ptr_sz;
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/*
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* HW fetches 4 S/G table entries at a time, irrespective of how many entries
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@ -56,6 +56,9 @@ EXPORT_SYMBOL(caam_little_end);
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bool caam_imx;
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EXPORT_SYMBOL(caam_imx);
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size_t caam_ptr_sz;
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EXPORT_SYMBOL(caam_ptr_sz);
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static const struct {
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u8 value;
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const char *error_text;
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