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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/amd/display: fix mpc alpha programming
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin
Alex Deucher
parent
8eee20139a
commit
1a2c82a2f1
@ -125,14 +125,8 @@ static void lock_otg_master_update(
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HWSEQ_REG_UPDATE(OTG0_OTG_GLOBAL_CONTROL0,
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OTG_MASTER_UPDATE_LOCK_SEL, inst);
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/* unlock master locker */
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HWSEQ_REG_UPDATE(OTG0_OTG_MASTER_UPDATE_LOCK,
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OTG_MASTER_UPDATE_LOCK, 1);
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/* wait for unlock happens */
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if (!wait_reg(ctx, inst_offset, OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, 1))
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BREAK_TO_DEBUGGER();
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}
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static bool unlock_master_tg_and_wait(
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@ -1562,8 +1556,9 @@ static void update_dchubp_dpp(
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enum dc_color_space color_space;
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struct tg_color black_color = {0};
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struct dcn10_mpc *mpc = TO_DCN10_MPC(dc->res_pool->mpc);
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struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
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struct pipe_ctx *temp_pipe;
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int i;
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int tree_pos = 0;
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/* depends on DML calculation, DPP clock value may change dynamically */
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enable_dppclk(
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@ -1609,41 +1604,30 @@ static void update_dchubp_dpp(
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/* TODO: build stream pipes group id. For now, use stream otg
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* id as pipe group id
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*/
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/*pipe_ctx->scl_data.lb_params.alpha_en = pipe_ctx->surface->public.per_pixel_alpha;*/
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if (pipe_ctx->bottom_pipe && surface != pipe_ctx->bottom_pipe->surface)
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pipe_ctx->scl_data.lb_params.alpha_en = 1;
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else
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pipe_ctx->scl_data.lb_params.alpha_en = 0;
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pipe_ctx->mpc_idx = pipe_ctx->tg->inst;
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tree_cfg = &context->res_ctx.mpc_tree[pipe_ctx->mpc_idx];
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/* enable when bottom pipe is present and
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* it does not share a surface with current pipe
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*/
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if (pipe_ctx->bottom_pipe && surface != pipe_ctx->bottom_pipe->surface) {
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pipe_ctx->scl_data.lb_params.alpha_en = 1;
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tree_cfg->mode = TOP_BLND;
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} else {
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pipe_ctx->scl_data.lb_params.alpha_en = 0;
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tree_cfg->mode = TOP_PASSTHRU;
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}
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if (!pipe_ctx->top_pipe && !cur_pipe_ctx->bottom_pipe) {
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/* primary pipe, set mpc tree index 0 only */
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tree_cfg->num_pipes = 1;
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if (tree_cfg->num_pipes == 0) {
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tree_cfg->opp_id = pipe_ctx->tg->inst;
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tree_cfg->dpp[0] = pipe_ctx->pipe_idx;
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tree_cfg->mpcc[0] = pipe_ctx->pipe_idx;
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for (i = 0; i < MAX_PIPES; i++) {
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tree_cfg->dpp[i] = 0xf;
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tree_cfg->mpcc[i] = 0xf;
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}
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}
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if (!cur_pipe_ctx->top_pipe && !pipe_ctx->top_pipe) {
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if (!cur_pipe_ctx->bottom_pipe)
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dcn10_set_mpc_tree(mpc, tree_cfg);
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} else if (!cur_pipe_ctx->top_pipe && pipe_ctx->top_pipe) {
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dcn10_add_dpp(mpc, tree_cfg,
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pipe_ctx->pipe_idx, pipe_ctx->pipe_idx, 1);
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} else {
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/* nothing to be done here */
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ASSERT(cur_pipe_ctx->top_pipe && pipe_ctx->top_pipe);
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}
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for (temp_pipe = pipe_ctx->top_pipe;
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temp_pipe != NULL; temp_pipe = temp_pipe->top_pipe)
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tree_pos++;
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tree_cfg->dpp[tree_pos] = pipe_ctx->pipe_idx;
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tree_cfg->mpcc[tree_pos] = pipe_ctx->pipe_idx;
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tree_cfg->per_pixel_alpha[tree_pos] = pipe_ctx->scl_data.lb_params.alpha_en;
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tree_cfg->num_pipes = tree_pos + 1;
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dcn10_set_mpc_tree(mpc, tree_cfg);
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color_space = pipe_ctx->stream->public.output_color_space;
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color_space_to_black_color(dc, color_space, &black_color);
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@ -1680,18 +1664,15 @@ static void program_all_pipe_in_tree(
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{
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unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
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if (pipe_ctx->surface->public.visible || pipe_ctx->top_pipe == NULL) {
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dcn10_power_on_fe(dc, pipe_ctx, context);
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if (pipe_ctx->top_pipe == NULL) {
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/* lock otg_master_update to process all pipes associated with
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* this OTG. this is done only one time.
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*/
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if (pipe_ctx->top_pipe == NULL) {
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/* watermark is for all pipes */
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pipe_ctx->mi->funcs->program_watermarks(
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pipe_ctx->mi, &context->bw.dcn.watermarks, ref_clk_mhz);
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lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst);
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}
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/* watermark is for all pipes */
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pipe_ctx->mi->funcs->program_watermarks(
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pipe_ctx->mi, &context->bw.dcn.watermarks, ref_clk_mhz);
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lock_otg_master_update(dc->ctx, pipe_ctx->tg->inst);
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pipe_ctx->tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
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pipe_ctx->tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
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@ -1702,12 +1683,11 @@ static void program_all_pipe_in_tree(
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pipe_ctx->tg->funcs->program_global_sync(
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pipe_ctx->tg);
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pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !is_pipe_tree_visible(pipe_ctx));
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}
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if (pipe_ctx->surface->public.visible) {
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dcn10_power_on_fe(dc, pipe_ctx, context);
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update_dchubp_dpp(dc, pipe_ctx, context);
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/* Only support one plane for now. */
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}
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if (pipe_ctx->bottom_pipe != NULL)
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@ -36,6 +36,9 @@
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#define FN(reg_name, field_name) \
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mpc->mpc_shift->field_name, mpc->mpc_mask->field_name
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#define MODE_TOP_ONLY 1
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#define MODE_BLEND 3
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/* Internal function to set mpc output mux */
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static void set_output_mux(struct dcn10_mpc *mpc,
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uint8_t opp_id,
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@ -45,32 +48,7 @@ static void set_output_mux(struct dcn10_mpc *mpc,
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REG_UPDATE(OPP_PIPE_CONTROL[opp_id],
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OPP_PIPE_CLOCK_EN, 1);
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REG_SET(MUX[opp_id], 0,
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MPC_OUT_MUX, mpcc_id);
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/* TODO: Move to post when ready.
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if (mpcc_id == 0xf) {
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MPCC_REG_UPDATE(OPP_PIPE0_OPP_PIPE_CONTROL,
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OPP_PIPE_CLOCK_EN, 0);
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}
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*/
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}
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static void set_blend_mode(struct dcn10_mpc *mpc,
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enum blend_mode mode,
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uint8_t mpcc_id)
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{
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/* Enable per-pixel alpha on this pipe */
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if (mode == TOP_BLND)
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REG_UPDATE_3(MPCC_CONTROL[mpcc_id],
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MPCC_ALPHA_BLND_MODE, 0,
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MPCC_ALPHA_MULTIPLIED_MODE, 0,
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MPCC_BLND_ACTIVE_OVERLAP_ONLY, 0);
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else
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REG_UPDATE_3(MPCC_CONTROL[mpcc_id],
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MPCC_ALPHA_BLND_MODE, 0,
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MPCC_ALPHA_MULTIPLIED_MODE, 1,
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MPCC_BLND_ACTIVE_OVERLAP_ONLY, 1);
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REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, mpcc_id);
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}
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void dcn10_set_mpc_background_color(struct dcn10_mpc *mpc,
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@ -121,44 +99,27 @@ void dcn10_set_mpc_tree(struct dcn10_mpc *mpc,
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REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
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MPCC_BOT_SEL, 0xF);
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/* MPCC_CONTROL->MPCC_MODE */
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REG_UPDATE(MPCC_CONTROL[mpcc_inst],
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MPCC_MODE, tree_cfg->mode);
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MPCC_MODE, MODE_TOP_ONLY);
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} else {
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REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
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MPCC_BOT_SEL, tree_cfg->dpp[i+1]);
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/* MPCC_CONTROL->MPCC_MODE */
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REG_UPDATE(MPCC_CONTROL[mpcc_inst],
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MPCC_MODE, 3);
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MPCC_MODE, MODE_BLEND);
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}
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if (i == 0)
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set_output_mux(
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mpc, tree_cfg->opp_id, mpcc_inst);
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set_blend_mode(mpc, tree_cfg->mode, mpcc_inst);
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REG_UPDATE_2(MPCC_CONTROL[mpcc_inst],
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MPCC_ALPHA_BLND_MODE,
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tree_cfg->per_pixel_alpha[i] ? 0 : 2,
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MPCC_ALPHA_MULTIPLIED_MODE, 0);
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}
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}
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void dcn10_set_mpc_passthrough(struct dcn10_mpc *mpc,
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uint8_t dpp_idx,
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uint8_t mpcc_idx,
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uint8_t opp_idx)
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{
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struct mpc_tree_cfg tree_cfg = { 0 };
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tree_cfg.num_pipes = 1;
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tree_cfg.opp_id = opp_idx;
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tree_cfg.mode = TOP_PASSTHRU;
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/* TODO: FPGA bring up one MPC has only 1 DPP and 1 MPCC
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* For blend case, need fill mode DPP and cascade MPCC
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*/
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tree_cfg.dpp[0] = dpp_idx;
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tree_cfg.mpcc[0] = mpcc_idx;
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dcn10_set_mpc_tree(mpc, &tree_cfg);
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}
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/*
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* This is the function to remove current MPC tree specified by tree_cfg
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* Before invoke this function, ensure that master lock of OPTC specified
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@ -188,6 +149,7 @@ void dcn10_delete_mpc_tree(struct dcn10_mpc *mpc,
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*/
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tree_cfg->dpp[i] = 0xf;
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tree_cfg->mpcc[i] = 0xf;
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tree_cfg->per_pixel_alpha[i] = false;
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}
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set_output_mux(mpc, tree_cfg->opp_id, 0xf);
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tree_cfg->opp_id = 0xf;
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@ -208,6 +170,7 @@ bool dcn10_remove_dpp(struct dcn10_mpc *mpc,
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uint8_t idx)
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{
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int i;
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uint8_t mpcc_inst;
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bool found = false;
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/* find dpp_idx from dpp array of tree_cfg */
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@ -218,54 +181,53 @@ bool dcn10_remove_dpp(struct dcn10_mpc *mpc,
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}
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}
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if (found) {
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/* add remove dpp/mpcc pair into pending list */
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if (!found) {
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BREAK_TO_DEBUGGER();
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return false;
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}
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mpcc_inst = tree_cfg->mpcc[i];
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/* TODO FPGA AddToPendingList if empty from pseudo code
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* AddToPendingList(tree_cfg->dpp[i],tree_cfg->mpcc[i]);
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*/
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uint8_t mpcc_inst = tree_cfg->mpcc[i];
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REG_SET(MPCC_OPP_ID[mpcc_inst], 0,
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MPCC_OPP_ID, 0xf);
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REG_SET(MPCC_OPP_ID[mpcc_inst], 0,
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MPCC_OPP_ID, 0xf);
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REG_SET(MPCC_TOP_SEL[mpcc_inst], 0,
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MPCC_TOP_SEL, 0xf);
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REG_SET(MPCC_TOP_SEL[mpcc_inst], 0,
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MPCC_TOP_SEL, 0xf);
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REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
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MPCC_BOT_SEL, 0xf);
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if (i == 0) {
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if (tree_cfg->num_pipes > 1)
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set_output_mux(mpc,
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tree_cfg->opp_id, tree_cfg->mpcc[i+1]);
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else
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set_output_mux(mpc, tree_cfg->opp_id, 0xf);
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} else if (i == tree_cfg->num_pipes-1) {
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mpcc_inst = tree_cfg->mpcc[i - 1];
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REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
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MPCC_BOT_SEL, 0xF);
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if (i == 0) {
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if (tree_cfg->num_pipes > 1)
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set_output_mux(mpc,
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tree_cfg->opp_id, tree_cfg->mpcc[i+1]);
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else
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set_output_mux(mpc, tree_cfg->opp_id, 0xf);
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} else if (i == tree_cfg->num_pipes-1) {
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mpcc_inst = tree_cfg->mpcc[i - 1];
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/* prev mpc is now last, set to top only*/
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REG_UPDATE(MPCC_CONTROL[mpcc_inst],
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MPCC_MODE, MODE_TOP_ONLY);
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} else {
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mpcc_inst = tree_cfg->mpcc[i - 1];
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REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
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MPCC_BOT_SEL, 0xF);
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REG_UPDATE(MPCC_CONTROL[mpcc_inst],
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MPCC_MODE, tree_cfg->mode);
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} else {
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mpcc_inst = tree_cfg->mpcc[i - 1];
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REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
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MPCC_BOT_SEL, tree_cfg->mpcc[i+1]);
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}
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set_blend_mode(mpc, tree_cfg->mode, mpcc_inst);
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/* update tree_cfg structure */
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while (i < tree_cfg->num_pipes - 1) {
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tree_cfg->dpp[i] = tree_cfg->dpp[i+1];
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tree_cfg->mpcc[i] = tree_cfg->mpcc[i+1];
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i++;
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}
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tree_cfg->num_pipes--;
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REG_SET(MPCC_BOT_SEL[mpcc_inst], 0,
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MPCC_BOT_SEL, tree_cfg->mpcc[i+1]);
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}
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return found;
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/* update tree_cfg structure */
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while (i < tree_cfg->num_pipes - 1) {
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tree_cfg->dpp[i] = tree_cfg->dpp[i+1];
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tree_cfg->mpcc[i] = tree_cfg->mpcc[i+1];
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tree_cfg->per_pixel_alpha[i] = tree_cfg->per_pixel_alpha[i+1];
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i++;
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}
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tree_cfg->num_pipes--;
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return true;
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}
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/* TODO FPGA: how to handle DPP?
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@ -284,14 +246,14 @@ void dcn10_add_dpp(struct dcn10_mpc *mpc,
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struct mpc_tree_cfg *tree_cfg,
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uint8_t dpp_idx,
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uint8_t mpcc_idx,
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uint8_t per_pixel_alpha,
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uint8_t position)
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{
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uint8_t temp;
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uint8_t temp1;
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uint8_t prev;
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uint8_t next;
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REG_SET(MPCC_OPP_ID[mpcc_idx], 0,
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MPCC_OPP_ID, tree_cfg->opp_id);
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REG_SET(MPCC_TOP_SEL[mpcc_idx], 0,
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MPCC_TOP_SEL, dpp_idx);
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@ -299,70 +261,71 @@ void dcn10_add_dpp(struct dcn10_mpc *mpc,
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/* idle dpp/mpcc is added to the top layer of tree */
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REG_SET(MPCC_BOT_SEL[mpcc_idx], 0,
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MPCC_BOT_SEL, tree_cfg->mpcc[0]);
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REG_UPDATE(MPCC_CONTROL[mpcc_idx],
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MPCC_MODE, 3);
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/* bottom mpc is always top only */
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REG_UPDATE(MPCC_CONTROL[mpcc_idx],
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MPCC_MODE, MODE_TOP_ONLY);
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/* opp will get new output. from new added mpcc */
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set_output_mux(mpc, tree_cfg->opp_id, mpcc_idx);
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set_blend_mode(mpc, tree_cfg->mode, mpcc_idx);
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} else if (position == tree_cfg->num_pipes) {
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/* idle dpp/mpcc is added to the bottom layer of tree */
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/* get instance of previous bottom mpcc, set to middle layer */
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temp = tree_cfg->mpcc[tree_cfg->num_pipes - 1];
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prev = tree_cfg->mpcc[position - 1];
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REG_SET(MPCC_BOT_SEL[temp], 0,
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REG_SET(MPCC_BOT_SEL[prev], 0,
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MPCC_BOT_SEL, mpcc_idx);
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REG_UPDATE(MPCC_CONTROL[temp],
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MPCC_MODE, 3);
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/* all mpcs other than bottom need to blend */
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REG_UPDATE(MPCC_CONTROL[prev],
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MPCC_MODE, MODE_BLEND);
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/* mpcc_idx become new bottom mpcc*/
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REG_SET(MPCC_BOT_SEL[mpcc_idx], 0,
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MPCC_BOT_SEL, 0xf);
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/* bottom mpc is always top only */
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REG_UPDATE(MPCC_CONTROL[mpcc_idx],
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MPCC_MODE, tree_cfg->mode);
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set_blend_mode(mpc, tree_cfg->mode, mpcc_idx);
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MPCC_MODE, MODE_TOP_ONLY);
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} else {
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/* idle dpp/mpcc is added to middle of tree */
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temp = tree_cfg->mpcc[position - 1];
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temp1 = tree_cfg->mpcc[position];
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prev = tree_cfg->mpcc[position - 1]; /* mpc a */
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next = tree_cfg->mpcc[position]; /* mpc b */
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/* new mpcc instance temp1 is added right after temp*/
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REG_SET(MPCC_BOT_SEL[temp], 0,
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/* connect mpc inserted below mpc a*/
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REG_SET(MPCC_BOT_SEL[prev], 0,
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MPCC_BOT_SEL, mpcc_idx);
|
||||
|
||||
/* mpcc_idx connect previous temp+1 to new mpcc */
|
||||
/* blend on mpc being inserted */
|
||||
REG_UPDATE(MPCC_CONTROL[mpcc_idx],
|
||||
MPCC_MODE, MODE_BLEND);
|
||||
|
||||
/* Connect mpc b below one inserted */
|
||||
REG_SET(MPCC_BOT_SEL[mpcc_idx], 0,
|
||||
MPCC_BOT_SEL, temp1);
|
||||
MPCC_BOT_SEL, next);
|
||||
|
||||
/* temp TODO: may not need*/
|
||||
REG_UPDATE(MPCC_CONTROL[temp],
|
||||
MPCC_MODE, 3);
|
||||
|
||||
set_blend_mode(mpc, tree_cfg->mode, temp);
|
||||
}
|
||||
|
||||
/* update tree_cfg structure */
|
||||
temp = tree_cfg->num_pipes - 1;
|
||||
/* premultiplied mode only if alpha is on for the layer*/
|
||||
REG_UPDATE_2(MPCC_CONTROL[mpcc_idx],
|
||||
MPCC_ALPHA_BLND_MODE,
|
||||
tree_cfg->per_pixel_alpha[position] ? 0 : 2,
|
||||
MPCC_ALPHA_MULTIPLIED_MODE, 0);
|
||||
|
||||
/*
|
||||
* iterating from the last mpc/dpp pair to the one being added, shift
|
||||
* them down one position
|
||||
*/
|
||||
while (temp > position) {
|
||||
tree_cfg->dpp[temp + 1] = tree_cfg->dpp[temp];
|
||||
tree_cfg->mpcc[temp + 1] = tree_cfg->mpcc[temp];
|
||||
temp--;
|
||||
for (next = tree_cfg->num_pipes; next > position; next--) {
|
||||
tree_cfg->dpp[next] = tree_cfg->dpp[next - 1];
|
||||
tree_cfg->mpcc[next] = tree_cfg->mpcc[next - 1];
|
||||
tree_cfg->per_pixel_alpha[next] = tree_cfg->per_pixel_alpha[next - 1];
|
||||
}
|
||||
|
||||
/* insert the new mpc/dpp pair into the tree_cfg*/
|
||||
tree_cfg->dpp[position] = dpp_idx;
|
||||
tree_cfg->mpcc[position] = mpcc_idx;
|
||||
tree_cfg->per_pixel_alpha[position] = per_pixel_alpha;
|
||||
tree_cfg->num_pipes++;
|
||||
}
|
||||
|
||||
|
||||
@ -105,11 +105,6 @@ struct dcn10_mpc {
|
||||
const struct dcn_mpc_mask *mpc_mask;
|
||||
};
|
||||
|
||||
void dcn10_set_mpc_passthrough(struct dcn10_mpc *mpc,
|
||||
uint8_t dpp_idx,
|
||||
uint8_t mpcc_idx,
|
||||
uint8_t opp_idx);
|
||||
|
||||
void dcn10_delete_mpc_tree(struct dcn10_mpc *mpc,
|
||||
struct mpc_tree_cfg *tree_cfg);
|
||||
|
||||
@ -121,6 +116,7 @@ void dcn10_add_dpp(struct dcn10_mpc *mpc,
|
||||
struct mpc_tree_cfg *tree_cfg,
|
||||
uint8_t dpp_idx,
|
||||
uint8_t mpcc_idx,
|
||||
uint8_t per_pixel_alpha,
|
||||
uint8_t position);
|
||||
|
||||
void wait_mpcc_idle(struct dcn10_mpc *mpc,
|
||||
|
||||
@ -25,19 +25,6 @@
|
||||
#ifndef __DC_MPC_H__
|
||||
#define __DC_MPC_H__
|
||||
|
||||
/* define the maximum number of pipes
|
||||
* MAX_NUM_PIPPES = MAX_PIPES defined in core_type.h
|
||||
*/
|
||||
enum {
|
||||
MAX_NUM_PIPPES = 6
|
||||
};
|
||||
|
||||
enum blend_mode {
|
||||
DIGI_BYPASS = 0, /* digital bypass */
|
||||
TOP_PASSTHRU, /* top layer pass through */
|
||||
TOP_BLND /* top layer blend */
|
||||
};
|
||||
|
||||
/* This structure define the mpc tree configuration
|
||||
* num_pipes - number of pipes of the tree
|
||||
* opp_id - instance id of OPP to drive MPC
|
||||
@ -60,10 +47,10 @@ struct mpc_tree_cfg {
|
||||
uint8_t num_pipes;
|
||||
uint8_t opp_id;
|
||||
/* dpp pipes for blend */
|
||||
uint8_t dpp[MAX_NUM_PIPPES];
|
||||
uint8_t dpp[6];
|
||||
/* mpcc insatnces for blend */
|
||||
uint8_t mpcc[MAX_NUM_PIPPES];
|
||||
enum blend_mode mode;
|
||||
uint8_t mpcc[6];
|
||||
bool per_pixel_alpha[6];
|
||||
};
|
||||
|
||||
struct mpcc_blnd_cfg {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user