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ARM: SoC fixes for 3.17-rc

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Here's the weekly batch of fixes from arm-soc.
 
 The delta is a largeish negative delta, due to revert of SMP support for Broadcom's
 STB SoC -- it was accidentally merged before some issues had been addressed, so they
 will make a new attempt for 3.18. I didn't see a need for a full revert of the whole
 platform due to this, we're keeping the rest enabled.
 
 The rest is mostly:
 
 * A handful of DT fixes for i.MX (Hummingboard/Cubox-i in particular)
 * Some MTD/NAND fixes for OMAP
 * Minor DT fixes for shmobile
 * Warning fix for UP builds on vexpress/spc
 
 There's also a couple of patches that wires up hwmod on TI's DRA7 SoC
 so it can boot. Drivers and the rest had landed for 3.17, and it's small
 and isolated so it made sense to pick up now even if it's not a bugfix.
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "Here's the weekly batch of fixes from arm-soc.

  The delta is a largeish negative delta, due to revert of SMP support
  for Broadcom's STB SoC -- it was accidentally merged before some
  issues had been addressed, so they will make a new attempt for 3.18.
  I didn't see a need for a full revert of the whole platform due to
  this, we're keeping the rest enabled.

  The rest is mostly:

   - a handful of DT fixes for i.MX (Hummingboard/Cubox-i in particular)
   - some MTD/NAND fixes for OMAP
   - minor DT fixes for shmobile
   - warning fix for UP builds on vexpress/spc

  There's also a couple of patches that wires up hwmod on TI's DRA7 SoC
  so it can boot.  Drivers and the rest had landed for 3.17, and it's
  small and isolated so it made sense to pick up now even if it's not a
  bugfix"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (23 commits)
  vexpress/spc: fix a build warning on array bounds
  ARM: DRA7: hwmod: Add dra74x and dra72x specific ocp interface lists
  ARM: DRA7: Add support for soc_is_dra74x() and soc_is_dra72x() variants
  MAINTAINERS: catch special Rockchip code locations
  ARM: dts: microsom-ar8035: MDIO pad must be set open drain
  ARM: dts: omap54xx-clocks: Fix the l3 and l4 clock rates
  ARM: brcmstb: revert SMP support
  ARM: OMAP2+: hwmod: Rearm wake-up interrupts for DT when MUSB is idled
  ARM: dts: Enable UART wake-up events for beagleboard
  ARM: dts: Remove twl6030 clk32g "regulator"
  ARM: OMAP2+: omap_device: remove warning that clk alias already exists
  ARM: OMAP: fix %d confusingly prefixed with 0x in format string
  ARM: dts: DRA7: fix interrupt-cells for GPIO
  mtd: nand: omap: Fix 1-bit Hamming code scheme, omap_calculate_ecc()
  ARM: dts: omap3430-sdp: Revert to using software ECC for NAND
  ARM: OMAP2+: GPMC: Support Software ECC scheme via DT
  mtd: nand: omap: Revert to using software ECC by default
  ARM: dts: hummingboard/cubox-i: change SPDIF output to be more descriptive
  ARM: dts: hummingboard/cubox-i: add USB OC pinctrl configuration
  ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR
  ...
This commit is contained in:
Linus Torvalds 2014-08-31 17:01:19 -07:00
commit 19ed3eb975
29 changed files with 133 additions and 464 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/mtd/gpmc-nand.txt
View File

@ -22,7 +22,7 @@ Optional properties:
width of 8 is assumed.
- ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
"sw" <deprecated> use "ham1" instead
"sw" 1-bit Hamming ecc code via software
"hw" <deprecated> use "ham1" instead
"hw-romcode" <deprecated> use "ham1" instead
"ham1" 1-bit Hamming ecc code

5
MAINTAINERS
View File

@ -1279,8 +1279,13 @@ M: Heiko Stuebner <heiko@sntech.de>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-rockchip@lists.infradead.org
S: Maintained
F: arch/arm/boot/dts/rk3*
F: arch/arm/mach-rockchip/
F: drivers/clk/rockchip/
F: drivers/i2c/busses/i2c-rk3x.c
F: drivers/*/*rockchip*
F: drivers/*/*/*rockchip*
F: sound/soc/rockchip/
ARM/SAMSUNG ARM ARCHITECTURES
M: Ben Dooks <ben-linux@fluff.org>

16
arch/arm/boot/dts/dra7.dtsi
View File

@ -245,7 +245,7 @@ gpio1: gpio@4ae10000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio2: gpio@48055000 {
@ -256,7 +256,7 @@ gpio2: gpio@48055000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio3: gpio@48057000 {
@ -267,7 +267,7 @@ gpio3: gpio@48057000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio4: gpio@48059000 {
@ -278,7 +278,7 @@ gpio4: gpio@48059000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio5: gpio@4805b000 {
@ -289,7 +289,7 @@ gpio5: gpio@4805b000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio6: gpio@4805d000 {
@ -300,7 +300,7 @@ gpio6: gpio@4805d000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio7: gpio@48051000 {
@ -311,7 +311,7 @@ gpio7: gpio@48051000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
gpio8: gpio@48053000 {
@ -322,7 +322,7 @@ gpio8: gpio@48053000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <1>;
#interrupt-cells = <2>;
};
uart1: serial@4806a000 {

8
arch/arm/boot/dts/imx53-qsrb.dts
View File

@ -28,6 +28,12 @@ MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX53_PAD_CSI0_DAT5__GPIO5_23 0x1e4 /* IRQ */
>;
};
};
};
@ -38,6 +44,8 @@ &i2c1 {
pmic: mc34708@8 {
compatible = "fsl,mc34708";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x08>;
interrupt-parent = <&gpio5>;
interrupts = <23 0x8>;

4
arch/arm/boot/dts/imx6dl-hummingboard.dts
View File

@ -58,7 +58,7 @@ reg_usbotg_vbus: usb-otg-vbus {
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
model = "On-board SPDIF";
/* IMX6 doesn't implement this yet */
spdif-controller = <&spdif>;
spdif-out;
@ -181,11 +181,13 @@ &spdif {
};
&usbh1 {
disable-over-current;
vbus-supply = <&reg_usbh1_vbus>;
status = "okay";
};
&usbotg {
disable-over-current;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>;
vbus-supply = <&reg_usbotg_vbus>;

19
arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
View File

@ -61,7 +61,7 @@ reg_usbotg_vbus: usb-otg-vbus {
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
model = "Integrated SPDIF";
/* IMX6 doesn't implement this yet */
spdif-controller = <&spdif>;
spdif-out;
@ -130,16 +130,23 @@ pinctrl_cubox_i_spdif: cubox-i-spdif {
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
};
pinctrl_cubox_i_usbh1: cubox-i-usbh1 {
fsl,pins = <MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0>;
};
pinctrl_cubox_i_usbh1_vbus: cubox-i-usbh1-vbus {
fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x4001b0b0>;
};
pinctrl_cubox_i_usbotg_id: cubox-i-usbotg-id {
pinctrl_cubox_i_usbotg: cubox-i-usbotg {
/*
* The Cubox-i pulls this low, but as it's pointless
* The Cubox-i pulls ID low, but as it's pointless
* leaving it as a pull-up, even if it is just 10uA.
*/
fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
>;
};
pinctrl_cubox_i_usbotg_vbus: cubox-i-usbotg-vbus {
@ -173,13 +180,15 @@ &spdif {
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cubox_i_usbh1>;
vbus-supply = <&reg_usbh1_vbus>;
status = "okay";
};
&usbotg {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cubox_i_usbotg_id>;
pinctrl-0 = <&pinctrl_cubox_i_usbotg>;
vbus-supply = <&reg_usbotg_vbus>;
status = "okay";
};

2
arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
View File

@ -17,7 +17,7 @@ &iomuxc {
enet {
pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
/* AR8035 reset */
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0

1
arch/arm/boot/dts/omap3-beagle.dts
View File

@ -292,6 +292,7 @@ &twl_gpio {
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
};
&gpio1 {

2
arch/arm/boot/dts/omap3430-sdp.dts
View File

@ -107,7 +107,7 @@ nand@1,0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <1 0 0x08000000>;
ti,nand-ecc-opt = "ham1";
ti,nand-ecc-opt = "sw";
nand-bus-width = <8>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <36>;

16
arch/arm/boot/dts/omap54xx-clocks.dtsi
View File

@ -367,10 +367,12 @@ usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
l3_iclk_div: l3_iclk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
compatible = "ti,divider-clock";
ti,max-div = <2>;
ti,bit-shift = <4>;
reg = <0x100>;
clocks = <&dpll_core_h12x2_ck>;
clock-mult = <1>;
clock-div = <1>;
ti,index-power-of-two;
};
gpu_l3_iclk: gpu_l3_iclk {
@ -383,10 +385,12 @@ gpu_l3_iclk: gpu_l3_iclk {
l4_root_clk_div: l4_root_clk_div {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
compatible = "ti,divider-clock";
ti,max-div = <2>;
ti,bit-shift = <8>;
reg = <0x100>;
clocks = <&l3_iclk_div>;
clock-mult = <1>;
clock-div = <1>;
ti,index-power-of-two;
};
slimbus1_slimbus_clk: slimbus1_slimbus_clk {

4
arch/arm/boot/dts/twl6030.dtsi
View File

@ -83,10 +83,6 @@ v2v1: regulator-v2v1 {
regulator-always-on;
};
clk32kg: regulator-clk32kg {
compatible = "ti,twl6030-clk32kg";
};
twl_usb_comparator: usb-comparator {
compatible = "ti,twl6030-usb";
interrupts = <4>, <10>;

1
arch/arm/mach-bcm/Makefile
View File

@ -36,5 +36,4 @@ obj-$(CONFIG_ARCH_BCM_5301X) += bcm_5301x.o
ifeq ($(CONFIG_ARCH_BRCMSTB),y)
obj-y += brcmstb.o
obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o
endif

19
arch/arm/mach-bcm/brcmstb.h
View File

@ -1,19 +0,0 @@
/*
* Copyright (C) 2013-2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __BRCMSTB_H__
#define __BRCMSTB_H__
void brcmstb_secondary_startup(void);
#endif /* __BRCMSTB_H__ */

33
arch/arm/mach-bcm/headsmp-brcmstb.S
View File

@ -1,33 +0,0 @@
/*
* SMP boot code for secondary CPUs
* Based on arch/arm/mach-tegra/headsmp.S
*
* Copyright (C) 2010 NVIDIA, Inc.
* Copyright (C) 2013-2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <asm/assembler.h>
#include <linux/linkage.h>
#include <linux/init.h>
.section ".text.head", "ax"
ENTRY(brcmstb_secondary_startup)
/*
* Ensure CPU is in a sane state by disabling all IRQs and switching
* into SVC mode.
*/
setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
bl v7_invalidate_l1
b secondary_startup
ENDPROC(brcmstb_secondary_startup)

363
arch/arm/mach-bcm/platsmp-brcmstb.c
View File

@ -1,363 +0,0 @@
/*
* Broadcom STB CPU SMP and hotplug support for ARM
*
* Copyright (C) 2013-2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/printk.h>
#include <linux/regmap.h>
#include <linux/smp.h>
#include <linux/mfd/syscon.h>
#include <linux/spinlock.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/mach-types.h>
#include <asm/smp_plat.h>
#include "brcmstb.h"
enum {
ZONE_MAN_CLKEN_MASK = BIT(0),
ZONE_MAN_RESET_CNTL_MASK = BIT(1),
ZONE_MAN_MEM_PWR_MASK = BIT(4),
ZONE_RESERVED_1_MASK = BIT(5),
ZONE_MAN_ISO_CNTL_MASK = BIT(6),
ZONE_MANUAL_CONTROL_MASK = BIT(7),
ZONE_PWR_DN_REQ_MASK = BIT(9),
ZONE_PWR_UP_REQ_MASK = BIT(10),
ZONE_BLK_RST_ASSERT_MASK = BIT(12),
ZONE_PWR_OFF_STATE_MASK = BIT(25),
ZONE_PWR_ON_STATE_MASK = BIT(26),
ZONE_DPG_PWR_STATE_MASK = BIT(28),
ZONE_MEM_PWR_STATE_MASK = BIT(29),
ZONE_RESET_STATE_MASK = BIT(31),
CPU0_PWR_ZONE_CTRL_REG = 1,
CPU_RESET_CONFIG_REG = 2,
};
static void __iomem *cpubiuctrl_block;
static void __iomem *hif_cont_block;
static u32 cpu0_pwr_zone_ctrl_reg;
static u32 cpu_rst_cfg_reg;
static u32 hif_cont_reg;
#ifdef CONFIG_HOTPLUG_CPU
static DEFINE_PER_CPU_ALIGNED(int, per_cpu_sw_state);
static int per_cpu_sw_state_rd(u32 cpu)
{
sync_cache_r(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
return per_cpu(per_cpu_sw_state, cpu);
}
static void per_cpu_sw_state_wr(u32 cpu, int val)
{
per_cpu(per_cpu_sw_state, cpu) = val;
dmb();
sync_cache_w(SHIFT_PERCPU_PTR(&per_cpu_sw_state, per_cpu_offset(cpu)));
dsb_sev();
}
#else
static inline void per_cpu_sw_state_wr(u32 cpu, int val) { }
#endif
static void __iomem *pwr_ctrl_get_base(u32 cpu)
{
void __iomem *base = cpubiuctrl_block + cpu0_pwr_zone_ctrl_reg;
base += (cpu_logical_map(cpu) * 4);
return base;
}
static u32 pwr_ctrl_rd(u32 cpu)
{
void __iomem *base = pwr_ctrl_get_base(cpu);
return readl_relaxed(base);
}
static void pwr_ctrl_wr(u32 cpu, u32 val)
{
void __iomem *base = pwr_ctrl_get_base(cpu);
writel(val, base);
}
static void cpu_rst_cfg_set(u32 cpu, int set)
{
u32 val;
val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg);
if (set)
val |= BIT(cpu_logical_map(cpu));
else
val &= ~BIT(cpu_logical_map(cpu));
writel_relaxed(val, cpubiuctrl_block + cpu_rst_cfg_reg);
}
static void cpu_set_boot_addr(u32 cpu, unsigned long boot_addr)
{
const int reg_ofs = cpu_logical_map(cpu) * 8;
writel_relaxed(0, hif_cont_block + hif_cont_reg + reg_ofs);
writel_relaxed(boot_addr, hif_cont_block + hif_cont_reg + 4 + reg_ofs);
}
static void brcmstb_cpu_boot(u32 cpu)
{
pr_info("SMP: Booting CPU%d...\n", cpu);
/*
* set the reset vector to point to the secondary_startup
* routine
*/
cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));
/* unhalt the cpu */
cpu_rst_cfg_set(cpu, 0);
}
static void brcmstb_cpu_power_on(u32 cpu)
{
/*
* The secondary cores power was cut, so we must go through
* power-on initialization.
*/
u32 tmp;
pr_info("SMP: Powering up CPU%d...\n", cpu);
/* Request zone power up */
pwr_ctrl_wr(cpu, ZONE_PWR_UP_REQ_MASK);
/* Wait for the power up FSM to complete */
do {
tmp = pwr_ctrl_rd(cpu);
} while (!(tmp & ZONE_PWR_ON_STATE_MASK));
per_cpu_sw_state_wr(cpu, 1);
}
static int brcmstb_cpu_get_power_state(u32 cpu)
{
int tmp = pwr_ctrl_rd(cpu);
return (tmp & ZONE_RESET_STATE_MASK) ? 0 : 1;
}
#ifdef CONFIG_HOTPLUG_CPU
static void brcmstb_cpu_die(u32 cpu)
{
v7_exit_coherency_flush(all);
/* Prevent all interrupts from reaching this CPU. */
arch_local_irq_disable();
/*
* Final full barrier to ensure everything before this instruction has
* quiesced.
*/
isb();
dsb();
per_cpu_sw_state_wr(cpu, 0);
/* Sit and wait to die */
wfi();
/* We should never get here... */
panic("Spurious interrupt on CPU %d received!\n", cpu);
}
static int brcmstb_cpu_kill(u32 cpu)
{
u32 tmp;
pr_info("SMP: Powering down CPU%d...\n", cpu);
while (per_cpu_sw_state_rd(cpu))
;
/* Program zone reset */
pwr_ctrl_wr(cpu, ZONE_RESET_STATE_MASK | ZONE_BLK_RST_ASSERT_MASK |
ZONE_PWR_DN_REQ_MASK);
/* Verify zone reset */
tmp = pwr_ctrl_rd(cpu);
if (!(tmp & ZONE_RESET_STATE_MASK))
pr_err("%s: Zone reset bit for CPU %d not asserted!\n",
__func__, cpu);
/* Wait for power down */
do {
tmp = pwr_ctrl_rd(cpu);
} while (!(tmp & ZONE_PWR_OFF_STATE_MASK));
/* Settle-time from Broadcom-internal DVT reference code */
udelay(7);
/* Assert reset on the CPU */
cpu_rst_cfg_set(cpu, 1);
return 1;
}
#endif /* CONFIG_HOTPLUG_CPU */
static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
{
int rc = 0;
char *name;
struct device_node *syscon_np = NULL;
name = "syscon-cpu";
syscon_np = of_parse_phandle(np, name, 0);
if (!syscon_np) {
pr_err("can't find phandle %s\n", name);
rc = -EINVAL;
goto cleanup;
}
cpubiuctrl_block = of_iomap(syscon_np, 0);
if (!cpubiuctrl_block) {
pr_err("iomap failed for cpubiuctrl_block\n");
rc = -EINVAL;
goto cleanup;
}
rc = of_property_read_u32_index(np, name, CPU0_PWR_ZONE_CTRL_REG,
&cpu0_pwr_zone_ctrl_reg);
if (rc) {
pr_err("failed to read 1st entry from %s property (%d)\n", name,
rc);
rc = -EINVAL;
goto cleanup;
}
rc = of_property_read_u32_index(np, name, CPU_RESET_CONFIG_REG,
&cpu_rst_cfg_reg);
if (rc) {
pr_err("failed to read 2nd entry from %s property (%d)\n", name,
rc);
rc = -EINVAL;
goto cleanup;
}
cleanup:
if (syscon_np)
of_node_put(syscon_np);
return rc;
}
static int __init setup_hifcont_regs(struct device_node *np)
{
int rc = 0;
char *name;
struct device_node *syscon_np = NULL;
name = "syscon-cont";
syscon_np = of_parse_phandle(np, name, 0);
if (!syscon_np) {
pr_err("can't find phandle %s\n", name);
rc = -EINVAL;
goto cleanup;
}
hif_cont_block = of_iomap(syscon_np, 0);
if (!hif_cont_block) {
pr_err("iomap failed for hif_cont_block\n");
rc = -EINVAL;
goto cleanup;
}
/* offset is at top of hif_cont_block */
hif_cont_reg = 0;
cleanup:
if (syscon_np)
of_node_put(syscon_np);
return rc;
}
static void __init brcmstb_cpu_ctrl_setup(unsigned int max_cpus)
{
int rc;
struct device_node *np;
char *name;
name = "brcm,brcmstb-smpboot";
np = of_find_compatible_node(NULL, NULL, name);
if (!np) {
pr_err("can't find compatible node %s\n", name);
return;
}
rc = setup_hifcpubiuctrl_regs(np);
if (rc)
return;
rc = setup_hifcont_regs(np);
if (rc)
return;
}
static DEFINE_SPINLOCK(boot_lock);
static void brcmstb_secondary_init(unsigned int cpu)
{
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
static int brcmstb_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
/*
* set synchronisation state between this boot processor
* and the secondary one
*/
spin_lock(&boot_lock);
/* Bring up power to the core if necessary */
if (brcmstb_cpu_get_power_state(cpu) == 0)
brcmstb_cpu_power_on(cpu);
brcmstb_cpu_boot(cpu);
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
spin_unlock(&boot_lock);
return 0;
}
static struct smp_operations brcmstb_smp_ops __initdata = {
.smp_prepare_cpus = brcmstb_cpu_ctrl_setup,
.smp_secondary_init = brcmstb_secondary_init,
.smp_boot_secondary = brcmstb_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = brcmstb_cpu_kill,
.cpu_die = brcmstb_cpu_die,
#endif
};
CPU_METHOD_OF_DECLARE(brcmstb_smp, "brcm,brahma-b15", &brcmstb_smp_ops);

2
arch/arm/mach-omap2/board-flash.c
View File

@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
board_nand_data.nr_parts = nr_parts;
board_nand_data.devsize = nand_type;
board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW;
board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_SW;
gpmc_nand_init(&board_nand_data, gpmc_t);
}
#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */

3
arch/arm/mach-omap2/gpmc-nand.c
View File

@ -49,7 +49,8 @@ static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
return 0;
/* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */
if (ecc_opt == OMAP_ECC_HAM1_CODE_HW)
if (ecc_opt == OMAP_ECC_HAM1_CODE_HW ||
ecc_opt == OMAP_ECC_HAM1_CODE_SW)
return 1;
else
return 0;

7
arch/arm/mach-omap2/gpmc.c
View File

@ -1403,8 +1403,11 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
return -ENODEV;
}
if (!strcmp(s, "ham1") || !strcmp(s, "sw") ||
!strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
if (!strcmp(s, "sw"))
gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
else if (!strcmp(s, "ham1") ||
!strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
gpmc_nand_data->ecc_opt =
OMAP_ECC_HAM1_CODE_HW;
else if (!strcmp(s, "bch4"))

2
arch/arm/mach-omap2/id.c
View File

@ -663,7 +663,7 @@ void __init dra7xxx_check_revision(void)
default:
/* Unknown default to latest silicon rev as default*/
pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n",
pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
__func__, idcode, hawkeye, rev);
omap_revision = DRA752_REV_ES1_1;
}

2
arch/arm/mach-omap2/omap_device.c
View File

@ -56,7 +56,7 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
r = clk_get_sys(dev_name(&od->pdev->dev), clk_alias);
if (!IS_ERR(r)) {
dev_warn(&od->pdev->dev,
dev_dbg(&od->pdev->dev,
"alias %s already exists\n", clk_alias);
clk_put(r);
return;

7
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -2185,6 +2185,8 @@ static int _enable(struct omap_hwmod *oh)
oh->mux->pads_dynamic))) {
omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
_reconfigure_io_chain();
} else if (oh->flags & HWMOD_FORCE_MSTANDBY) {
_reconfigure_io_chain();
}
_add_initiator_dep(oh, mpu_oh);
@ -2291,6 +2293,8 @@ static int _idle(struct omap_hwmod *oh)
if (oh->mux && oh->mux->pads_dynamic) {
omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
_reconfigure_io_chain();
} else if (oh->flags & HWMOD_FORCE_MSTANDBY) {
_reconfigure_io_chain();
}
oh->_state = _HWMOD_STATE_IDLE;
@ -3345,6 +3349,9 @@ int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
if (!ois)
return 0;
if (ois[0] == NULL) /* Empty list */
return 0;
if (!linkspace) {
if (_alloc_linkspace(ois)) {
pr_err("omap_hwmod: could not allocate link space\n");

22
arch/arm/mach-omap2/omap_hwmod_7xx_data.c
View File

@ -35,6 +35,7 @@
#include "i2c.h"
#include "mmc.h"
#include "wd_timer.h"
#include "soc.h"
/* Base offset for all DRA7XX interrupts external to MPUSS */
#define DRA7XX_IRQ_GIC_START 32
@ -3261,7 +3262,6 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per3__usb_otg_ss1,
&dra7xx_l4_per3__usb_otg_ss2,
&dra7xx_l4_per3__usb_otg_ss3,
&dra7xx_l4_per3__usb_otg_ss4,
&dra7xx_l3_main_1__vcp1,
&dra7xx_l4_per2__vcp1,
&dra7xx_l3_main_1__vcp2,
@ -3270,8 +3270,26 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
NULL,
};
static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_per3__usb_otg_ss4,
NULL,
};
static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
NULL,
};
int __init dra7xx_hwmod_init(void)
{
int ret;
omap_hwmod_init();
return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
if (!ret && soc_is_dra74x())
return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
else if (!ret && soc_is_dra72x())
return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
return ret;
}

6
arch/arm/mach-omap2/soc.h
View File

@ -245,6 +245,8 @@ IS_AM_SUBCLASS(437x, 0x437)
#define soc_is_omap54xx() 0
#define soc_is_omap543x() 0
#define soc_is_dra7xx() 0
#define soc_is_dra74x() 0
#define soc_is_dra72x() 0
#if defined(MULTI_OMAP2)
# if defined(CONFIG_ARCH_OMAP2)
@ -393,7 +395,11 @@ IS_OMAP_TYPE(3430, 0x3430)
#if defined(CONFIG_SOC_DRA7XX)
#undef soc_is_dra7xx
#undef soc_is_dra74x
#undef soc_is_dra72x
#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7"))
#define soc_is_dra74x() (of_machine_is_compatible("ti,dra74"))
#define soc_is_dra72x() (of_machine_is_compatible("ti,dra72"))
#endif
/* Various silicon revisions for omap2 */

4
arch/arm/mach-shmobile/clock-r8a7790.c
View File

@ -183,8 +183,8 @@ enum {
static struct clk div4_clks[DIV4_NR] = {
[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
};
/* DIV6 clocks */

2
arch/arm/mach-shmobile/clock-r8a7791.c
View File

@ -152,7 +152,7 @@ enum {
static struct clk div4_clks[DIV4_NR] = {
[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
};
/* DIV6 clocks */

2
arch/arm/mach-shmobile/clock-sh73a0.c
View File

@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
CLKDEV_DEV_ID("0xe6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
CLKDEV_DEV_ID("e6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */

14
arch/arm/mach-vexpress/spc.c
View File

@ -426,9 +426,15 @@ static int ve_spc_populate_opps(uint32_t cluster)
static int ve_init_opp_table(struct device *cpu_dev)
{
int cluster = topology_physical_package_id(cpu_dev->id);
int idx, ret = 0, max_opp = info->num_opps[cluster];
struct ve_spc_opp *opps = info->opps[cluster];
int cluster;
int idx, ret = 0, max_opp;
struct ve_spc_opp *opps;
cluster = topology_physical_package_id(cpu_dev->id);
cluster = cluster < 0 ? 0 : cluster;
max_opp = info->num_opps[cluster];
opps = info->opps[cluster];
for (idx = 0; idx < max_opp; idx++, opps++) {
ret = dev_pm_opp_add(cpu_dev, opps->freq * 1000, opps->u_volt);
@ -537,6 +543,8 @@ static struct clk *ve_spc_clk_register(struct device *cpu_dev)
spc->hw.init = &init;
spc->cluster = topology_physical_package_id(cpu_dev->id);
spc->cluster = spc->cluster < 0 ? 0 : spc->cluster;
init.name = dev_name(cpu_dev);
init.ops = &clk_spc_ops;
init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;

16
drivers/mtd/nand/omap2.c
View File

@ -931,7 +931,7 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u32 val;
val = readl(info->reg.gpmc_ecc_config);
if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs)
if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
return -EINVAL;
/* read ecc result */
@ -1794,9 +1794,12 @@ static int omap_nand_probe(struct platform_device *pdev)
}
/* populate MTD interface based on ECC scheme */
nand_chip->ecc.layout = &omap_oobinfo;
ecclayout = &omap_oobinfo;
switch (info->ecc_opt) {
case OMAP_ECC_HAM1_CODE_SW:
nand_chip->ecc.mode = NAND_ECC_SOFT;
break;
case OMAP_ECC_HAM1_CODE_HW:
pr_info("nand: using OMAP_ECC_HAM1_CODE_HW\n");
nand_chip->ecc.mode = NAND_ECC_HW;
@ -1848,7 +1851,7 @@ static int omap_nand_probe(struct platform_device *pdev)
nand_chip->ecc.priv = nand_bch_init(mtd,
nand_chip->ecc.size,
nand_chip->ecc.bytes,
&nand_chip->ecc.layout);
&ecclayout);
if (!nand_chip->ecc.priv) {
pr_err("nand: error: unable to use s/w BCH library\n");
err = -EINVAL;
@ -1923,7 +1926,7 @@ static int omap_nand_probe(struct platform_device *pdev)
nand_chip->ecc.priv = nand_bch_init(mtd,
nand_chip->ecc.size,
nand_chip->ecc.bytes,
&nand_chip->ecc.layout);
&ecclayout);
if (!nand_chip->ecc.priv) {
pr_err("nand: error: unable to use s/w BCH library\n");
err = -EINVAL;
@ -2012,6 +2015,9 @@ static int omap_nand_probe(struct platform_device *pdev)
goto return_error;
}
if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW)
goto scan_tail;
/* all OOB bytes from oobfree->offset till end off OOB are free */
ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
/* check if NAND device's OOB is enough to store ECC signatures */
@ -2021,7 +2027,9 @@ static int omap_nand_probe(struct platform_device *pdev)
err = -EINVAL;
goto return_error;
}
nand_chip->ecc.layout = ecclayout;
scan_tail:
/* second phase scan */
if (nand_scan_tail(mtd)) {
err = -ENXIO;

13
include/linux/platform_data/mtd-nand-omap2.h
View File

@ -21,8 +21,17 @@ enum nand_io {
};
enum omap_ecc {
/* 1-bit ECC calculation by GPMC, Error detection by Software */
OMAP_ECC_HAM1_CODE_HW = 0,
/*
* 1-bit ECC: calculation and correction by SW
* ECC stored at end of spare area
*/
OMAP_ECC_HAM1_CODE_SW = 0,
/*
* 1-bit ECC: calculation by GPMC, Error detection by Software
* ECC layout compatible with ROM code layout
*/
OMAP_ECC_HAM1_CODE_HW,
/* 4-bit ECC calculation by GPMC, Error detection by Software */
OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
/* 4-bit ECC calculation by GPMC, Error detection by ELM */