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drm/nouveau/gr/gf100: wait on bottom half of FE's pipeline

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When emitting the ICMD bundle, wait on the bottom half (bit 3 of the
GR_STATUS register) instead of upper half (bit 2) to make sure methods
are effectively emitted.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Alexandre Courbot 2015-04-29 23:04:23 +09:00 committed by Ben Skeggs
parent 1addc12648
commit 19bf09cecf
1 changed files with 1 additions and 1 deletions
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drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
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@ -699,7 +699,7 @@ gf100_gr_icmd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
while (addr < next) {
nv_wr32(priv, 0x400200, addr);
nv_wait(priv, 0x400700, 0x00000002, 0x00000000);
nv_wait(priv, 0x400700, 0x00000004, 0x00000000);
addr += init->pitch;
}
}