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drm/amd/powerplay: skip soc clk setting under pp one vf
Under sriov pp one vf mode, there is no need to set soc clk under pp one vf because smu firmware will depend on the mclk to set the appropriate soc clk for it. Signed-off-by: Yintian Tao <yttao@amd.com> Reviewed-by : Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3538,7 +3538,8 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
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if (!data->registry_data.mclk_dpm_key_disabled) {
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if (data->smc_state_table.mem_boot_level !=
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data->dpm_table.mem_table.dpm_state.soft_min_level) {
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if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) {
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if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1)
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&& hwmgr->not_vf) {
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socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetSoftMinSocclkByIndex,
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