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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ARM: sunxi: DT: Convert the DTs to use the GIC headers
The GIC requires some extra opaque arguments to set the IRQ type and flags. Convert the DTs to using the common defines. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Maxime Ripard
parent
092a0c3b18
commit
19882b84d7
@ -49,6 +49,8 @@
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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/ {
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@ -113,10 +115,10 @@ memory {
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pmu {
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compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
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interrupts = <0 120 4>,
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<0 121 4>,
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<0 122 4>,
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<0 123 4>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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};
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clocks {
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@ -363,7 +365,7 @@ soc@01c00000 {
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dma: dma-controller@01c02000 {
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compatible = "allwinner,sun6i-a31-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <0 50 4>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb1_gates 6>;
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resets = <&ahb1_rst 6>;
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#dma-cells = <1>;
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@ -380,7 +382,7 @@ mmc0: mmc@01c0f000 {
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clock-names = "ahb", "mmc";
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resets = <&ahb1_rst 8>;
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reset-names = "ahb";
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interrupts = <0 60 4>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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@ -391,7 +393,7 @@ mmc1: mmc@01c10000 {
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clock-names = "ahb", "mmc";
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resets = <&ahb1_rst 9>;
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reset-names = "ahb";
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interrupts = <0 61 4>;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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@ -402,7 +404,7 @@ mmc2: mmc@01c11000 {
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clock-names = "ahb", "mmc";
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resets = <&ahb1_rst 10>;
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reset-names = "ahb";
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interrupts = <0 62 4>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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@ -413,7 +415,7 @@ mmc3: mmc@01c12000 {
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clock-names = "ahb", "mmc";
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resets = <&ahb1_rst 11>;
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reset-names = "ahb";
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interrupts = <0 63 4>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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@ -444,7 +446,7 @@ usbphy: phy@01c19400 {
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ehci0: usb@01c1a000 {
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compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
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reg = <0x01c1a000 0x100>;
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interrupts = <0 72 4>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb1_gates 26>;
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resets = <&ahb1_rst 26>;
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phys = <&usbphy 1>;
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@ -455,7 +457,7 @@ ehci0: usb@01c1a000 {
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ohci0: usb@01c1a400 {
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compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
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reg = <0x01c1a400 0x100>;
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interrupts = <0 73 4>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb1_gates 29>, <&usb_clk 16>;
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resets = <&ahb1_rst 29>;
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phys = <&usbphy 1>;
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@ -466,7 +468,7 @@ ohci0: usb@01c1a400 {
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ehci1: usb@01c1b000 {
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compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
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reg = <0x01c1b000 0x100>;
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interrupts = <0 74 4>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb1_gates 27>;
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resets = <&ahb1_rst 27>;
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phys = <&usbphy 2>;
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@ -477,7 +479,7 @@ ehci1: usb@01c1b000 {
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ohci1: usb@01c1b400 {
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compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
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reg = <0x01c1b400 0x100>;
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interrupts = <0 75 4>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb1_gates 30>, <&usb_clk 17>;
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resets = <&ahb1_rst 30>;
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phys = <&usbphy 2>;
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@ -488,7 +490,7 @@ ohci1: usb@01c1b400 {
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ohci2: usb@01c1c400 {
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compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
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reg = <0x01c1c400 0x100>;
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interrupts = <0 77 4>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb1_gates 31>, <&usb_clk 18>;
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resets = <&ahb1_rst 31>;
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status = "disabled";
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@ -497,10 +499,10 @@ ohci2: usb@01c1c400 {
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun6i-a31-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <0 11 4>,
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<0 15 4>,
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<0 16 4>,
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<0 17 4>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb1_gates 5>;
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gpio-controller;
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interrupt-controller;
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@ -607,11 +609,11 @@ apb2_rst: reset@01c202d8 {
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timer@01c20c00 {
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compatible = "allwinner,sun4i-a10-timer";
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reg = <0x01c20c00 0xa0>;
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interrupts = <0 18 4>,
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<0 19 4>,
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<0 20 4>,
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<0 21 4>,
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<0 22 4>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc24M>;
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};
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@ -623,7 +625,7 @@ wdt1: watchdog@01c20ca0 {
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uart0: serial@01c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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interrupts = <0 0 4>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 16>;
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@ -636,7 +638,7 @@ uart0: serial@01c28000 {
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uart1: serial@01c28400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28400 0x400>;
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interrupts = <0 1 4>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 17>;
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@ -649,7 +651,7 @@ uart1: serial@01c28400 {
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uart2: serial@01c28800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28800 0x400>;
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interrupts = <0 2 4>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 18>;
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@ -662,7 +664,7 @@ uart2: serial@01c28800 {
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uart3: serial@01c28c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28c00 0x400>;
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interrupts = <0 3 4>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 19>;
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@ -675,7 +677,7 @@ uart3: serial@01c28c00 {
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uart4: serial@01c29000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29000 0x400>;
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interrupts = <0 4 4>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 20>;
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@ -688,7 +690,7 @@ uart4: serial@01c29000 {
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uart5: serial@01c29400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29400 0x400>;
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interrupts = <0 5 4>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb2_gates 21>;
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@ -701,7 +703,7 @@ uart5: serial@01c29400 {
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i2c0: i2c@01c2ac00 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2ac00 0x400>;
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interrupts = <0 6 4>;
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb2_gates 0>;
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resets = <&apb2_rst 0>;
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status = "disabled";
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@ -712,7 +714,7 @@ i2c0: i2c@01c2ac00 {
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i2c1: i2c@01c2b000 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b000 0x400>;
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interrupts = <0 7 4>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb2_gates 1>;
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resets = <&apb2_rst 1>;
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status = "disabled";
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@ -723,7 +725,7 @@ i2c1: i2c@01c2b000 {
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i2c2: i2c@01c2b400 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b400 0x400>;
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interrupts = <0 8 4>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb2_gates 2>;
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resets = <&apb2_rst 2>;
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status = "disabled";
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@ -734,7 +736,7 @@ i2c2: i2c@01c2b400 {
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i2c3: i2c@01c2b800 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x01c2b800 0x400>;
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interrupts = <0 9 4>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb2_gates 3>;
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resets = <&apb2_rst 3>;
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status = "disabled";
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@ -745,7 +747,7 @@ i2c3: i2c@01c2b800 {
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gmac: ethernet@01c30000 {
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compatible = "allwinner,sun7i-a20-gmac";
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reg = <0x01c30000 0x1054>;
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interrupts = <0 82 4>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
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clock-names = "stmmaceth", "allwinner_gmac_tx";
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@ -762,10 +764,10 @@ gmac: ethernet@01c30000 {
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timer@01c60000 {
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compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
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reg = <0x01c60000 0x1000>;
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interrupts = <0 51 4>,
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<0 52 4>,
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<0 53 4>,
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<0 54 4>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb1_gates 19>;
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resets = <&ahb1_rst 19>;
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};
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@ -773,7 +775,7 @@ timer@01c60000 {
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spi0: spi@01c68000 {
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compatible = "allwinner,sun6i-a31-spi";
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reg = <0x01c68000 0x1000>;
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interrupts = <0 65 4>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb1_gates 20>, <&spi0_clk>;
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clock-names = "ahb", "mod";
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dmas = <&dma 23>, <&dma 23>;
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@ -785,7 +787,7 @@ spi0: spi@01c68000 {
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spi1: spi@01c69000 {
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compatible = "allwinner,sun6i-a31-spi";
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reg = <0x01c69000 0x1000>;
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interrupts = <0 66 4>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb1_gates 21>, <&spi1_clk>;
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clock-names = "ahb", "mod";
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dmas = <&dma 24>, <&dma 24>;
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@ -797,7 +799,7 @@ spi1: spi@01c69000 {
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spi2: spi@01c6a000 {
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compatible = "allwinner,sun6i-a31-spi";
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reg = <0x01c6a000 0x1000>;
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interrupts = <0 67 4>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb1_gates 22>, <&spi2_clk>;
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clock-names = "ahb", "mod";
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dmas = <&dma 25>, <&dma 25>;
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@ -809,7 +811,7 @@ spi2: spi@01c6a000 {
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spi3: spi@01c6b000 {
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compatible = "allwinner,sun6i-a31-spi";
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reg = <0x01c6b000 0x1000>;
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interrupts = <0 68 4>;
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ahb1_gates 23>, <&spi3_clk>;
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clock-names = "ahb", "mod";
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dmas = <&dma 26>, <&dma 26>;
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@ -826,13 +828,14 @@ gic: interrupt-controller@01c81000 {
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<0x01c86000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <1 9 0xf04>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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rtc: rtc@01f00000 {
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compatible = "allwinner,sun6i-a31-rtc";
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reg = <0x01f00000 0x54>;
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interrupts = <0 40 4>, <0 41 4>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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};
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nmi_intc: interrupt-controller@01f00c0c {
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@ -840,7 +843,7 @@ nmi_intc: interrupt-controller@01f00c0c {
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x01f00c0c 0x38>;
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interrupts = <0 32 4>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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};
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prcm@01f01400 {
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@ -903,7 +906,7 @@ ir: ir@01f02000 {
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clocks = <&apb0_gates 1>, <&ir_clk>;
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clock-names = "apb", "ir";
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resets = <&apb0_rst 1>;
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interrupts = <0 37 4>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x01f02000 0x40>;
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status = "disabled";
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};
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@ -911,8 +914,8 @@ ir: ir@01f02000 {
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r_pio: pinctrl@01f02c00 {
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compatible = "allwinner,sun6i-a31-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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interrupts = <0 45 4>,
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<0 46 4>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&apb0_gates 0>;
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resets = <&apb0_rst 0>;
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gpio-controller;
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@ -49,6 +49,8 @@
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/dma/sun4i-a10.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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@ -104,16 +106,16 @@ memory {
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
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interrupts = <0 120 4>,
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<0 121 4>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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};
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clocks {
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@ -465,13 +467,13 @@ nmi_intc: interrupt-controller@01c00030 {
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interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x01c00030 0x0c>;
|
||||
interrupts = <0 0 4>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
dma: dma-controller@01c02000 {
|
||||
compatible = "allwinner,sun4i-a10-dma";
|
||||
reg = <0x01c02000 0x1000>;
|
||||
interrupts = <0 27 4>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ahb_gates 6>;
|
||||
#dma-cells = <2>;
|
||||
};
|
||||
@ -479,7 +481,7 @@ dma: dma-controller@01c02000 {
|
||||
spi0: spi@01c05000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c05000 0x1000>;
|
||||
interrupts = <0 10 4>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ahb_gates 20>, <&spi0_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma SUN4I_DMA_DEDICATED 27>,
|
||||
@ -493,7 +495,7 @@ spi0: spi@01c05000 {
|
||||
spi1: spi@01c06000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c06000 0x1000>;
|
||||
interrupts = <0 11 4>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ahb_gates 21>, <&spi1_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma SUN4I_DMA_DEDICATED 9>,
|
||||
@ -507,7 +509,7 @@ spi1: spi@01c06000 {
|
||||
emac: ethernet@01c0b000 {
|
||||
compatible = "allwinner,sun4i-a10-emac";
|
||||
reg = <0x01c0b000 0x1000>;
|
||||
interrupts = <0 55 4>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ahb_gates 17>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -525,7 +527,7 @@ mmc0: mmc@01c0f000 {
|
||||
reg = <0x01c0f000 0x1000>;
|
||||
clocks = <&ahb_gates 8>, <&mmc0_clk>;
|
||||
clock-names = "ahb", "mmc";
|
||||
interrupts = <0 32 4>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -534,7 +536,7 @@ mmc1: mmc@01c10000 {
|
||||
reg = <0x01c10000 0x1000>;
|
||||
clocks = <&ahb_gates 9>, <&mmc1_clk>;
|
||||
clock-names = "ahb", "mmc";
|
||||
interrupts = <0 33 4>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -543,7 +545,7 @@ mmc2: mmc@01c11000 {
|
||||
reg = <0x01c11000 0x1000>;
|
||||
clocks = <&ahb_gates 10>, <&mmc2_clk>;
|
||||
clock-names = "ahb", "mmc";
|
||||
interrupts = <0 34 4>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -552,7 +554,7 @@ mmc3: mmc@01c12000 {
|
||||
reg = <0x01c12000 0x1000>;
|
||||
clocks = <&ahb_gates 11>, <&mmc3_clk>;
|
||||
clock-names = "ahb", "mmc";
|
||||
interrupts = <0 35 4>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -571,7 +573,7 @@ usbphy: phy@01c13400 {
|
||||
ehci0: usb@01c14000 {
|
||||
compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
|
||||
reg = <0x01c14000 0x100>;
|
||||
interrupts = <0 39 4>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ahb_gates 1>;
|
||||
phys = <&usbphy 1>;
|
||||
phy-names = "usb";
|
||||
@ -581,7 +583,7 @@ ehci0: usb@01c14000 {
|
||||
ohci0: usb@01c14400 {
|
||||
compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
|
||||
reg = <0x01c14400 0x100>;
|
||||
interrupts = <0 64 4>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&usb_clk 6>, <&ahb_gates 2>;
|
||||
phys = <&usbphy 1>;
|
||||
phy-names = "usb";
|
||||
@ -591,7 +593,7 @@ ohci0: usb@01c14400 {
|
||||
spi2: spi@01c17000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c17000 0x1000>;
|
||||
interrupts = <0 12 4>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ahb_gates 22>, <&spi2_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma SUN4I_DMA_DEDICATED 29>,
|
||||
@ -605,7 +607,7 @@ spi2: spi@01c17000 {
|
||||
ahci: sata@01c18000 {
|
||||
compatible = "allwinner,sun4i-a10-ahci";
|
||||
reg = <0x01c18000 0x1000>;
|
||||
interrupts = <0 56 4>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pll6 0>, <&ahb_gates 25>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -613,7 +615,7 @@ ahci: sata@01c18000 {
|
||||
ehci1: usb@01c1c000 {
|
||||
compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
|
||||
reg = <0x01c1c000 0x100>;
|
||||
interrupts = <0 40 4>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ahb_gates 3>;
|
||||
phys = <&usbphy 2>;
|
||||
phy-names = "usb";
|
||||
@ -623,7 +625,7 @@ ehci1: usb@01c1c000 {
|
||||
ohci1: usb@01c1c400 {
|
||||
compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
|
||||
reg = <0x01c1c400 0x100>;
|
||||
interrupts = <0 65 4>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&usb_clk 7>, <&ahb_gates 4>;
|
||||
phys = <&usbphy 2>;
|
||||
phy-names = "usb";
|
||||
@ -633,7 +635,7 @@ ohci1: usb@01c1c400 {
|
||||
spi3: spi@01c1f000 {
|
||||
compatible = "allwinner,sun4i-a10-spi";
|
||||
reg = <0x01c1f000 0x1000>;
|
||||
interrupts = <0 50 4>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ahb_gates 23>, <&spi3_clk>;
|
||||
clock-names = "ahb", "mod";
|
||||
dmas = <&dma SUN4I_DMA_DEDICATED 31>,
|
||||
@ -647,7 +649,7 @@ spi3: spi@01c1f000 {
|
||||
pio: pinctrl@01c20800 {
|
||||
compatible = "allwinner,sun7i-a20-pinctrl";
|
||||
reg = <0x01c20800 0x400>;
|
||||
interrupts = <0 28 4>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb0_gates 5>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
@ -878,12 +880,12 @@ ir1_pins_a: ir1@0 {
|
||||
timer@01c20c00 {
|
||||
compatible = "allwinner,sun4i-a10-timer";
|
||||
reg = <0x01c20c00 0x90>;
|
||||
interrupts = <0 22 4>,
|
||||
<0 23 4>,
|
||||
<0 24 4>,
|
||||
<0 25 4>,
|
||||
<0 67 4>,
|
||||
<0 68 4>;
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
@ -895,7 +897,7 @@ wdt: watchdog@01c20c90 {
|
||||
rtc: rtc@01c20d00 {
|
||||
compatible = "allwinner,sun7i-a20-rtc";
|
||||
reg = <0x01c20d00 0x20>;
|
||||
interrupts = <0 24 4>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pwm: pwm@01c20e00 {
|
||||
@ -910,7 +912,7 @@ ir0: ir@01c21800 {
|
||||
compatible = "allwinner,sun4i-a10-ir";
|
||||
clocks = <&apb0_gates 6>, <&ir0_clk>;
|
||||
clock-names = "apb", "ir";
|
||||
interrupts = <0 5 4>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x01c21800 0x40>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -919,7 +921,7 @@ ir1: ir@01c21c00 {
|
||||
compatible = "allwinner,sun4i-a10-ir";
|
||||
clocks = <&apb0_gates 7>, <&ir1_clk>;
|
||||
clock-names = "apb", "ir";
|
||||
interrupts = <0 6 4>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x01c21c00 0x40>;
|
||||
status = "disabled";
|
||||
};
|
||||
@ -927,7 +929,7 @@ ir1: ir@01c21c00 {
|
||||
lradc: lradc@01c22800 {
|
||||
compatible = "allwinner,sun4i-a10-lradc-keys";
|
||||
reg = <0x01c22800 0x100>;
|
||||
interrupts = <0 31 4>;
|
||||
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -939,13 +941,13 @@ sid: eeprom@01c23800 {
|
||||
rtp: rtp@01c25000 {
|
||||
compatible = "allwinner,sun4i-a10-ts";
|
||||
reg = <0x01c25000 0x100>;
|
||||
interrupts = <0 29 4>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart0: serial@01c28000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28000 0x400>;
|
||||
interrupts = <0 1 4>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 16>;
|
||||
@ -955,7 +957,7 @@ uart0: serial@01c28000 {
|
||||
uart1: serial@01c28400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28400 0x400>;
|
||||
interrupts = <0 2 4>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 17>;
|
||||
@ -965,7 +967,7 @@ uart1: serial@01c28400 {
|
||||
uart2: serial@01c28800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28800 0x400>;
|
||||
interrupts = <0 3 4>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 18>;
|
||||
@ -975,7 +977,7 @@ uart2: serial@01c28800 {
|
||||
uart3: serial@01c28c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28c00 0x400>;
|
||||
interrupts = <0 4 4>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 19>;
|
||||
@ -985,7 +987,7 @@ uart3: serial@01c28c00 {
|
||||
uart4: serial@01c29000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c29000 0x400>;
|
||||
interrupts = <0 17 4>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 20>;
|
||||
@ -995,7 +997,7 @@ uart4: serial@01c29000 {
|
||||
uart5: serial@01c29400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c29400 0x400>;
|
||||
interrupts = <0 18 4>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 21>;
|
||||
@ -1005,7 +1007,7 @@ uart5: serial@01c29400 {
|
||||
uart6: serial@01c29800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c29800 0x400>;
|
||||
interrupts = <0 19 4>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 22>;
|
||||
@ -1015,7 +1017,7 @@ uart6: serial@01c29800 {
|
||||
uart7: serial@01c29c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c29c00 0x400>;
|
||||
interrupts = <0 20 4>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 23>;
|
||||
@ -1025,7 +1027,7 @@ uart7: serial@01c29c00 {
|
||||
i2c0: i2c@01c2ac00 {
|
||||
compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2ac00 0x400>;
|
||||
interrupts = <0 7 4>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 0>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
@ -1035,7 +1037,7 @@ i2c0: i2c@01c2ac00 {
|
||||
i2c1: i2c@01c2b000 {
|
||||
compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2b000 0x400>;
|
||||
interrupts = <0 8 4>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 1>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
@ -1045,7 +1047,7 @@ i2c1: i2c@01c2b000 {
|
||||
i2c2: i2c@01c2b400 {
|
||||
compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2b400 0x400>;
|
||||
interrupts = <0 9 4>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 2>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
@ -1055,7 +1057,7 @@ i2c2: i2c@01c2b400 {
|
||||
i2c3: i2c@01c2b800 {
|
||||
compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2b800 0x400>;
|
||||
interrupts = <0 88 4>;
|
||||
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 3>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
@ -1065,7 +1067,7 @@ i2c3: i2c@01c2b800 {
|
||||
i2c4: i2c@01c2c000 {
|
||||
compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
|
||||
reg = <0x01c2c000 0x400>;
|
||||
interrupts = <0 89 4>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 15>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
@ -1075,7 +1077,7 @@ i2c4: i2c@01c2c000 {
|
||||
gmac: ethernet@01c50000 {
|
||||
compatible = "allwinner,sun7i-a20-gmac";
|
||||
reg = <0x01c50000 0x10000>;
|
||||
interrupts = <0 85 4>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "macirq";
|
||||
clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
|
||||
clock-names = "stmmaceth", "allwinner_gmac_tx";
|
||||
@ -1090,10 +1092,10 @@ gmac: ethernet@01c50000 {
|
||||
hstimer@01c60000 {
|
||||
compatible = "allwinner,sun7i-a20-hstimer";
|
||||
reg = <0x01c60000 0x1000>;
|
||||
interrupts = <0 81 4>,
|
||||
<0 82 4>,
|
||||
<0 83 4>,
|
||||
<0 84 4>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ahb_gates 28>;
|
||||
};
|
||||
|
||||
@ -1105,7 +1107,7 @@ gic: interrupt-controller@01c81000 {
|
||||
<0x01c86000 0x2000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -49,6 +49,8 @@
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include <dt-bindings/pinctrl/sun4i-a10.h>
|
||||
|
||||
/ {
|
||||
@ -244,7 +246,7 @@ soc@01c00000 {
|
||||
dma: dma-controller@01c02000 {
|
||||
compatible = "allwinner,sun8i-a23-dma";
|
||||
reg = <0x01c02000 0x1000>;
|
||||
interrupts = <0 50 4>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ahb1_gates 6>;
|
||||
resets = <&ahb1_rst 6>;
|
||||
#dma-cells = <1>;
|
||||
@ -257,7 +259,7 @@ mmc0: mmc@01c0f000 {
|
||||
clock-names = "ahb", "mmc";
|
||||
resets = <&ahb1_rst 8>;
|
||||
reset-names = "ahb";
|
||||
interrupts = <0 60 4>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -268,7 +270,7 @@ mmc1: mmc@01c10000 {
|
||||
clock-names = "ahb", "mmc";
|
||||
resets = <&ahb1_rst 9>;
|
||||
reset-names = "ahb";
|
||||
interrupts = <0 61 4>;
|
||||
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -279,16 +281,16 @@ mmc2: mmc@01c11000 {
|
||||
clock-names = "ahb", "mmc";
|
||||
resets = <&ahb1_rst 10>;
|
||||
reset-names = "ahb";
|
||||
interrupts = <0 62 4>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pio: pinctrl@01c20800 {
|
||||
compatible = "allwinner,sun8i-a23-pinctrl";
|
||||
reg = <0x01c20800 0x400>;
|
||||
interrupts = <0 11 4>,
|
||||
<0 15 4>,
|
||||
<0 17 4>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 5>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
@ -360,21 +362,21 @@ apb2_rst: reset@01c202d8 {
|
||||
timer@01c20c00 {
|
||||
compatible = "allwinner,sun4i-a10-timer";
|
||||
reg = <0x01c20c00 0xa0>;
|
||||
interrupts = <0 18 4>,
|
||||
<0 19 4>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
wdt0: watchdog@01c20ca0 {
|
||||
compatible = "allwinner,sun6i-a31-wdt";
|
||||
reg = <0x01c20ca0 0x20>;
|
||||
interrupts = <0 25 4>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart0: serial@01c28000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28000 0x400>;
|
||||
interrupts = <0 0 4>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb2_gates 16>;
|
||||
@ -387,7 +389,7 @@ uart0: serial@01c28000 {
|
||||
uart1: serial@01c28400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28400 0x400>;
|
||||
interrupts = <0 1 4>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb2_gates 17>;
|
||||
@ -400,7 +402,7 @@ uart1: serial@01c28400 {
|
||||
uart2: serial@01c28800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28800 0x400>;
|
||||
interrupts = <0 2 4>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb2_gates 18>;
|
||||
@ -413,7 +415,7 @@ uart2: serial@01c28800 {
|
||||
uart3: serial@01c28c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28c00 0x400>;
|
||||
interrupts = <0 3 4>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb2_gates 19>;
|
||||
@ -426,7 +428,7 @@ uart3: serial@01c28c00 {
|
||||
uart4: serial@01c29000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c29000 0x400>;
|
||||
interrupts = <0 4 4>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb2_gates 20>;
|
||||
@ -439,7 +441,7 @@ uart4: serial@01c29000 {
|
||||
i2c0: i2c@01c2ac00 {
|
||||
compatible = "allwinner,sun6i-a31-i2c";
|
||||
reg = <0x01c2ac00 0x400>;
|
||||
interrupts = <0 6 4>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb2_gates 0>;
|
||||
resets = <&apb2_rst 0>;
|
||||
status = "disabled";
|
||||
@ -450,7 +452,7 @@ i2c0: i2c@01c2ac00 {
|
||||
i2c1: i2c@01c2b000 {
|
||||
compatible = "allwinner,sun6i-a31-i2c";
|
||||
reg = <0x01c2b000 0x400>;
|
||||
interrupts = <0 7 4>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb2_gates 1>;
|
||||
resets = <&apb2_rst 1>;
|
||||
status = "disabled";
|
||||
@ -461,7 +463,7 @@ i2c1: i2c@01c2b000 {
|
||||
i2c2: i2c@01c2b400 {
|
||||
compatible = "allwinner,sun6i-a31-i2c";
|
||||
reg = <0x01c2b400 0x400>;
|
||||
interrupts = <0 8 4>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb2_gates 2>;
|
||||
resets = <&apb2_rst 2>;
|
||||
status = "disabled";
|
||||
@ -477,13 +479,14 @@ gic: interrupt-controller@01c81000 {
|
||||
<0x01c86000 0x2000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
rtc: rtc@01f00000 {
|
||||
compatible = "allwinner,sun6i-a31-rtc";
|
||||
reg = <0x01f00000 0x54>;
|
||||
interrupts = <0 40 4>, <0 41 4>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
prcm@01f01400 {
|
||||
@ -533,7 +536,7 @@ apb0_rst: apb0_rst {
|
||||
r_uart: serial@01f02800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01f02800 0x400>;
|
||||
interrupts = <0 38 4>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb0_gates 4>;
|
||||
@ -544,7 +547,7 @@ r_uart: serial@01f02800 {
|
||||
r_pio: pinctrl@01f02c00 {
|
||||
compatible = "allwinner,sun8i-a23-r-pinctrl";
|
||||
reg = <0x01f02c00 0x400>;
|
||||
interrupts = <0 45 4>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb0_gates 0>;
|
||||
resets = <&apb0_rst 0>;
|
||||
gpio-controller;
|
||||
|
||||
@ -49,6 +49,8 @@
|
||||
|
||||
#include "skeleton64.dtsi"
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include <dt-bindings/pinctrl/sun4i-a10.h>
|
||||
|
||||
/ {
|
||||
@ -293,7 +295,7 @@ gic: interrupt-controller@01c41000 {
|
||||
<0x01c46000 0x2000>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <1 9 0xf04>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
ahb0_resets: reset@060005a0 {
|
||||
@ -329,12 +331,12 @@ apb1_resets: reset@060005b4 {
|
||||
timer@06000c00 {
|
||||
compatible = "allwinner,sun4i-a10-timer";
|
||||
reg = <0x06000c00 0xa0>;
|
||||
interrupts = <0 18 4>,
|
||||
<0 19 4>,
|
||||
<0 20 4>,
|
||||
<0 21 4>,
|
||||
<0 22 4>,
|
||||
<0 23 4>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
@ -342,11 +344,11 @@ timer@06000c00 {
|
||||
pio: pinctrl@06000800 {
|
||||
compatible = "allwinner,sun9i-a80-pinctrl";
|
||||
reg = <0x06000800 0x400>;
|
||||
interrupts = <0 11 4>,
|
||||
<0 15 4>,
|
||||
<0 16 4>,
|
||||
<0 17 4>,
|
||||
<0 120 4>;
|
||||
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb0_gates 5>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
@ -379,7 +381,7 @@ uart4_pins_a: uart4@0 {
|
||||
uart0: serial@07000000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x07000000 0x400>;
|
||||
interrupts = <0 0 4>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 16>;
|
||||
@ -390,7 +392,7 @@ uart0: serial@07000000 {
|
||||
uart1: serial@07000400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x07000400 0x400>;
|
||||
interrupts = <0 1 4>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 17>;
|
||||
@ -401,7 +403,7 @@ uart1: serial@07000400 {
|
||||
uart2: serial@07000800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x07000800 0x400>;
|
||||
interrupts = <0 2 4>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 18>;
|
||||
@ -412,7 +414,7 @@ uart2: serial@07000800 {
|
||||
uart3: serial@07000c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x07000c00 0x400>;
|
||||
interrupts = <0 3 4>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 19>;
|
||||
@ -423,7 +425,7 @@ uart3: serial@07000c00 {
|
||||
uart4: serial@07001000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x07001000 0x400>;
|
||||
interrupts = <0 4 4>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 20>;
|
||||
@ -434,7 +436,7 @@ uart4: serial@07001000 {
|
||||
uart5: serial@07001400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x07001400 0x400>;
|
||||
interrupts = <0 5 4>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 21>;
|
||||
@ -445,7 +447,7 @@ uart5: serial@07001400 {
|
||||
i2c0: i2c@07002800 {
|
||||
compatible = "allwinner,sun6i-a31-i2c";
|
||||
reg = <0x07002800 0x400>;
|
||||
interrupts = <0 6 4>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 0>;
|
||||
resets = <&apb1_resets 0>;
|
||||
status = "disabled";
|
||||
@ -456,7 +458,7 @@ i2c0: i2c@07002800 {
|
||||
i2c1: i2c@07002c00 {
|
||||
compatible = "allwinner,sun6i-a31-i2c";
|
||||
reg = <0x07002c00 0x400>;
|
||||
interrupts = <0 7 4>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 1>;
|
||||
resets = <&apb1_resets 1>;
|
||||
status = "disabled";
|
||||
@ -467,7 +469,7 @@ i2c1: i2c@07002c00 {
|
||||
i2c2: i2c@07003000 {
|
||||
compatible = "allwinner,sun6i-a31-i2c";
|
||||
reg = <0x07003000 0x400>;
|
||||
interrupts = <0 8 4>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 2>;
|
||||
resets = <&apb1_resets 2>;
|
||||
status = "disabled";
|
||||
@ -478,7 +480,7 @@ i2c2: i2c@07003000 {
|
||||
i2c3: i2c@07003400 {
|
||||
compatible = "allwinner,sun6i-a31-i2c";
|
||||
reg = <0x07003400 0x400>;
|
||||
interrupts = <0 9 4>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 3>;
|
||||
resets = <&apb1_resets 3>;
|
||||
status = "disabled";
|
||||
@ -489,7 +491,7 @@ i2c3: i2c@07003400 {
|
||||
i2c4: i2c@07003800 {
|
||||
compatible = "allwinner,sun6i-a31-i2c";
|
||||
reg = <0x07003800 0x400>;
|
||||
interrupts = <0 10 4>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&apb1_gates 4>;
|
||||
resets = <&apb1_resets 4>;
|
||||
status = "disabled";
|
||||
@ -500,13 +502,13 @@ i2c4: i2c@07003800 {
|
||||
r_wdt: watchdog@08001000 {
|
||||
compatible = "allwinner,sun6i-a31-wdt";
|
||||
reg = <0x08001000 0x20>;
|
||||
interrupts = <0 36 4>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
r_uart: serial@08002800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x08002800 0x400>;
|
||||
interrupts = <0 38 4>;
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&osc24M>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user