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arm64: Remove pgprot_dmacoherent()
Since this macro is identical to pgprot_writecombine() and is only used in a single place, remove it completely to avoid confusion. On ARMv7+ processors, the coherent DMA mapping must be Normal NonCacheable (a.k.a. writecombine) to avoid mismatched hardware attribute aliases (with the kernel linear mapping as Normal Cacheable). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -280,8 +280,6 @@ static inline int has_transparent_hugepage(void)
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
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#define pgprot_writecombine(prot) \
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
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#define pgprot_dmacoherent(prot) \
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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struct file;
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extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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@ -33,10 +33,8 @@ EXPORT_SYMBOL(dma_ops);
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static pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot,
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bool coherent)
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{
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if (dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs))
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if (!coherent || dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs))
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return pgprot_writecombine(prot);
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else if (!coherent)
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return pgprot_dmacoherent(prot);
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return prot;
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}
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