mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 07:46:45 +07:00
drm/radeon/kms/evergreen: always set certain VGT regs at CP init
These should be handled by the clear_state setup, but set them directly as well just to be sure. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
129205910f
commit
18ff84da29
@ -1248,7 +1248,7 @@ static int evergreen_cp_start(struct radeon_device *rdev)
|
|||||||
cp_me = 0xff;
|
cp_me = 0xff;
|
||||||
WREG32(CP_ME_CNTL, cp_me);
|
WREG32(CP_ME_CNTL, cp_me);
|
||||||
|
|
||||||
r = radeon_ring_lock(rdev, evergreen_default_size + 15);
|
r = radeon_ring_lock(rdev, evergreen_default_size + 19);
|
||||||
if (r) {
|
if (r) {
|
||||||
DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
|
DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
|
||||||
return r;
|
return r;
|
||||||
@ -1281,6 +1281,11 @@ static int evergreen_cp_start(struct radeon_device *rdev)
|
|||||||
radeon_ring_write(rdev, 0xffffffff);
|
radeon_ring_write(rdev, 0xffffffff);
|
||||||
radeon_ring_write(rdev, 0xffffffff);
|
radeon_ring_write(rdev, 0xffffffff);
|
||||||
|
|
||||||
|
radeon_ring_write(rdev, 0xc0026900);
|
||||||
|
radeon_ring_write(rdev, 0x00000316);
|
||||||
|
radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
|
||||||
|
radeon_ring_write(rdev, 0x00000010); /* */
|
||||||
|
|
||||||
radeon_ring_unlock_commit(rdev);
|
radeon_ring_unlock_commit(rdev);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
Loading…
Reference in New Issue
Block a user