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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 20:47:12 +07:00
igb: add 88E1543 initialization code
Initialize the 88E1543 PHY. Signed-off-by: Todd Fujinaka <todd.fujinaka@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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e09b89069f
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@ -272,6 +272,11 @@ static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
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if (ret_val)
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goto out;
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}
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if (phy->id == M88E1543_E_PHY_ID) {
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ret_val = igb_initialize_M88E1543_phy(hw);
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if (ret_val)
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goto out;
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}
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break;
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case IGP03E1000_E_PHY_ID:
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phy->type = e1000_phy_igp_3;
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@ -925,6 +930,8 @@ static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
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if (phy->id == M88E1512_E_PHY_ID)
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ret_val = igb_initialize_M88E1512_phy(hw);
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if (phy->id == M88E1543_E_PHY_ID)
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ret_val = igb_initialize_M88E1543_phy(hw);
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out:
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return ret_val;
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}
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@ -990,6 +990,7 @@
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#define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */
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#define E1000_M88E1543_EEE_CTRL_1 0x0
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#define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */
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#define E1000_M88E1543_FIBER_CTRL 0x0
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#define E1000_EEE_ADV_DEV_I354 7
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#define E1000_EEE_ADV_ADDR_I354 60
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#define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */
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@ -2277,6 +2277,100 @@ s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw)
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return ret_val;
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}
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/**
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* igb_initialize_M88E1543_phy - Initialize M88E1512 PHY
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* @hw: pointer to the HW structure
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*
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* Initialize Marvell 1543 to work correctly with Avoton.
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**/
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s32 igb_initialize_M88E1543_phy(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val = 0;
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/* Switch to PHY page 0xFF. */
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ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
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if (ret_val)
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goto out;
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ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
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if (ret_val)
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goto out;
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ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
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if (ret_val)
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goto out;
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ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
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if (ret_val)
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goto out;
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ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
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if (ret_val)
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goto out;
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ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
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if (ret_val)
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goto out;
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ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
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if (ret_val)
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goto out;
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ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
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if (ret_val)
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goto out;
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ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
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if (ret_val)
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goto out;
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/* Switch to PHY page 0xFB. */
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ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
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if (ret_val)
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goto out;
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ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x0C0D);
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if (ret_val)
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goto out;
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/* Switch to PHY page 0x12. */
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ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
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if (ret_val)
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goto out;
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/* Change mode to SGMII-to-Copper */
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ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
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if (ret_val)
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goto out;
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/* Switch to PHY page 1. */
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ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
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if (ret_val)
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goto out;
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/* Change mode to 1000BASE-X/SGMII and autoneg enable */
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ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
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if (ret_val)
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goto out;
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/* Return the PHY to page 0. */
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ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
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if (ret_val)
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goto out;
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ret_val = igb_phy_sw_reset(hw);
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if (ret_val) {
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hw_dbg("Error committing the PHY changes\n");
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return ret_val;
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}
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/* msec_delay(1000); */
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usleep_range(1000, 2000);
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out:
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return ret_val;
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}
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/**
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* igb_power_up_phy_copper - Restore copper link in case of PHY power down
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* @hw: pointer to the HW structure
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@ -62,6 +62,7 @@ void igb_power_up_phy_copper(struct e1000_hw *hw);
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void igb_power_down_phy_copper(struct e1000_hw *hw);
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s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
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s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw);
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s32 igb_initialize_M88E1543_phy(struct e1000_hw *hw);
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s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
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s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
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s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
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