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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/amdgpu: add helper funcs to detect PCS error
Since from vega20, hardware supports run-time detect and report XGMI/WAFL PCS ras error. Add helper functions to walkthrough every type of ras error and report it if any. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang
Alex Deucher
parent
15a1fbdcfb
commit
18f36157f2
@ -26,7 +26,12 @@
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#include "amdgpu_xgmi.h"
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#include "amdgpu_smu.h"
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#include "amdgpu_ras.h"
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#include "soc15.h"
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#include "df/df_3_6_offset.h"
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#include "xgmi/xgmi_4_0_0_smn.h"
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#include "xgmi/xgmi_4_0_0_sh_mask.h"
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#include "wafl/wafl2_4_0_0_smn.h"
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#include "wafl/wafl2_4_0_0_sh_mask.h"
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static DEFINE_MUTEX(xgmi_mutex);
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@ -36,6 +41,94 @@ static DEFINE_MUTEX(xgmi_mutex);
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static struct amdgpu_hive_info xgmi_hives[AMDGPU_MAX_XGMI_HIVE];
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static unsigned hive_count = 0;
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static const int xgmi_pcs_err_status_reg_vg20[] = {
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smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS,
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smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000,
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};
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static const int wafl_pcs_err_status_reg_vg20[] = {
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smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS,
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smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000,
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};
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static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = {
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{"XGMI PCS DataLossErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)},
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{"XGMI PCS TrainingErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)},
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{"XGMI PCS CRCErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)},
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{"XGMI PCS BERExceededErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)},
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{"XGMI PCS TxMetaDataErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)},
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{"XGMI PCS ReplayBufParityErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)},
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{"XGMI PCS DataParityErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)},
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{"XGMI PCS ReplayFifoOverflowErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
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{"XGMI PCS ReplayFifoUnderflowErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
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{"XGMI PCS ElasticFifoOverflowErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
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{"XGMI PCS DeskewErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)},
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{"XGMI PCS DataStartupLimitErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)},
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{"XGMI PCS FCInitTimeoutErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)},
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{"XGMI PCS RecoveryTimeoutErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
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{"XGMI PCS ReadySerialTimeoutErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
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{"XGMI PCS ReadySerialAttemptErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
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{"XGMI PCS RecoveryAttemptErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)},
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{"XGMI PCS RecoveryRelockAttemptErr",
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SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
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};
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static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = {
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{"WAFL PCS DataLossErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)},
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{"WAFL PCS TrainingErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)},
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{"WAFL PCS CRCErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)},
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{"WAFL PCS BERExceededErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)},
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{"WAFL PCS TxMetaDataErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)},
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{"WAFL PCS ReplayBufParityErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)},
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{"WAFL PCS DataParityErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)},
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{"WAFL PCS ReplayFifoOverflowErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)},
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{"WAFL PCS ReplayFifoUnderflowErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)},
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{"WAFL PCS ElasticFifoOverflowErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)},
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{"WAFL PCS DeskewErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)},
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{"WAFL PCS DataStartupLimitErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)},
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{"WAFL PCS FCInitTimeoutErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)},
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{"WAFL PCS RecoveryTimeoutErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)},
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{"WAFL PCS ReadySerialTimeoutErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)},
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{"WAFL PCS ReadySerialAttemptErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)},
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{"WAFL PCS RecoveryAttemptErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)},
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{"WAFL PCS RecoveryRelockAttemptErr",
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SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)},
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};
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void *amdgpu_xgmi_hive_try_lock(struct amdgpu_hive_info *hive)
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{
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return &hive->device_list;
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@ -560,3 +653,83 @@ uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
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return addr + dram_base_addr;
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}
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static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev,
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uint32_t value,
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uint32_t *ue_count,
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uint32_t *ce_count,
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bool is_xgmi_pcs)
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{
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int i;
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int ue_cnt;
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if (is_xgmi_pcs) {
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/* query xgmi pcs error status,
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* only ue is supported */
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for (i = 0; i < ARRAY_SIZE(xgmi_pcs_ras_fields); i ++) {
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ue_cnt = (value &
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xgmi_pcs_ras_fields[i].pcs_err_mask) >>
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xgmi_pcs_ras_fields[i].pcs_err_shift;
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if (ue_cnt) {
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dev_info(adev->dev, "%s detected\n",
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xgmi_pcs_ras_fields[i].err_name);
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*ue_count += ue_cnt;
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}
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}
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} else {
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/* query wafl pcs error status,
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* only ue is supported */
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for (i = 0; i < ARRAY_SIZE(wafl_pcs_ras_fields); i++) {
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ue_cnt = (value &
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wafl_pcs_ras_fields[i].pcs_err_mask) >>
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wafl_pcs_ras_fields[i].pcs_err_shift;
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if (ue_cnt) {
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dev_info(adev->dev, "%s detected\n",
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wafl_pcs_ras_fields[i].err_name);
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*ue_count += ue_cnt;
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}
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}
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}
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return 0;
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}
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int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
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int i;
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uint32_t data;
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uint32_t ue_cnt = 0, ce_cnt = 0;
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if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL))
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return -EINVAL;
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err_data->ue_count = 0;
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err_data->ce_count = 0;
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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default:
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/* check xgmi pcs error */
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for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) {
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data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]);
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if (data)
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amdgpu_xgmi_query_pcs_error_status(adev,
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data, &ue_cnt, &ce_cnt, true);
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}
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/* check wafl pcs error */
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for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) {
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data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]);
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if (data)
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amdgpu_xgmi_query_pcs_error_status(adev,
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data, &ue_cnt, &ce_cnt, false);
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}
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break;
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}
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err_data->ue_count += ue_cnt;
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err_data->ce_count += ce_cnt;
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return 0;
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}
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@ -37,6 +37,12 @@ struct amdgpu_hive_info {
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struct task_barrier tb;
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};
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struct amdgpu_pcs_ras_field {
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const char *err_name;
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uint32_t pcs_err_mask;
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uint32_t pcs_err_shift;
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};
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struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev, int lock);
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int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);
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int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
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@ -48,6 +54,8 @@ int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev);
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void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev);
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uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
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uint64_t addr);
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int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status);
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static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
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struct amdgpu_device *bo_adev)
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