mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 06:23:17 +07:00
iwlwifi: dbg: move debug data to a struct
The debug variables are bloating the iwl_fw struct. And the fields are out of order, missing docs and some are redundant. Clean this up. This serves as preparation for unionizing it for the new ini infra. Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
parent
2e1976bb75
commit
17b809c9b2
@ -240,7 +240,7 @@ static void iwl_fw_dump_fifos(struct iwl_fw_runtime *fwrt,
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if (!iwl_trans_grab_nic_access(fwrt->trans, &flags))
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return;
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_RXF)) {
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_RXF)) {
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/* Pull RXF1 */
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iwl_fwrt_dump_rxf(fwrt, dump_data,
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cfg->lmac[0].rxfifo1_size, 0, 0);
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@ -254,7 +254,7 @@ static void iwl_fw_dump_fifos(struct iwl_fw_runtime *fwrt,
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LMAC2_PRPH_OFFSET, 2);
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}
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_TXF)) {
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_TXF)) {
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/* Pull TXF data from LMAC1 */
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for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) {
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/* Mark the number of TXF we're pulling now */
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@ -279,7 +279,7 @@ static void iwl_fw_dump_fifos(struct iwl_fw_runtime *fwrt,
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}
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}
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_INTERNAL_TXF) &&
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fw_has_capa(&fwrt->fw->ucode_capa,
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IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
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/* Pull UMAC internal TXF data from all TXFs */
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@ -576,11 +576,11 @@ static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt,
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u32 sram_len, u32 sram_ofs, u32 smem_len,
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u32 sram2_len)
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{
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const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = fwrt->fw->dbg_mem_tlv;
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const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = fwrt->fw->dbg.mem_tlv;
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struct iwl_fw_error_dump_mem *dump_mem;
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int i;
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if (!fwrt->fw->n_dbg_mem_tlv) {
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if (!fwrt->fw->dbg.n_mem_tlv) {
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(*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM);
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(*dump_data)->len = cpu_to_le32(sram_len + sizeof(*dump_mem));
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dump_mem = (void *)(*dump_data)->data;
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@ -591,7 +591,7 @@ static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt,
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*dump_data = iwl_fw_error_next_data(*dump_data);
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}
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for (i = 0; i < fwrt->fw->n_dbg_mem_tlv; i++) {
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for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) {
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u32 len = le32_to_cpu(fw_dbg_mem[i].len);
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u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs);
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@ -645,11 +645,11 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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struct iwl_fw_dump_ptrs *fw_error_dump;
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struct scatterlist *sg_dump_data;
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u32 sram_len, sram_ofs;
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const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = fwrt->fw->dbg_mem_tlv;
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const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = fwrt->fw->dbg.mem_tlv;
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struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg;
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u32 file_len, fifo_data_len = 0, prph_len = 0, radio_len = 0;
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u32 smem_len = fwrt->fw->n_dbg_mem_tlv ? 0 : fwrt->trans->cfg->smem_len;
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u32 sram2_len = fwrt->fw->n_dbg_mem_tlv ?
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u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len;
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u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ?
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0 : fwrt->trans->cfg->dccm2_len;
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bool monitor_dump_only = false;
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int i;
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@ -686,7 +686,7 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) {
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fifo_data_len = 0;
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_RXF)) {
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_RXF)) {
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/* Count RXF2 size */
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if (mem_cfg->rxfifo2_size) {
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@ -710,7 +710,7 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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}
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}
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_TXF)) {
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_TXF)) {
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size_t fifo_const_len = sizeof(*dump_data) +
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sizeof(struct iwl_fw_error_dump_fifo);
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@ -731,7 +731,7 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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}
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}
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if ((fwrt->fw->dbg_dump_mask &
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if ((fwrt->fw->dbg.dump_mask &
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BIT(IWL_FW_ERROR_DUMP_INTERNAL_TXF)) &&
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fw_has_capa(&fwrt->fw->ucode_capa,
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IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) {
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@ -751,11 +751,11 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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/* Make room for PRPH registers */
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if (!fwrt->trans->cfg->gen2 &&
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fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_PRPH))
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fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_PRPH))
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prph_len += iwl_fw_get_prph_len(fwrt);
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if (fwrt->trans->cfg->device_family == IWL_DEVICE_FAMILY_7000 &&
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fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_RADIO_REG))
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fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_RADIO_REG))
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radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ;
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}
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@ -764,12 +764,12 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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prph_len +
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radio_len;
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_DEV_FW_INFO))
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_DEV_FW_INFO))
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file_len += sizeof(*dump_data) + sizeof(*dump_info);
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM_CFG))
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM_CFG))
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file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg);
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM)) {
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM)) {
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/* Make room for the SMEM, if it exists */
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if (smem_len)
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file_len += sizeof(*dump_data) + smem_len +
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@ -781,7 +781,7 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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sizeof(struct iwl_fw_error_dump_mem);
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/* Make room for MEM segments */
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for (i = 0; i < fwrt->fw->n_dbg_mem_tlv; i++) {
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for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) {
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file_len += sizeof(*dump_data) +
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le32_to_cpu(fw_dbg_mem[i].len) +
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sizeof(struct iwl_fw_error_dump_mem);
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@ -789,7 +789,7 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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}
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/* Make room for fw's virtual image pages, if it exists */
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING) &&
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING) &&
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!fwrt->trans->cfg->gen2 &&
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fwrt->fw->img[fwrt->cur_fw_img].paging_mem_size &&
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fwrt->fw_paging_db[0].fw_paging_block)
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@ -809,13 +809,13 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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sizeof(*dump_info) + sizeof(*dump_smem_cfg);
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}
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_ERROR_INFO) &&
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_ERROR_INFO) &&
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fwrt->dump.desc)
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file_len += sizeof(*dump_data) + sizeof(*dump_trig) +
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fwrt->dump.desc->len;
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM) &&
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!fwrt->fw->n_dbg_mem_tlv)
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM) &&
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!fwrt->fw->dbg.n_mem_tlv)
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file_len += sizeof(*dump_data) + sram_len +
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sizeof(struct iwl_fw_error_dump_mem);
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@ -830,7 +830,7 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER);
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dump_data = (void *)dump_file->data;
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_DEV_FW_INFO)) {
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_DEV_FW_INFO)) {
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dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO);
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dump_data->len = cpu_to_le32(sizeof(*dump_info));
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dump_info = (void *)dump_data->data;
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@ -851,7 +851,7 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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dump_data = iwl_fw_error_next_data(dump_data);
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}
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM_CFG)) {
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM_CFG)) {
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/* Dump shared memory configuration */
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dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG);
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dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg));
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@ -888,7 +888,7 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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iwl_read_radio_regs(fwrt, &dump_data);
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}
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_ERROR_INFO) &&
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_ERROR_INFO) &&
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fwrt->dump.desc) {
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dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO);
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dump_data->len = cpu_to_le32(sizeof(*dump_trig) +
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@ -904,7 +904,7 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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if (monitor_dump_only)
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goto dump_trans_data;
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM))
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_MEM))
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iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, smem_len,
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sram2_len);
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@ -929,7 +929,7 @@ void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt)
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}
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/* Dump fw's virtual image */
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if (fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING) &&
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if (fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING) &&
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!fwrt->trans->cfg->gen2 &&
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fwrt->fw->img[fwrt->cur_fw_img].paging_mem_size &&
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fwrt->fw_paging_db[0].fw_paging_block) {
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@ -1118,17 +1118,17 @@ int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id)
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int ret;
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int i;
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if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg_conf_tlv),
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if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv),
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"Invalid configuration %d\n", conf_id))
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return -EINVAL;
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/* EARLY START - firmware's configuration is hard coded */
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if ((!fwrt->fw->dbg_conf_tlv[conf_id] ||
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!fwrt->fw->dbg_conf_tlv[conf_id]->num_of_hcmds) &&
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if ((!fwrt->fw->dbg.conf_tlv[conf_id] ||
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!fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) &&
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conf_id == FW_DBG_START_FROM_ALIVE)
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return 0;
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if (!fwrt->fw->dbg_conf_tlv[conf_id])
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if (!fwrt->fw->dbg.conf_tlv[conf_id])
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return -EINVAL;
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if (fwrt->dump.conf != FW_DBG_INVALID)
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@ -1136,8 +1136,8 @@ int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id)
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fwrt->dump.conf);
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/* Send all HCMDs for configuring the FW debug */
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ptr = (void *)&fwrt->fw->dbg_conf_tlv[conf_id]->hcmd;
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for (i = 0; i < fwrt->fw->dbg_conf_tlv[conf_id]->num_of_hcmds; i++) {
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ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd;
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for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) {
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struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
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struct iwl_host_cmd hcmd = {
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.id = cmd->id,
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@ -1183,7 +1183,7 @@ void iwl_fw_error_dump_wk(struct work_struct *work)
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/* start recording again if the firmware is not crashed */
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if (!test_bit(STATUS_FW_ERROR, &fwrt->trans->status) &&
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fwrt->fw->dbg_dest_tlv) {
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fwrt->fw->dbg.dest_tlv) {
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/* wait before we collect the data till the DBGC stop */
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udelay(500);
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iwl_fw_dbg_restart_recording(fwrt, ¶ms);
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@ -118,14 +118,14 @@ int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt,
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int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 id);
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#define iwl_fw_dbg_trigger_enabled(fw, id) ({ \
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void *__dbg_trigger = (fw)->dbg_trigger_tlv[(id)]; \
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void *__dbg_trigger = (fw)->dbg.trigger_tlv[(id)]; \
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unlikely(__dbg_trigger); \
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})
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static inline struct iwl_fw_dbg_trigger_tlv*
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_iwl_fw_dbg_get_trigger(const struct iwl_fw *fw, enum iwl_fw_dbg_trigger id)
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{
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return fw->dbg_trigger_tlv[id];
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return fw->dbg.trigger_tlv[id];
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}
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#define iwl_fw_dbg_get_trigger(fw, id) ({ \
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@ -293,7 +293,7 @@ static inline bool iwl_fw_dbg_is_d3_debug_enabled(struct iwl_fw_runtime *fwrt)
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return fw_has_capa(&fwrt->fw->ucode_capa,
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IWL_UCODE_TLV_CAPA_D3_DEBUG) &&
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fwrt->trans->cfg->d3_debug_data_length &&
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fwrt->fw->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA);
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fwrt->fw->dbg.dump_mask & BIT(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA);
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}
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void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt);
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@ -197,6 +197,29 @@ enum iwl_fw_type {
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IWL_FW_MVM,
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};
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/**
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* struct iwl_fw_dbg - debug data
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*
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* @dest_tlv: points to debug destination TLV (typically SRAM or DRAM)
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* @n_dest_reg: num of reg_ops in dest_tlv
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* @conf_tlv: array of pointers to configuration HCMDs
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* @trigger_tlv: array of pointers to triggers TLVs
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* @trigger_tlv_len: lengths of the @dbg_trigger_tlv entries
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* @mem_tlv: Runtime addresses to dump
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* @n_mem_tlv: number of runtime addresses
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* @dump_mask: bitmask of dump regions
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*/
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struct iwl_fw_dbg {
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struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv;
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u8 n_dest_reg;
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struct iwl_fw_dbg_conf_tlv *conf_tlv[FW_DBG_CONF_MAX];
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struct iwl_fw_dbg_trigger_tlv *trigger_tlv[FW_DBG_TRIGGER_MAX];
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size_t trigger_tlv_len[FW_DBG_TRIGGER_MAX];
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struct iwl_fw_dbg_mem_seg_tlv *mem_tlv;
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size_t n_mem_tlv;
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u32 dump_mask;
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};
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/**
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* struct iwl_fw - variables associated with the firmware
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*
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@ -217,12 +240,6 @@ enum iwl_fw_type {
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* @cipher_scheme: optional external cipher scheme.
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* @human_readable: human readable version
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* we get the ALIVE from the uCode
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* @dbg_dest_tlv: points to the destination TLV for debug
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* @dbg_conf_tlv: array of pointers to configuration TLVs for debug
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* @dbg_conf_tlv_len: lengths of the @dbg_conf_tlv entries
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* @dbg_trigger_tlv: array of pointers to triggers TLVs
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* @dbg_trigger_tlv_len: lengths of the @dbg_trigger_tlv entries
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* @dbg_dest_reg_num: num of reg_ops in %dbg_dest_tlv
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*/
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struct iwl_fw {
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u32 ucode_ver;
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@ -250,15 +267,7 @@ struct iwl_fw {
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struct iwl_fw_cipher_scheme cs[IWL_UCODE_MAX_CS];
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u8 human_readable[FW_VER_HUMAN_READABLE_SZ];
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struct iwl_fw_dbg_dest_tlv_v1 *dbg_dest_tlv;
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struct iwl_fw_dbg_conf_tlv *dbg_conf_tlv[FW_DBG_CONF_MAX];
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size_t dbg_conf_tlv_len[FW_DBG_CONF_MAX];
|
||||
struct iwl_fw_dbg_trigger_tlv *dbg_trigger_tlv[FW_DBG_TRIGGER_MAX];
|
||||
struct iwl_fw_dbg_mem_seg_tlv *dbg_mem_tlv;
|
||||
size_t n_dbg_mem_tlv;
|
||||
size_t dbg_trigger_tlv_len[FW_DBG_TRIGGER_MAX];
|
||||
u8 dbg_dest_reg_num;
|
||||
u32 dbg_dump_mask;
|
||||
struct iwl_fw_dbg dbg;
|
||||
};
|
||||
|
||||
static inline const char *get_fw_dbg_mode_string(int mode)
|
||||
@ -280,7 +289,7 @@ static inline const char *get_fw_dbg_mode_string(int mode)
|
||||
static inline bool
|
||||
iwl_fw_dbg_conf_usniffer(const struct iwl_fw *fw, u8 id)
|
||||
{
|
||||
const struct iwl_fw_dbg_conf_tlv *conf_tlv = fw->dbg_conf_tlv[id];
|
||||
const struct iwl_fw_dbg_conf_tlv *conf_tlv = fw->dbg.conf_tlv[id];
|
||||
|
||||
if (!conf_tlv)
|
||||
return false;
|
||||
|
@ -168,12 +168,12 @@ static void iwl_dealloc_ucode(struct iwl_drv *drv)
|
||||
{
|
||||
int i;
|
||||
|
||||
kfree(drv->fw.dbg_dest_tlv);
|
||||
for (i = 0; i < ARRAY_SIZE(drv->fw.dbg_conf_tlv); i++)
|
||||
kfree(drv->fw.dbg_conf_tlv[i]);
|
||||
for (i = 0; i < ARRAY_SIZE(drv->fw.dbg_trigger_tlv); i++)
|
||||
kfree(drv->fw.dbg_trigger_tlv[i]);
|
||||
kfree(drv->fw.dbg_mem_tlv);
|
||||
kfree(drv->fw.dbg.dest_tlv);
|
||||
for (i = 0; i < ARRAY_SIZE(drv->fw.dbg.conf_tlv); i++)
|
||||
kfree(drv->fw.dbg.conf_tlv[i]);
|
||||
for (i = 0; i < ARRAY_SIZE(drv->fw.dbg.trigger_tlv); i++)
|
||||
kfree(drv->fw.dbg.trigger_tlv[i]);
|
||||
kfree(drv->fw.dbg.mem_tlv);
|
||||
kfree(drv->fw.iml);
|
||||
|
||||
for (i = 0; i < IWL_UCODE_TYPE_MAX; i++)
|
||||
@ -303,7 +303,7 @@ struct iwl_firmware_pieces {
|
||||
struct iwl_fw_dbg_trigger_tlv *dbg_trigger_tlv[FW_DBG_TRIGGER_MAX];
|
||||
size_t dbg_trigger_tlv_len[FW_DBG_TRIGGER_MAX];
|
||||
struct iwl_fw_dbg_mem_seg_tlv *dbg_mem_tlv;
|
||||
size_t n_dbg_mem_tlv;
|
||||
size_t n_mem_tlv;
|
||||
};
|
||||
|
||||
/*
|
||||
@ -936,7 +936,7 @@ static int iwl_parse_tlv_firmware(struct iwl_drv *drv,
|
||||
IWL_INFO(drv, "Found debug destination: %s\n",
|
||||
get_fw_dbg_mode_string(mon_mode));
|
||||
|
||||
drv->fw.dbg_dest_reg_num = (dest_v1) ?
|
||||
drv->fw.dbg.n_dest_reg = (dest_v1) ?
|
||||
tlv_len -
|
||||
offsetof(struct iwl_fw_dbg_dest_tlv_v1,
|
||||
reg_ops) :
|
||||
@ -944,8 +944,8 @@ static int iwl_parse_tlv_firmware(struct iwl_drv *drv,
|
||||
offsetof(struct iwl_fw_dbg_dest_tlv,
|
||||
reg_ops);
|
||||
|
||||
drv->fw.dbg_dest_reg_num /=
|
||||
sizeof(drv->fw.dbg_dest_tlv->reg_ops[0]);
|
||||
drv->fw.dbg.n_dest_reg /=
|
||||
sizeof(drv->fw.dbg.dest_tlv->reg_ops[0]);
|
||||
|
||||
break;
|
||||
}
|
||||
@ -959,7 +959,7 @@ static int iwl_parse_tlv_firmware(struct iwl_drv *drv,
|
||||
break;
|
||||
}
|
||||
|
||||
if (conf->id >= ARRAY_SIZE(drv->fw.dbg_conf_tlv)) {
|
||||
if (conf->id >= ARRAY_SIZE(drv->fw.dbg.conf_tlv)) {
|
||||
IWL_ERR(drv,
|
||||
"Skip unknown configuration: %d\n",
|
||||
conf->id);
|
||||
@ -988,7 +988,7 @@ static int iwl_parse_tlv_firmware(struct iwl_drv *drv,
|
||||
(void *)tlv_data;
|
||||
u32 trigger_id = le32_to_cpu(trigger->id);
|
||||
|
||||
if (trigger_id >= ARRAY_SIZE(drv->fw.dbg_trigger_tlv)) {
|
||||
if (trigger_id >= ARRAY_SIZE(drv->fw.dbg.trigger_tlv)) {
|
||||
IWL_ERR(drv,
|
||||
"Skip unknown trigger: %u\n",
|
||||
trigger->id);
|
||||
@ -1015,7 +1015,7 @@ static int iwl_parse_tlv_firmware(struct iwl_drv *drv,
|
||||
break;
|
||||
}
|
||||
|
||||
drv->fw.dbg_dump_mask =
|
||||
drv->fw.dbg.dump_mask =
|
||||
le32_to_cpup((__le32 *)tlv_data);
|
||||
break;
|
||||
}
|
||||
@ -1070,13 +1070,13 @@ static int iwl_parse_tlv_firmware(struct iwl_drv *drv,
|
||||
dbg_mem->data_type);
|
||||
|
||||
size = sizeof(*pieces->dbg_mem_tlv) *
|
||||
(pieces->n_dbg_mem_tlv + 1);
|
||||
(pieces->n_mem_tlv + 1);
|
||||
n = krealloc(pieces->dbg_mem_tlv, size, GFP_KERNEL);
|
||||
if (!n)
|
||||
return -ENOMEM;
|
||||
pieces->dbg_mem_tlv = n;
|
||||
pieces->dbg_mem_tlv[pieces->n_dbg_mem_tlv] = *dbg_mem;
|
||||
pieces->n_dbg_mem_tlv++;
|
||||
pieces->dbg_mem_tlv[pieces->n_mem_tlv] = *dbg_mem;
|
||||
pieces->n_mem_tlv++;
|
||||
break;
|
||||
}
|
||||
case IWL_UCODE_TLV_IML: {
|
||||
@ -1256,7 +1256,7 @@ static void iwl_req_fw_callback(const struct firmware *ucode_raw, void *context)
|
||||
IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
|
||||
fw->ucode_capa.n_scan_channels = IWL_DEFAULT_SCAN_CHANNELS;
|
||||
/* dump all fw memory areas by default except d3 debug data */
|
||||
fw->dbg_dump_mask = 0xfffdffff;
|
||||
fw->dbg.dump_mask = 0xfffdffff;
|
||||
|
||||
pieces = kzalloc(sizeof(*pieces), GFP_KERNEL);
|
||||
if (!pieces)
|
||||
@ -1323,21 +1323,21 @@ static void iwl_req_fw_callback(const struct firmware *ucode_raw, void *context)
|
||||
goto out_free_fw;
|
||||
|
||||
if (pieces->dbg_dest_tlv_init) {
|
||||
size_t dbg_dest_size = sizeof(*drv->fw.dbg_dest_tlv) +
|
||||
sizeof(drv->fw.dbg_dest_tlv->reg_ops[0]) *
|
||||
drv->fw.dbg_dest_reg_num;
|
||||
size_t dbg_dest_size = sizeof(*drv->fw.dbg.dest_tlv) +
|
||||
sizeof(drv->fw.dbg.dest_tlv->reg_ops[0]) *
|
||||
drv->fw.dbg.n_dest_reg;
|
||||
|
||||
drv->fw.dbg_dest_tlv = kmalloc(dbg_dest_size, GFP_KERNEL);
|
||||
drv->fw.dbg.dest_tlv = kmalloc(dbg_dest_size, GFP_KERNEL);
|
||||
|
||||
if (!drv->fw.dbg_dest_tlv)
|
||||
if (!drv->fw.dbg.dest_tlv)
|
||||
goto out_free_fw;
|
||||
|
||||
if (*pieces->dbg_dest_ver == 0) {
|
||||
memcpy(drv->fw.dbg_dest_tlv, pieces->dbg_dest_tlv_v1,
|
||||
memcpy(drv->fw.dbg.dest_tlv, pieces->dbg_dest_tlv_v1,
|
||||
dbg_dest_size);
|
||||
} else {
|
||||
struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv =
|
||||
drv->fw.dbg_dest_tlv;
|
||||
drv->fw.dbg.dest_tlv;
|
||||
|
||||
dest_tlv->version = pieces->dbg_dest_tlv->version;
|
||||
dest_tlv->monitor_mode =
|
||||
@ -1352,8 +1352,8 @@ static void iwl_req_fw_callback(const struct firmware *ucode_raw, void *context)
|
||||
pieces->dbg_dest_tlv->base_shift;
|
||||
memcpy(dest_tlv->reg_ops,
|
||||
pieces->dbg_dest_tlv->reg_ops,
|
||||
sizeof(drv->fw.dbg_dest_tlv->reg_ops[0]) *
|
||||
drv->fw.dbg_dest_reg_num);
|
||||
sizeof(drv->fw.dbg.dest_tlv->reg_ops[0]) *
|
||||
drv->fw.dbg.n_dest_reg);
|
||||
|
||||
/* In version 1 of the destination tlv, which is
|
||||
* relevant for internal buffer exclusively,
|
||||
@ -1369,15 +1369,13 @@ static void iwl_req_fw_callback(const struct firmware *ucode_raw, void *context)
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(drv->fw.dbg_conf_tlv); i++) {
|
||||
for (i = 0; i < ARRAY_SIZE(drv->fw.dbg.conf_tlv); i++) {
|
||||
if (pieces->dbg_conf_tlv[i]) {
|
||||
drv->fw.dbg_conf_tlv_len[i] =
|
||||
pieces->dbg_conf_tlv_len[i];
|
||||
drv->fw.dbg_conf_tlv[i] =
|
||||
drv->fw.dbg.conf_tlv[i] =
|
||||
kmemdup(pieces->dbg_conf_tlv[i],
|
||||
drv->fw.dbg_conf_tlv_len[i],
|
||||
pieces->dbg_conf_tlv_len[i],
|
||||
GFP_KERNEL);
|
||||
if (!drv->fw.dbg_conf_tlv[i])
|
||||
if (!pieces->dbg_conf_tlv_len[i])
|
||||
goto out_free_fw;
|
||||
}
|
||||
}
|
||||
@ -1404,7 +1402,7 @@ static void iwl_req_fw_callback(const struct firmware *ucode_raw, void *context)
|
||||
trigger_tlv_sz[FW_DBG_TRIGGER_TDLS] =
|
||||
sizeof(struct iwl_fw_dbg_trigger_tdls);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(drv->fw.dbg_trigger_tlv); i++) {
|
||||
for (i = 0; i < ARRAY_SIZE(drv->fw.dbg.trigger_tlv); i++) {
|
||||
if (pieces->dbg_trigger_tlv[i]) {
|
||||
/*
|
||||
* If the trigger isn't long enough, WARN and exit.
|
||||
@ -1417,22 +1415,22 @@ static void iwl_req_fw_callback(const struct firmware *ucode_raw, void *context)
|
||||
(trigger_tlv_sz[i] +
|
||||
sizeof(struct iwl_fw_dbg_trigger_tlv))))
|
||||
goto out_free_fw;
|
||||
drv->fw.dbg_trigger_tlv_len[i] =
|
||||
drv->fw.dbg.trigger_tlv_len[i] =
|
||||
pieces->dbg_trigger_tlv_len[i];
|
||||
drv->fw.dbg_trigger_tlv[i] =
|
||||
drv->fw.dbg.trigger_tlv[i] =
|
||||
kmemdup(pieces->dbg_trigger_tlv[i],
|
||||
drv->fw.dbg_trigger_tlv_len[i],
|
||||
drv->fw.dbg.trigger_tlv_len[i],
|
||||
GFP_KERNEL);
|
||||
if (!drv->fw.dbg_trigger_tlv[i])
|
||||
if (!drv->fw.dbg.trigger_tlv[i])
|
||||
goto out_free_fw;
|
||||
}
|
||||
}
|
||||
|
||||
/* Now that we can no longer fail, copy information */
|
||||
|
||||
drv->fw.dbg_mem_tlv = pieces->dbg_mem_tlv;
|
||||
drv->fw.dbg.mem_tlv = pieces->dbg_mem_tlv;
|
||||
pieces->dbg_mem_tlv = NULL;
|
||||
drv->fw.n_dbg_mem_tlv = pieces->n_dbg_mem_tlv;
|
||||
drv->fw.dbg.n_mem_tlv = pieces->n_mem_tlv;
|
||||
|
||||
/*
|
||||
* The (size - 16) / 12 formula is based on the information recorded
|
||||
|
@ -725,7 +725,7 @@ struct iwl_dram_data {
|
||||
* @dbg_dest_tlv: points to the destination TLV for debug
|
||||
* @dbg_conf_tlv: array of pointers to configuration TLVs for debug
|
||||
* @dbg_trigger_tlv: array of pointers to triggers TLVs for debug
|
||||
* @dbg_dest_reg_num: num of reg_ops in %dbg_dest_tlv
|
||||
* @dbg_n_dest_reg: num of reg_ops in %dbg_dest_tlv
|
||||
* @num_blocks: number of blocks in fw_mon
|
||||
* @fw_mon: address of the buffers for firmware monitor
|
||||
* @system_pm_mode: the system-wide power management mode in use.
|
||||
@ -778,7 +778,7 @@ struct iwl_trans {
|
||||
const struct iwl_fw_dbg_conf_tlv *dbg_conf_tlv[FW_DBG_CONF_MAX];
|
||||
struct iwl_fw_dbg_trigger_tlv * const *dbg_trigger_tlv;
|
||||
u32 dbg_dump_mask;
|
||||
u8 dbg_dest_reg_num;
|
||||
u8 dbg_n_dest_reg;
|
||||
int num_blocks;
|
||||
struct iwl_dram_data fw_mon[IWL_MAX_DEBUG_ALLOCATIONS];
|
||||
|
||||
|
@ -1026,7 +1026,7 @@ int iwl_mvm_up(struct iwl_mvm *mvm)
|
||||
|
||||
mvm->fwrt.dump.conf = FW_DBG_INVALID;
|
||||
/* if we have a destination, assume EARLY START */
|
||||
if (mvm->fw->dbg_dest_tlv)
|
||||
if (mvm->fw->dbg.dest_tlv)
|
||||
mvm->fwrt.dump.conf = FW_DBG_START_FROM_ALIVE;
|
||||
iwl_fw_start_dbg_conf(&mvm->fwrt, FW_DBG_START_FROM_ALIVE);
|
||||
|
||||
|
@ -748,12 +748,12 @@ iwl_op_mode_mvm_start(struct iwl_trans *trans, const struct iwl_cfg *cfg,
|
||||
iwl_trans_configure(mvm->trans, &trans_cfg);
|
||||
|
||||
trans->rx_mpdu_cmd = REPLY_RX_MPDU_CMD;
|
||||
trans->dbg_dest_tlv = mvm->fw->dbg_dest_tlv;
|
||||
trans->dbg_dest_reg_num = mvm->fw->dbg_dest_reg_num;
|
||||
memcpy(trans->dbg_conf_tlv, mvm->fw->dbg_conf_tlv,
|
||||
trans->dbg_dest_tlv = mvm->fw->dbg.dest_tlv;
|
||||
trans->dbg_n_dest_reg = mvm->fw->dbg.n_dest_reg;
|
||||
memcpy(trans->dbg_conf_tlv, mvm->fw->dbg.conf_tlv,
|
||||
sizeof(trans->dbg_conf_tlv));
|
||||
trans->dbg_trigger_tlv = mvm->fw->dbg_trigger_tlv;
|
||||
trans->dbg_dump_mask = mvm->fw->dbg_dump_mask;
|
||||
trans->dbg_trigger_tlv = mvm->fw->dbg.trigger_tlv;
|
||||
trans->dbg_dump_mask = mvm->fw->dbg.dump_mask;
|
||||
|
||||
trans->iml = mvm->fw->iml;
|
||||
trans->iml_len = mvm->fw->iml_len;
|
||||
|
@ -931,7 +931,7 @@ void iwl_pcie_apply_destination(struct iwl_trans *trans)
|
||||
else
|
||||
IWL_WARN(trans, "PCI should have external buffer debug\n");
|
||||
|
||||
for (i = 0; i < trans->dbg_dest_reg_num; i++) {
|
||||
for (i = 0; i < trans->dbg_n_dest_reg; i++) {
|
||||
u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
|
||||
u32 val = le32_to_cpu(dest->reg_ops[i].val);
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user