AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2025-02-05 01:55:29 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

ARM: dts: meson8: add the cortex-a9-pmu compatible PMU

Browse Source 
Enable the performance monitor unit on Meson8.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This commit is contained in:
Martin Blumenstingl 2018-04-22 12:45:01 +02:00 committed by Kevin Hilman
parent 60cc43fc88
commit 17b66027e6
1 changed files with 13 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
arch/arm/boot/dts/meson8.dtsi
View File

@ -57,7 +57,7 @@ cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
cpu@200 { cpu0: cpu@200 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>; next-level-cache = <&L2>;
@ -66,7 +66,7 @@ cpu@200 {
resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
}; };
cpu@201 { cpu1: cpu@201 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>; next-level-cache = <&L2>;
@ -75,7 +75,7 @@ cpu@201 {
resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
}; };
cpu@202 { cpu2: cpu@202 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>; next-level-cache = <&L2>;
@ -84,7 +84,7 @@ cpu@202 {
resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
}; };
cpu@203 { cpu3: cpu@203 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
next-level-cache = <&L2>; next-level-cache = <&L2>;
@ -94,6 +94,15 @@ cpu@203 {
}; };
}; };
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
reserved-memory { reserved-memory {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;