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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ethernet: cavium: octeon: Switch to using netdev_info().
Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -705,14 +705,15 @@ static int octeon_mgmt_ioctl_hwtstamp(struct net_device *netdev,
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u64 clock_comp = (NSEC_PER_SEC << 32) / octeon_get_io_clock_rate();
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u64 clock_comp = (NSEC_PER_SEC << 32) / octeon_get_io_clock_rate();
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if (!ptp.s.ptp_en)
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if (!ptp.s.ptp_en)
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cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, clock_comp);
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cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, clock_comp);
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pr_info("PTP Clock: Using sclk reference at %lld Hz\n",
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netdev_info(netdev,
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(NSEC_PER_SEC << 32) / clock_comp);
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"PTP Clock using sclk reference @ %lldHz\n",
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(NSEC_PER_SEC << 32) / clock_comp);
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} else {
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} else {
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/* The clock is already programmed to use a GPIO */
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/* The clock is already programmed to use a GPIO */
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u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP);
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u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP);
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pr_info("PTP Clock: Using GPIO %d at %lld Hz\n",
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netdev_info(netdev,
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ptp.s.ext_clk_in,
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"PTP Clock using GPIO%d @ %lld Hz\n",
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(NSEC_PER_SEC << 32) / clock_comp);
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ptp.s.ext_clk_in, (NSEC_PER_SEC << 32) / clock_comp);
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}
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}
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/* Enable the clock if it wasn't done already */
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/* Enable the clock if it wasn't done already */
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@ -926,14 +927,11 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev)
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spin_unlock_irqrestore(&p->lock, flags);
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spin_unlock_irqrestore(&p->lock, flags);
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if (link_changed != 0) {
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if (link_changed != 0) {
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if (link_changed > 0) {
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if (link_changed > 0)
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pr_info("%s: Link is up - %d/%s\n", netdev->name,
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netdev_info(netdev, "Link is up - %d/%s\n",
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phydev->speed,
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phydev->speed, phydev->duplex == DUPLEX_FULL ? "Full" : "Half");
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phydev->duplex == DUPLEX_FULL ?
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else
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"Full" : "Half");
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netdev_info(netdev, "Link is down\n");
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} else {
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pr_info("%s: Link is down\n", netdev->name);
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}
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}
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}
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}
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}
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