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pinctrl/amd: fix gpio irq level in debugfs
According to the AMD BKDG, the GPIO ActiveLevel bits (10:9) map to: 00 Active High 01 Active Low 10 Active on both edges iff LevelTrig (bit 8) == 0 11 Reserved The current code has a bug where it interprets 00 => Active Low, and 01 => Active High. Fix the bug, restrict "Active on both" to just the edge trigger case, and refactor a bit to make the logic more readable. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -247,16 +247,16 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
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raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
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if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
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u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
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ACTIVE_LEVEL_MASK;
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interrupt_enable = "interrupt is enabled|";
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if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&
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!(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))
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active_level = "Active low|";
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else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) &&
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!(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)))
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if (level == ACTIVE_LEVEL_HIGH)
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active_level = "Active high|";
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else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) &&
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pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))
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else if (level == ACTIVE_LEVEL_LOW)
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active_level = "Active low|";
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else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
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level == ACTIVE_LEVEL_BOTH)
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active_level = "Active on both|";
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else
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active_level = "Unknown Active level|";
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@ -54,6 +54,10 @@
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#define ACTIVE_LEVEL_MASK 0x3UL
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#define DRV_STRENGTH_SEL_MASK 0x3UL
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#define ACTIVE_LEVEL_HIGH 0x0UL
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#define ACTIVE_LEVEL_LOW 0x1UL
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#define ACTIVE_LEVEL_BOTH 0x2UL
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#define DB_TYPE_NO_DEBOUNCE 0x0UL
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#define DB_TYPE_PRESERVE_LOW_GLITCH 0x1UL
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#define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL
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