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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 21:50:53 +07:00
vxge: MSIX one shot mode
To reduce the possibility of losing an interrupt in the handler due to a race between an interrupt processing and disable/enable of interrupts, enable MSIX one shot. Also, add support for adaptive interrupt coalesing Signed-off-by: Jon Mason <jon.mason@exar.com> Signed-off-by: Masroor Vettuparambil <masroor.vettuparambil@exar.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jon Mason
David S. Miller
parent
1d15f81cda
commit
16fded7da2
@ -2868,6 +2868,8 @@ __vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
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ring->rxd_init = attr->rxd_init;
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ring->rxd_term = attr->rxd_term;
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ring->buffer_mode = config->buffer_mode;
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ring->tim_rti_cfg1_saved = vp->vpath->tim_rti_cfg1_saved;
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ring->tim_rti_cfg3_saved = vp->vpath->tim_rti_cfg3_saved;
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ring->rxds_limit = config->rxds_limit;
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ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
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@ -3511,6 +3513,8 @@ __vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
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/* apply "interrupts per txdl" attribute */
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fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
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fifo->tim_tti_cfg1_saved = vpath->tim_tti_cfg1_saved;
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fifo->tim_tti_cfg3_saved = vpath->tim_tti_cfg3_saved;
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if (fifo->config->intr)
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fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
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@ -4377,6 +4381,8 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
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}
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writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
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vpath->tim_tti_cfg1_saved = val64;
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val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
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if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
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@ -4433,6 +4439,7 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
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}
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writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
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vpath->tim_tti_cfg3_saved = val64;
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}
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if (config->ring.enable == VXGE_HW_RING_ENABLE) {
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@ -4481,6 +4488,8 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
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}
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writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
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vpath->tim_rti_cfg1_saved = val64;
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val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
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if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
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@ -4537,6 +4546,7 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
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}
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writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
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vpath->tim_rti_cfg3_saved = val64;
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}
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val64 = 0;
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@ -4555,26 +4565,6 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
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return status;
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}
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void vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id)
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{
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struct __vxge_hw_virtualpath *vpath;
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struct vxge_hw_vpath_reg __iomem *vp_reg;
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struct vxge_hw_vp_config *config;
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u64 val64;
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vpath = &hldev->virtual_paths[vp_id];
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vp_reg = vpath->vp_reg;
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config = vpath->vp_config;
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if (config->fifo.enable == VXGE_HW_FIFO_ENABLE &&
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config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
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config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
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val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
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val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
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writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
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}
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}
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/*
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* __vxge_hw_vpath_initialize
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* This routine is the final phase of init which initializes the
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@ -682,6 +682,10 @@ struct __vxge_hw_virtualpath {
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u32 vsport_number;
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u32 max_kdfc_db;
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u32 max_nofl_db;
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u64 tim_tti_cfg1_saved;
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u64 tim_tti_cfg3_saved;
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u64 tim_rti_cfg1_saved;
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u64 tim_rti_cfg3_saved;
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struct __vxge_hw_ring *____cacheline_aligned ringh;
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struct __vxge_hw_fifo *____cacheline_aligned fifoh;
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@ -921,6 +925,9 @@ struct __vxge_hw_ring {
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u32 doorbell_cnt;
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u32 total_db_cnt;
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u64 rxds_limit;
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u32 rtimer;
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u64 tim_rti_cfg1_saved;
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u64 tim_rti_cfg3_saved;
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enum vxge_hw_status (*callback)(
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struct __vxge_hw_ring *ringh,
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@ -1000,6 +1007,9 @@ struct __vxge_hw_fifo {
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u32 per_txdl_space;
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u32 vp_id;
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u32 tx_intr_num;
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u32 rtimer;
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u64 tim_tti_cfg1_saved;
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u64 tim_tti_cfg3_saved;
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enum vxge_hw_status (*callback)(
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struct __vxge_hw_fifo *fifo_handle,
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@ -371,9 +371,6 @@ vxge_rx_1b_compl(struct __vxge_hw_ring *ringh, void *dtr,
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struct vxge_hw_ring_rxd_info ext_info;
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vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d",
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ring->ndev->name, __func__, __LINE__);
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ring->pkts_processed = 0;
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vxge_hw_ring_replenish(ringh);
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do {
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prefetch((char *)dtr + L1_CACHE_BYTES);
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@ -1588,6 +1585,36 @@ static int vxge_reset_vpath(struct vxgedev *vdev, int vp_id)
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return ret;
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}
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/* Configure CI */
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static void vxge_config_ci_for_tti_rti(struct vxgedev *vdev)
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{
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int i = 0;
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/* Enable CI for RTI */
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if (vdev->config.intr_type == MSI_X) {
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for (i = 0; i < vdev->no_of_vpath; i++) {
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struct __vxge_hw_ring *hw_ring;
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hw_ring = vdev->vpaths[i].ring.handle;
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vxge_hw_vpath_dynamic_rti_ci_set(hw_ring);
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}
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}
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/* Enable CI for TTI */
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for (i = 0; i < vdev->no_of_vpath; i++) {
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struct __vxge_hw_fifo *hw_fifo = vdev->vpaths[i].fifo.handle;
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vxge_hw_vpath_tti_ci_set(hw_fifo);
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/*
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* For Inta (with or without napi), Set CI ON for only one
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* vpath. (Have only one free running timer).
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*/
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if ((vdev->config.intr_type == INTA) && (i == 0))
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break;
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}
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return;
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}
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static int do_vxge_reset(struct vxgedev *vdev, int event)
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{
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enum vxge_hw_status status;
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@ -1753,6 +1780,9 @@ static int do_vxge_reset(struct vxgedev *vdev, int event)
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netif_tx_wake_all_queues(vdev->ndev);
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}
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/* configure CI */
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vxge_config_ci_for_tti_rti(vdev);
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out:
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vxge_debug_entryexit(VXGE_TRACE,
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"%s:%d Exiting...", __func__, __LINE__);
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@ -1793,22 +1823,29 @@ static void vxge_reset(struct work_struct *work)
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*/
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static int vxge_poll_msix(struct napi_struct *napi, int budget)
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{
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struct vxge_ring *ring =
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container_of(napi, struct vxge_ring, napi);
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struct vxge_ring *ring = container_of(napi, struct vxge_ring, napi);
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int pkts_processed;
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int budget_org = budget;
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ring->budget = budget;
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ring->budget = budget;
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ring->pkts_processed = 0;
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vxge_hw_vpath_poll_rx(ring->handle);
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pkts_processed = ring->pkts_processed;
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if (ring->pkts_processed < budget_org) {
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napi_complete(napi);
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/* Re enable the Rx interrupts for the vpath */
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vxge_hw_channel_msix_unmask(
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(struct __vxge_hw_channel *)ring->handle,
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ring->rx_vector_no);
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mmiowb();
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}
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return ring->pkts_processed;
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/* We are copying and returning the local variable, in case if after
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* clearing the msix interrupt above, if the interrupt fires right
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* away which can preempt this NAPI thread */
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return pkts_processed;
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}
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static int vxge_poll_inta(struct napi_struct *napi, int budget)
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@ -1824,6 +1861,7 @@ static int vxge_poll_inta(struct napi_struct *napi, int budget)
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for (i = 0; i < vdev->no_of_vpath; i++) {
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ring = &vdev->vpaths[i].ring;
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ring->budget = budget;
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ring->pkts_processed = 0;
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vxge_hw_vpath_poll_rx(ring->handle);
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pkts_processed += ring->pkts_processed;
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budget -= ring->pkts_processed;
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@ -2054,6 +2092,7 @@ static int vxge_open_vpaths(struct vxgedev *vdev)
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netdev_get_tx_queue(vdev->ndev, 0);
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vpath->fifo.indicate_max_pkts =
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vdev->config.fifo_indicate_max_pkts;
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vpath->fifo.tx_vector_no = 0;
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vpath->ring.rx_vector_no = 0;
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vpath->ring.rx_csum = vdev->rx_csum;
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vpath->ring.rx_hwts = vdev->rx_hwts;
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@ -2079,6 +2118,61 @@ static int vxge_open_vpaths(struct vxgedev *vdev)
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return VXGE_HW_OK;
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}
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/**
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* adaptive_coalesce_tx_interrupts - Changes the interrupt coalescing
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* if the interrupts are not within a range
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* @fifo: pointer to transmit fifo structure
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* Description: The function changes boundary timer and restriction timer
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* value depends on the traffic
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* Return Value: None
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*/
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static void adaptive_coalesce_tx_interrupts(struct vxge_fifo *fifo)
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{
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fifo->interrupt_count++;
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if (jiffies > fifo->jiffies + HZ / 100) {
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struct __vxge_hw_fifo *hw_fifo = fifo->handle;
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fifo->jiffies = jiffies;
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if (fifo->interrupt_count > VXGE_T1A_MAX_TX_INTERRUPT_COUNT &&
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hw_fifo->rtimer != VXGE_TTI_RTIMER_ADAPT_VAL) {
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hw_fifo->rtimer = VXGE_TTI_RTIMER_ADAPT_VAL;
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vxge_hw_vpath_dynamic_tti_rtimer_set(hw_fifo);
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} else if (hw_fifo->rtimer != 0) {
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hw_fifo->rtimer = 0;
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vxge_hw_vpath_dynamic_tti_rtimer_set(hw_fifo);
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}
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fifo->interrupt_count = 0;
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}
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}
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/**
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* adaptive_coalesce_rx_interrupts - Changes the interrupt coalescing
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* if the interrupts are not within a range
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* @ring: pointer to receive ring structure
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* Description: The function increases of decreases the packet counts within
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* the ranges of traffic utilization, if the interrupts due to this ring are
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* not within a fixed range.
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* Return Value: Nothing
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*/
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static void adaptive_coalesce_rx_interrupts(struct vxge_ring *ring)
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{
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ring->interrupt_count++;
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if (jiffies > ring->jiffies + HZ / 100) {
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struct __vxge_hw_ring *hw_ring = ring->handle;
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ring->jiffies = jiffies;
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if (ring->interrupt_count > VXGE_T1A_MAX_INTERRUPT_COUNT &&
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hw_ring->rtimer != VXGE_RTI_RTIMER_ADAPT_VAL) {
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hw_ring->rtimer = VXGE_RTI_RTIMER_ADAPT_VAL;
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vxge_hw_vpath_dynamic_rti_rtimer_set(hw_ring);
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} else if (hw_ring->rtimer != 0) {
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hw_ring->rtimer = 0;
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vxge_hw_vpath_dynamic_rti_rtimer_set(hw_ring);
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}
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ring->interrupt_count = 0;
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}
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}
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/*
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* vxge_isr_napi
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* @irq: the irq of the device.
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@ -2139,24 +2233,39 @@ static irqreturn_t vxge_isr_napi(int irq, void *dev_id)
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#ifdef CONFIG_PCI_MSI
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static irqreturn_t
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vxge_tx_msix_handle(int irq, void *dev_id)
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static irqreturn_t vxge_tx_msix_handle(int irq, void *dev_id)
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{
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struct vxge_fifo *fifo = (struct vxge_fifo *)dev_id;
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adaptive_coalesce_tx_interrupts(fifo);
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vxge_hw_channel_msix_mask((struct __vxge_hw_channel *)fifo->handle,
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fifo->tx_vector_no);
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vxge_hw_channel_msix_clear((struct __vxge_hw_channel *)fifo->handle,
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fifo->tx_vector_no);
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VXGE_COMPLETE_VPATH_TX(fifo);
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vxge_hw_channel_msix_unmask((struct __vxge_hw_channel *)fifo->handle,
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fifo->tx_vector_no);
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mmiowb();
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return IRQ_HANDLED;
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}
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static irqreturn_t
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vxge_rx_msix_napi_handle(int irq, void *dev_id)
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static irqreturn_t vxge_rx_msix_napi_handle(int irq, void *dev_id)
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{
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struct vxge_ring *ring = (struct vxge_ring *)dev_id;
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/* MSIX_IDX for Rx is 1 */
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adaptive_coalesce_rx_interrupts(ring);
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vxge_hw_channel_msix_mask((struct __vxge_hw_channel *)ring->handle,
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ring->rx_vector_no);
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ring->rx_vector_no);
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vxge_hw_channel_msix_clear((struct __vxge_hw_channel *)ring->handle,
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ring->rx_vector_no);
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napi_schedule(&ring->napi);
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return IRQ_HANDLED;
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@ -2173,14 +2282,20 @@ vxge_alarm_msix_handle(int irq, void *dev_id)
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VXGE_HW_VPATH_MSIX_ACTIVE) + VXGE_ALARM_MSIX_ID;
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for (i = 0; i < vdev->no_of_vpath; i++) {
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/* Reduce the chance of loosing alarm interrupts by masking
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* the vector. A pending bit will be set if an alarm is
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* generated and on unmask the interrupt will be fired.
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*/
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vxge_hw_vpath_msix_mask(vdev->vpaths[i].handle, msix_id);
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vxge_hw_vpath_msix_clear(vdev->vpaths[i].handle, msix_id);
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mmiowb();
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status = vxge_hw_vpath_alarm_process(vdev->vpaths[i].handle,
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vdev->exec_mode);
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if (status == VXGE_HW_OK) {
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vxge_hw_vpath_msix_unmask(vdev->vpaths[i].handle,
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msix_id);
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msix_id);
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mmiowb();
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continue;
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}
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vxge_debug_intr(VXGE_ERR,
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@ -2299,6 +2414,9 @@ static int vxge_enable_msix(struct vxgedev *vdev)
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vpath->ring.rx_vector_no = (vpath->device_id *
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VXGE_HW_VPATH_MSIX_ACTIVE) + 1;
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vpath->fifo.tx_vector_no = (vpath->device_id *
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VXGE_HW_VPATH_MSIX_ACTIVE);
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vxge_hw_vpath_msix_set(vpath->handle, tim_msix_id,
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VXGE_ALARM_MSIX_ID);
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}
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@ -2474,8 +2592,9 @@ static int vxge_add_isr(struct vxgedev *vdev)
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"%s:vxge:INTA", vdev->ndev->name);
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vxge_hw_device_set_intr_type(vdev->devh,
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VXGE_HW_INTR_MODE_IRQLINE);
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vxge_hw_vpath_tti_ci_set(vdev->devh,
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vdev->vpaths[0].device_id);
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vxge_hw_vpath_tti_ci_set(vdev->vpaths[0].fifo.handle);
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ret = request_irq((int) vdev->pdev->irq,
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vxge_isr_napi,
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IRQF_SHARED, vdev->desc[0], vdev);
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@ -2745,6 +2864,10 @@ static int vxge_open(struct net_device *dev)
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}
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netif_tx_start_all_queues(vdev->ndev);
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/* configure CI */
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vxge_config_ci_for_tti_rti(vdev);
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goto out0;
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out2:
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@ -3804,7 +3927,7 @@ static void __devinit vxge_device_config_init(
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break;
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case MSI_X:
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device_config->intr_mode = VXGE_HW_INTR_MODE_MSIX;
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device_config->intr_mode = VXGE_HW_INTR_MODE_MSIX_ONE_SHOT;
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||||
break;
|
||||
}
|
||||
|
||||
|
||||
@ -59,11 +59,13 @@
|
||||
#define VXGE_TTI_LTIMER_VAL 1000
|
||||
#define VXGE_T1A_TTI_LTIMER_VAL 80
|
||||
#define VXGE_TTI_RTIMER_VAL 0
|
||||
#define VXGE_TTI_RTIMER_ADAPT_VAL 10
|
||||
#define VXGE_T1A_TTI_RTIMER_VAL 400
|
||||
#define VXGE_RTI_BTIMER_VAL 250
|
||||
#define VXGE_RTI_LTIMER_VAL 100
|
||||
#define VXGE_RTI_RTIMER_VAL 0
|
||||
#define VXGE_FIFO_INDICATE_MAX_PKTS VXGE_DEF_FIFO_LENGTH
|
||||
#define VXGE_RTI_RTIMER_ADAPT_VAL 15
|
||||
#define VXGE_FIFO_INDICATE_MAX_PKTS VXGE_DEF_FIFO_LENGTH
|
||||
#define VXGE_ISR_POLLING_CNT 8
|
||||
#define VXGE_MAX_CONFIG_DEV 0xFF
|
||||
#define VXGE_EXEC_MODE_DISABLE 0
|
||||
@ -107,6 +109,14 @@
|
||||
#define RTI_T1A_RX_UFC_C 50
|
||||
#define RTI_T1A_RX_UFC_D 60
|
||||
|
||||
/*
|
||||
* The interrupt rate is maintained at 3k per second with the moderation
|
||||
* parameters for most traffic but not all. This is the maximum interrupt
|
||||
* count allowed per function with INTA or per vector in the case of
|
||||
* MSI-X in a 10 millisecond time period. Enabled only for Titan 1A.
|
||||
*/
|
||||
#define VXGE_T1A_MAX_INTERRUPT_COUNT 100
|
||||
#define VXGE_T1A_MAX_TX_INTERRUPT_COUNT 200
|
||||
|
||||
/* Milli secs timer period */
|
||||
#define VXGE_TIMER_DELAY 10000
|
||||
@ -247,6 +257,11 @@ struct vxge_fifo {
|
||||
int tx_steering_type;
|
||||
int indicate_max_pkts;
|
||||
|
||||
/* Adaptive interrupt moderation parameters used in T1A */
|
||||
unsigned long interrupt_count;
|
||||
unsigned long jiffies;
|
||||
|
||||
u32 tx_vector_no;
|
||||
/* Tx stats */
|
||||
struct vxge_fifo_stats stats;
|
||||
} ____cacheline_aligned;
|
||||
@ -271,6 +286,10 @@ struct vxge_ring {
|
||||
*/
|
||||
int driver_id;
|
||||
|
||||
/* Adaptive interrupt moderation parameters used in T1A */
|
||||
unsigned long interrupt_count;
|
||||
unsigned long jiffies;
|
||||
|
||||
/* copy of the flag indicating whether rx_csum is to be used */
|
||||
u32 rx_csum:1,
|
||||
rx_hwts:1;
|
||||
@ -286,7 +305,7 @@ struct vxge_ring {
|
||||
|
||||
int vlan_tag_strip;
|
||||
struct vlan_group *vlgrp;
|
||||
int rx_vector_no;
|
||||
u32 rx_vector_no;
|
||||
enum vxge_hw_status last_status;
|
||||
|
||||
/* Rx stats */
|
||||
|
||||
@ -218,6 +218,68 @@ enum vxge_hw_status vxge_hw_vpath_intr_disable(
|
||||
return status;
|
||||
}
|
||||
|
||||
void vxge_hw_vpath_tti_ci_set(struct __vxge_hw_fifo *fifo)
|
||||
{
|
||||
struct vxge_hw_vpath_reg __iomem *vp_reg;
|
||||
struct vxge_hw_vp_config *config;
|
||||
u64 val64;
|
||||
|
||||
if (fifo->config->enable != VXGE_HW_FIFO_ENABLE)
|
||||
return;
|
||||
|
||||
vp_reg = fifo->vp_reg;
|
||||
config = container_of(fifo->config, struct vxge_hw_vp_config, fifo);
|
||||
|
||||
if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
|
||||
config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
|
||||
val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
|
||||
val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
|
||||
fifo->tim_tti_cfg1_saved = val64;
|
||||
writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
|
||||
}
|
||||
}
|
||||
|
||||
void vxge_hw_vpath_dynamic_rti_ci_set(struct __vxge_hw_ring *ring)
|
||||
{
|
||||
u64 val64 = ring->tim_rti_cfg1_saved;
|
||||
|
||||
val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
|
||||
ring->tim_rti_cfg1_saved = val64;
|
||||
writeq(val64, &ring->vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
|
||||
}
|
||||
|
||||
void vxge_hw_vpath_dynamic_tti_rtimer_set(struct __vxge_hw_fifo *fifo)
|
||||
{
|
||||
u64 val64 = fifo->tim_tti_cfg3_saved;
|
||||
u64 timer = (fifo->rtimer * 1000) / 272;
|
||||
|
||||
val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
|
||||
if (timer)
|
||||
val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
|
||||
VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(5);
|
||||
|
||||
writeq(val64, &fifo->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
|
||||
/* tti_cfg3_saved is not updated again because it is
|
||||
* initialized at one place only - init time.
|
||||
*/
|
||||
}
|
||||
|
||||
void vxge_hw_vpath_dynamic_rti_rtimer_set(struct __vxge_hw_ring *ring)
|
||||
{
|
||||
u64 val64 = ring->tim_rti_cfg3_saved;
|
||||
u64 timer = (ring->rtimer * 1000) / 272;
|
||||
|
||||
val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(0x3ffffff);
|
||||
if (timer)
|
||||
val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(timer) |
|
||||
VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF(4);
|
||||
|
||||
writeq(val64, &ring->vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
|
||||
/* rti_cfg3_saved is not updated again because it is
|
||||
* initialized at one place only - init time.
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* vxge_hw_channel_msix_mask - Mask MSIX Vector.
|
||||
* @channeh: Channel for rx or tx handle
|
||||
@ -253,6 +315,23 @@ vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channel, int msix_id)
|
||||
&channel->common_reg->clear_msix_mask_vect[msix_id%4]);
|
||||
}
|
||||
|
||||
/**
|
||||
* vxge_hw_channel_msix_clear - Unmask the MSIX Vector.
|
||||
* @channel: Channel for rx or tx handle
|
||||
* @msix_id: MSI ID
|
||||
*
|
||||
* The function unmasks the msix interrupt for the given msix_id
|
||||
* if configured in MSIX oneshot mode
|
||||
*
|
||||
* Returns: 0
|
||||
*/
|
||||
void vxge_hw_channel_msix_clear(struct __vxge_hw_channel *channel, int msix_id)
|
||||
{
|
||||
__vxge_hw_pio_mem_write32_upper(
|
||||
(u32) vxge_bVALn(vxge_mBIT(msix_id >> 2), 0, 32),
|
||||
&channel->common_reg->clr_msix_one_shot_vec[msix_id % 4]);
|
||||
}
|
||||
|
||||
/**
|
||||
* vxge_hw_device_set_intr_type - Updates the configuration
|
||||
* with new interrupt type.
|
||||
@ -2190,20 +2269,15 @@ vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id,
|
||||
|
||||
if (vpath->hldev->config.intr_mode ==
|
||||
VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) {
|
||||
__vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
|
||||
VXGE_HW_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN,
|
||||
0, 32), &vp_reg->one_shot_vect0_en);
|
||||
__vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
|
||||
VXGE_HW_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN,
|
||||
0, 32), &vp_reg->one_shot_vect1_en);
|
||||
}
|
||||
|
||||
if (vpath->hldev->config.intr_mode ==
|
||||
VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) {
|
||||
__vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
|
||||
VXGE_HW_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN,
|
||||
0, 32), &vp_reg->one_shot_vect2_en);
|
||||
|
||||
__vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
|
||||
VXGE_HW_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN,
|
||||
0, 32), &vp_reg->one_shot_vect3_en);
|
||||
}
|
||||
}
|
||||
|
||||
@ -2228,6 +2302,32 @@ vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vp, int msix_id)
|
||||
&hldev->common_reg->set_msix_mask_vect[msix_id % 4]);
|
||||
}
|
||||
|
||||
/**
|
||||
* vxge_hw_vpath_msix_clear - Clear MSIX Vector.
|
||||
* @vp: Virtual Path handle.
|
||||
* @msix_id: MSI ID
|
||||
*
|
||||
* The function clears the msix interrupt for the given msix_id
|
||||
*
|
||||
* Returns: 0,
|
||||
* Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
|
||||
* status.
|
||||
* See also:
|
||||
*/
|
||||
void vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id)
|
||||
{
|
||||
struct __vxge_hw_device *hldev = vp->vpath->hldev;
|
||||
|
||||
if ((hldev->config.intr_mode == VXGE_HW_INTR_MODE_MSIX_ONE_SHOT))
|
||||
__vxge_hw_pio_mem_write32_upper(
|
||||
(u32) vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32),
|
||||
&hldev->common_reg->clr_msix_one_shot_vec[msix_id % 4]);
|
||||
else
|
||||
__vxge_hw_pio_mem_write32_upper(
|
||||
(u32) vxge_bVALn(vxge_mBIT((msix_id >> 2)), 0, 32),
|
||||
&hldev->common_reg->clear_msix_mask_vect[msix_id % 4]);
|
||||
}
|
||||
|
||||
/**
|
||||
* vxge_hw_vpath_msix_unmask - Unmask the MSIX Vector.
|
||||
* @vp: Virtual Path handle.
|
||||
|
||||
@ -2142,6 +2142,10 @@ void vxge_hw_device_clear_tx_rx(
|
||||
* Virtual Paths
|
||||
*/
|
||||
|
||||
void vxge_hw_vpath_dynamic_rti_rtimer_set(struct __vxge_hw_ring *ring);
|
||||
|
||||
void vxge_hw_vpath_dynamic_tti_rtimer_set(struct __vxge_hw_fifo *fifo);
|
||||
|
||||
u32 vxge_hw_vpath_id(
|
||||
struct __vxge_hw_vpath_handle *vpath_handle);
|
||||
|
||||
@ -2245,6 +2249,8 @@ void
|
||||
vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vpath_handle,
|
||||
int msix_id);
|
||||
|
||||
void vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id);
|
||||
|
||||
void vxge_hw_device_flush_io(struct __vxge_hw_device *devh);
|
||||
|
||||
void
|
||||
@ -2269,6 +2275,9 @@ vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channelh, int msix_id);
|
||||
void
|
||||
vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channelh, int msix_id);
|
||||
|
||||
void
|
||||
vxge_hw_channel_msix_clear(struct __vxge_hw_channel *channelh, int msix_id);
|
||||
|
||||
void
|
||||
vxge_hw_channel_dtr_try_complete(struct __vxge_hw_channel *channel,
|
||||
void **dtrh);
|
||||
@ -2282,7 +2291,8 @@ vxge_hw_channel_dtr_free(struct __vxge_hw_channel *channel, void *dtrh);
|
||||
int
|
||||
vxge_hw_channel_dtr_count(struct __vxge_hw_channel *channel);
|
||||
|
||||
void
|
||||
vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id);
|
||||
void vxge_hw_vpath_tti_ci_set(struct __vxge_hw_fifo *fifo);
|
||||
|
||||
void vxge_hw_vpath_dynamic_rti_ci_set(struct __vxge_hw_ring *ring);
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user