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e1000e: Do not read ICR in Other interrupt
Removes the ICR read in the other interrupt handler, uses EIAC to autoclear the Other bit from ICR and IMS. This allows us to avoid interference with Rx and Tx interrupts in the Other interrupt handler. The information read from ICR is not needed. IMS is configured such that the only interrupt cause that can trigger the Other interrupt is Link Status Change. Signed-off-by: Benjamin Poirier <bpoirier@suse.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -1905,23 +1905,14 @@ static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
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struct net_device *netdev = data;
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struct e1000_adapter *adapter = netdev_priv(netdev);
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struct e1000_hw *hw = &adapter->hw;
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u32 icr = er32(ICR);
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if (icr & adapter->eiac_mask)
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ew32(ICS, (icr & adapter->eiac_mask));
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if (icr & E1000_ICR_OTHER) {
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if (!(icr & E1000_ICR_LSC))
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goto no_link_interrupt;
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hw->mac.get_link_status = true;
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/* guard against interrupt when we're going down */
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if (!test_bit(__E1000_DOWN, &adapter->state))
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mod_timer(&adapter->watchdog_timer, jiffies + 1);
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}
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no_link_interrupt:
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if (!test_bit(__E1000_DOWN, &adapter->state))
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ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
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/* guard against interrupt when we're going down */
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if (!test_bit(__E1000_DOWN, &adapter->state)) {
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mod_timer(&adapter->watchdog_timer, jiffies + 1);
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ew32(IMS, E1000_IMS_OTHER);
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}
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return IRQ_HANDLED;
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}
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@ -2021,6 +2012,7 @@ static void e1000_configure_msix(struct e1000_adapter *adapter)
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hw->hw_addr + E1000_EITR_82574(vector));
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else
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writel(1, hw->hw_addr + E1000_EITR_82574(vector));
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adapter->eiac_mask |= E1000_IMS_OTHER;
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/* Cause Tx interrupts on every write back */
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ivar |= (1 << 31);
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@ -2249,7 +2241,7 @@ static void e1000_irq_enable(struct e1000_adapter *adapter)
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if (adapter->msix_entries) {
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ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
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ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
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ew32(IMS, adapter->eiac_mask | E1000_IMS_LSC);
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} else if ((hw->mac.type == e1000_pch_lpt) ||
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(hw->mac.type == e1000_pch_spt)) {
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ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
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