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MIPS: uasm: Add mflo uasm instruction

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It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
Markos Chandras 2014-04-14 15:42:31 +01:00 committed by Ralf Baechle
parent a8e897ad00
commit 16d21a812f
5 changed files with 11 additions and 5 deletions
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1
arch/mips/include/asm/uasm.h
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@ -133,6 +133,7 @@ Ip_u2s3u1(_lw);
Ip_u3u1u2(_lwx); Ip_u3u1u2(_lwx);
Ip_u1u2u3(_mfc0); Ip_u1u2u3(_mfc0);
Ip_u1(_mfhi); Ip_u1(_mfhi);
Ip_u1(_mflo);
Ip_u1u2u3(_mtc0); Ip_u1u2u3(_mtc0);
Ip_u3u1u2(_mul); Ip_u3u1u2(_mul);
Ip_u3u1u2(_or); Ip_u3u1u2(_or);

1
arch/mips/include/uapi/asm/inst.h
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@ -316,6 +316,7 @@ enum mm_32axf_minor_op {
mm_mfhi32_op = 0x035, mm_mfhi32_op = 0x035,
mm_jalr_op = 0x03c, mm_jalr_op = 0x03c,
mm_tlbr_op = 0x04d, mm_tlbr_op = 0x04d,
mm_mflo32_op = 0x075,
mm_jalrhb_op = 0x07c, mm_jalrhb_op = 0x07c,
mm_tlbwi_op = 0x08d, mm_tlbwi_op = 0x08d,
mm_tlbwr_op = 0x0cd, mm_tlbwr_op = 0x0cd,

1
arch/mips/mm/uasm-micromips.c
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@ -89,6 +89,7 @@ static struct insn insn_table_MM[] = {
{ insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM }, { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
{ insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD }, { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD },
{ insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS }, { insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS },
{ insn_mflo, M(mm_pool32a_op, 0, 0, 0, mm_mflo32_op, mm_pool32axf_op), RS },
{ insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD }, { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD },
{ insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD }, { insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD },
{ insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD }, { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD },

1
arch/mips/mm/uasm-mips.c
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@ -96,6 +96,7 @@ static struct insn insn_table[] = {
{ insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD }, { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
{ insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET}, { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
{ insn_mfhi, M(spec_op, 0, 0, 0, 0, mfhi_op), RD }, { insn_mfhi, M(spec_op, 0, 0, 0, 0, mfhi_op), RD },
{ insn_mflo, M(spec_op, 0, 0, 0, 0, mflo_op), RD },
{ insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET}, { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
{ insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD}, { insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
{ insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },

12
arch/mips/mm/uasm.c
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@ -51,11 +51,12 @@ enum opcode {
insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld, insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld,
insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_ldx, insn_lh, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx,
insn_mfc0, insn_mfhi, insn_mtc0, insn_mul, insn_or, insn_ori, insn_pref, insn_mfc0, insn_mfhi, insn_mflo, insn_mtc0, insn_mul, insn_or,
insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd,
insn_sltiu, insn_sltu, insn_sra, insn_srl, insn_srlv, insn_subu, insn_sll, insn_sllv, insn_sltiu, insn_sltu, insn_sra, insn_srl,
insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp,
insn_tlbwr, insn_wait, insn_wsbh, insn_xor, insn_xori, insn_yield, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_wsbh, insn_xor,
insn_xori, insn_yield,
}; };
struct insn { struct insn {
@ -276,6 +277,7 @@ I_u1s2(_lui)
I_u2s3u1(_lw) I_u2s3u1(_lw)
I_u1u2u3(_mfc0) I_u1u2u3(_mfc0)
I_u1(_mfhi) I_u1(_mfhi)
I_u1(_mflo)
I_u1u2u3(_mtc0) I_u1u2u3(_mtc0)
I_u3u1u2(_mul) I_u3u1u2(_mul)
I_u2u1u3(_ori) I_u2u1u3(_ori)